DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-16 are pending.
Response to Arguments
The rejection of Claim 11 under 35 USC §112(a) is withdrawn.
The remainder of Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7, 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ozaki (US 2019/0130860) in view of Bansho (JP 2015197581). All reference is to Ozaki unless otherwise indicated.
Regarding Claims 1 and 9 (Currently Amended), Ozaki teaches a driving method and a display device comprising:
a backlight unit [fig. 1 @400] including a light-emitting element [fig. 1 @404];
a plurality of pixels [fig. 1 @502], each comprising
a pixel electrode [fig. 3 @Node A (Seventh terminal)], a common electrode [fig. 3 @sixth terminal], and a liquid crystal layer [fig. 3 @436] between the pixel electrode and the common electrode and
arranged so that light from the backlight unit is incident [¶0031, “the light source control part 402 controls irradiation of light to the display panel 500 and light shielding. The light source part 404 includes a light source. The light source is facing an electro-optical element described later”]
and arranged in a matrix form having a plurality of rows [horizontal or x direction] and a plurality of columns [vertical or y direction, ¶0036, “The display region 504 includes a plurality of pixels 502. The plurality of pixels 502 are arranged in one direction and along a direction which intersects this direction”];
a gate-line driver circuit [fig. 1 @508] and a signal-line driver circuit [fig. 1 @506] each electrically connected to the plurality of pixels [fig. 3 @410 and 409];
and a control substrate [fig. 1 @514] electrically connected to the backlight unit [fig. 1 @400 via 512 and 513], the gate-line driver circuit, and the signal-line driver circuit [¶0034, “A display region 504, an image signal line drive circuit 506, a scanning signal line drive circuit 508, a scanning signal line drive circuit 510 and a control circuit 122 are formed above a substrate 514. The connector 512 is connected to the substrate 514”], wherein
the plurality of rows [fig. 2 @G1-Gn] is composed of a plurality of row groups [fig. 2 @G1-Gn] having the same number of rows [one row per group] and sequentially arranged in a column direction [fig. 2 illustrates rows extending in the column direction], and
the control substrate [fig. 1 @514] is configured to, in a first frame period [fig. 5 @ 1F],
simultaneously supply the same potential [fig. 4 illustrates WAL causing simultaneous gate on signals to all pixels during time Tawr] to all of the plurality of pixels to perform a pre-charge [¶0049, “WAL is a signal line supplied with a first signal which is supplied to the gate of the transistor 432. The first signal is a signal for turning the transistor 432 to an ON state during a period Tawr before a potential of the signal supplied to the VCOMS changes due to common inversion … By turning the transistor 432 to an ON state in the period Tawr … a pixel is written with the maximum value of the fluctuation of the amplitude of the signal supplied to the VCOMS”], and
sequentially supply an image signal [fig. 4 @Gradation voltage of PIX] to every row group after the pre-charge is completed [fig. 4 illustrates sequential row driving, from G1 to G480, following Tawr (pre-charge period)]
so that the gate-line driver circuit [fig. 1 @508] and the signal-line driver circuit [fig. 1 @506] are supplied with a control signal [fig. 4 @GST] for supplying the image signal to the pixels [¶0050, “GST is a signal line serving as a trigger for generating a signal for writing a voltage corresponding to an image signal corresponding to each pixel … ” GST is supplied to the scanning signal line drive circuit 508 and/or the scanning signal line drive circuit 51”] in each of the plurality of row groups [fig. 4 @G1 to G480]
Ozaki does not teach a magnitude of the potential supplied in the pre-charge with respect to a potential supplied to a common electrode is smaller than a magnitude of a potential of the image signal providing a maximum gradation
Bansho teaches a magnitude [4v] of the potential supplied in the pre-charge [fig. 15 @Vpr1 and Vpr2 are 4 volts] with respect to a potential supplied to a common electrode [fig. 15 @VcomH for Vpr1 and VcomL for Vpr2] is smaller than a magnitude [8v] of a potential of the image signal providing a maximum gradation [¶0076 teaches a voltage difference of 8 volts causes the pixel to display Black (maximum gradation potential)]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of setting the precharge potential to a predetermined reference potential, as taught by Bansho, into the method and display device taught by Ozaki in order to reduce potential fluctuation of the data line and thereby suppress degradation of image quality (Bansho: ¶0082).
Regarding Claims 2 and 10 (Original), Ozaki in view of Bansho teaches the method according to Claim 1 and the display device according to Claim 9, wherein the control substrate is further configured to,
in the first frame period [fig. 4 @f-th frame], turn on the light-emitting element [fig. 1 @404] after the image signal [ fig. 4 illustrates Tblon occurs after G480 image data loaded into pixel] is supplied to all of the plurality of pixels [¶0069, “BLPS is a signal line for controlling ON/OFF of the light source part 404 … BLPS is supplied with the maximum value of a fluctuation of an amplitude of a signal during the period Tblon”].
Regarding Claims 3 (Original) and 11 (Currently Amended), Ozaki in view of Bansho teaches the method according to Claim 2 and the display device according to Claim 10 wherein the control substrate is further configured to,
in a second frame period [fig. 4 @ f-1-th frame is construed identical to f+1-th frame] following the first frame period [fig. 4 @f-th frame], turn off the light-emitting element before performing the pre-charge [fig. 4 illustrates Tblon turns off lighting elements before Tawr (pre-charge period)].
Regarding Claims 4 and 12 (Original), Ozaki in view of Bansho teaches the method according to Claim 1 and the display device according to Claim 9, wherein
a period [fig. 4 @Tblank] after completing the supply of the image signal to all of the plurality of pixels and before turning on the light-emitting element [fig. 4 @Tblon] is equal to or greater than 10% [fig. 4 @Tblank is construed as 10% of the illustrated frame period] and equal to or less than 50% of the first frame period [¶0055, “Tblank is a period from when a signal is supplied to G480 until the light source part 404 is turned ON”].
Regarding Claims 5 and 13 (Currently Amended), Ozaki in view of Bansho teaches the method according to Claim 1 and the display device according to Claim 9, wherein
the potential supplied in the pre-charge is supplied to the pixel electrode [¶0049, “By turning the transistor 432 to an ON state in the period Tawr, the maximum value of the fluctuation of the amplitude of the signal supplied to the VCOMS can be written to the node A”, fig. 3 @Seventh terminal], and
the potential is the same as a potential supplied to the common electrode [fig. 3 @VCOMS].
Regarding Claims 6 and 14 (Currently Amended), Ozaki in view of Bansho teaches the method according to Claim 1 and the display device according to Claim 9, wherein
the potential supplied in the pre-charge is supplied to the pixel electrode [¶0049, “By turning the transistor 432 to an ON state in the period Tawr, the maximum value of the fluctuation of the amplitude of the signal supplied to the VCOMS can be written to the node A”, fig. 3 @Seventh terminal], and
the potential [fig. 5 voltage polarity during Tawr (frame 1F) is positive] has the same polarity as a potential of the image signal [fig. 5 illustrates polarity of DIN is same as VCOM during frame 1F] with respect to a potential supplied to the common electrode.
Regarding Claims 7 and 15 (Currently Amended), Ozaki in view of Bansho teaches the method according to Claim 1 and the display device according to Claim 9, wherein
a polarity of a potential of the image signal [fig. 5 illustrates image data (gradation voltage) polarity remains positive in each frame] with respect to a potential supplied to the common electrode is different [¶0025 teaches common inversion driving] between the first frame period and a second frame period following the first frame period [fig. 5 illustrates VCOMS polarity inverting (positive to negative) from frame 1F to adjacent frame].
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ozaki in view of Bansho and Chen (US 2019/0172399). All reference is to Ozaki unless otherwise indicated.
Regarding Claims 8 and 16 (Original), Ozaki in view of Bansho teaches the method according to Claim 1 and the display device according to Claim 9
Ozaki does not teach the number of rows of each of the plurality of row groups is equal to or greater than 2 and equal to or less than 4
Chen teaches a number of rows [fig. 19 @row (1-3060)] of each of a plurality of row groups [fig. 19 @Gate Block (1-765)] is equal to or greater than 2 and equal to or less than 4 [fig. 19 illustrates each Gate Block (group) comprises four rows]
Before the application was filed it would have been obvious to one of ordinary skill in the art to incorporate the concept of controlling multiple rows of an active matrix display as a group, as taught by Chen, into the method and display device taught by Ozaki in view of Bansho in order to display content of different resolutions in different display areas (Chen: ¶0002).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Douglas Wilson whose telephone number is (571)272-5640. The Examiner can normally be reached 1000-1800 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Douglas Wilson/Primary Examiner, Art Unit 2622
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