DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statements, dated 6/2/25 and 12/14/25, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
2. REJECTIONS NOT BASED ON PRIOR ART
a. DEFICIENCIES IN THE CLAIMED SUBJECT MATTER
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 12321271. Although the claims at issue are not identical, they are not patentably distinct from each other because, as an example, claim 1 of the US Patent would anticipate claim 1 of the instant application. The dependent claims and other independent claims of the instant application (claims 2-19) would be obvious in view of claims 2-21 of the US Patent for at least the reasoning set forth above and thus are rejected under a similar rationale.
3. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rangarajan (US 20120005524).
With respect to claim 1, the Rangarajan reference teaches a processor, (see fig. 2a, processing system 200) comprising:
a plurality of cores comprising a first core and a second core; (e.g. Fig. 2a; and paragraph 25, where processors 201_1 through 201_X)
a distributed cache comprising a plurality of cache slices including a first cache slice and a second cache slice; (see Fig. 2a; and paragraph 36, where there is a TAG value in combination with a cache slice ID value can uniquely identify any cache line across the distributed cache slices) and
a first interconnect between the first cache slice and the second cache slice, (e.g. Fig. 2a; paragraph 20, where "flows" of cache line snoop requests 251_1 through 251_Y are observed that extend through network 204 to respective cache agents 203_1 through 203_Y of cache slices 202_1 through 202_Y)
wherein the distributed cache is configured to cache a copy of data stored at a plurality of memory addresses of a memory, (paragraph 7, where the hashing function used by the hashing engine 111 may be designed to evenly spread the various addresses of the field of potential cache line addresses across the cache slices 102_1 through 102_Y. The set of cache slices 102_1 through 102_Y are sometimes collectively referred to as the "last level cache" (LLC) 112)
wherein the first cache slice is connected to the first core, and the second cache slice is connected to the second core, (e.g. fig. 2a; where paragraph 26, where network 204 is implemented with a ring architecture that includes at least two oppositely directed rings. Here, each processor may have its own associated access to the rings and an outgoing request is placed on the ring having the shortest path to the request's destination)
wherein the first cache slice is configured to cache a copy of data stored at a first set of memory addresses of the plurality of memory addresses, (paragraph 7, where the hashing function used by the hashing engine 111 may be designed to evenly spread the various addresses of the field of potential cache line addresses across the cache slices 102_1 through 102_Y. The set of cache slices 102_1 through 102_Y are sometimes collectively referred to as the "last level cache" (LLC) 112)
wherein the second cache slice is configured to cache a copy of data stored at a second, different, set of memory addresses of the plurality of memory addresses, (paragraph 7, where the hashing function used by the hashing engine 111 may be designed to evenly spread the various addresses of the field of potential cache line addresses across the cache slices 102_1 through 102_Y. The set of cache slices 102_1 through 102_Y are sometimes collectively referred to as the "last level cache" (LLC) 112 [i.e. each cache slice stores ‘different’ addresses to spread the data])
wherein the first cache slice is configured to:
receive, from the first core, a first memory access request specifying a target memory address of the memory, wherein the plurality of memory addresses includes the first target memory address; (paragraph 6, where when a processor looks for an item of information in its local cache and a "miss" occurs (or, if the processors 101_1 through 101_X simply do not include their own respective local cache), one of the cache slices 102_1 through 102_Y is snooped for the desired information. The particular cache slice that is snooped is determined from the address of the information (e.g., the address of the desired cache line))
identify based on the target memory address a target cache slice among the first and second cache slices, wherein the target cache slice is the cache slice configured to cache a copy of the data stored at the target memory address; (paragraph 6, where when a processor looks for an item of information in its local cache and a "miss" occurs (or, if the processors 101_1 through 101_X simply do not include their own respective local cache), one of the cache slices 102_1 through 102_Y is snooped for the desired information. The particular cache slice that is snooped is determined from the address of the information (e.g., the address of the desired cache line)) and
responsive to the target cache slice being identified as the second cache slice, forward the first memory access request to the target cache slice; (paragraph 7, where if a cache miss occurs at processor 101_1, a request is constructed for the desired cache line, and, hash engine logic circuitry 111 performs a hash function on the address to determine which cache slice is the appropriate cache slice for the particular address)
wherein the first interconnect is configured to convey the first memory access request to the second cache slice. (paragraph 20, where flows" of cache line snoop requests 251_1 through 251_Y are observed that extend through network 204 to respective cache agents 203_1 through 203_Y of cache slices 202_1 through 202_Y)
With respect to claim 2, the Rangarajan reference teaches the processor of claim 1, wherein the first cache slice comprises a first cache bank configured to cache the copy of the data stored at the first set of memory addresses, and a first crossbar connected to the first cache bank, (paragraph 7, where the hashing function used by the hashing engine 111 may be designed to evenly spread the various addresses of the field of potential cache line addresses across the cache slices 102_1 through 102_Y. The set of cache slices 102_1 through 102_Y are sometimes collectively referred to as the "last level cache" (LLC) 112)
wherein the second cache slice comprises a second cache bank configured to cache the copy of the data stored at the second set of memory addresses, (paragraph 7, where the hashing function used by the hashing engine 111 may be designed to evenly spread the various addresses of the field of potential cache line addresses across the cache slices 102_1 through 102_Y. The set of cache slices 102_1 through 102_Y are sometimes collectively referred to as the "last level cache" (LLC) 112) and
a second crossbar connected to the second cache bank, (e.g. fig. 2a; internal network 204)
wherein the first crossbar is configured to:
identify based on the target memory address a target cache bank, wherein the target cache bank is the cache bank configured to cache the copy of the data stored at the target memory address; and forward the first memory access request to the target cache bank. (paragraph 7, where the request is then directed over network 104 to the cache agent for the appropriate cache slice (e.g. cache agent 103_1 if cache slice 102_1 is the targeted slice). The cache agent snoops the targeted cache slice, and, if the desired cache line is found it is sent over network 104 to processor 101_1)
With respect to claim 3, the Rangarajan reference teaches the processor of claim 2, wherein the first crossbar is configured to transmit the first memory access request to the second crossbar via the first interconnect when the target cache bank is identified as the second cache bank, and wherein the second crossbar is configured to: receive, via the first interconnect, the first memory access request when the target cache bank is the second cache bank; and send, to the second cache bank, the first memory access request when the target cache bank is the second cache bank. (paragraph 7, where the request is then directed over network 104 to the cache agent for the appropriate cache slice (e.g. cache agent 103_1 if cache slice 102_1 is the targeted slice). The cache agent snoops the targeted cache slice, and, if the desired cache line is found it is sent over network 104 to processor 101_1; and paragraph 20, where flows" of cache line snoop requests 251_1 through 251_Y are observed that extend through network 204 to respective cache agents 203_1 through 203_Y of cache slices 202_1 through 202_Y))
With respect to claim 4, the Rangarajan reference teaches the processor of claim 2, wherein the processor further comprises: a third core; a third cache slice; and a second interconnect between the second cache slice and the third cache slice; wherein the third cache slice is connected to the third core; wherein the third cache slice comprises a third cache bank configured to cache a copy of data stored at a third set of memory addresses of the plurality of memory addresses, and a third crossbar connected to the third cache bank; wherein the first crossbar is configured to transmit the first memory access request to the second crossbar via the first interconnect when the third cache bank is identified as the target cache bank; wherein the second crossbar is configured to transmit the first memory access request to the third crossbar via the second interconnect when the target cache bank is identified as the third cache bank; and wherein the third crossbar is configured to send, to the third cache bank, the first memory access request when the target cache bank is identified as the third cache bank. (paragraph 7, where the hashing function used by the hashing engine 111 may be designed to evenly spread the various addresses of the field of potential cache line addresses across the cache slices 102_1 through 102_Y. The set of cache slices 102_1 through 102_Y are sometimes collectively referred to as the "last level cache" (LLC) 112; and paragraph 20, where flows" of cache line snoop requests 251_1 through 251_Y are observed that extend through network 204 to respective cache agents 203_1 through 203_Y of cache slices 202_1 through 202_Y) [The Examiner notes this claim merely recites a ‘third cache slice’ and their interconnections and rejected under the same rationale as the claims above])
With respect to claim 5, the Rangarajan reference teaches the processor of claim 4, wherein each cache bank is associated with an identifier, wherein the first crossbar is configured to use a hash function, wherein the hash function is configured to map each memory address in the memory to the identifier of the cache bank configured to cache a copy of the data stored at that memory address, and wherein the first crossbar is configured to use the hash function to identify the target cache bank based on the target memory address. (paragraph 27, where the hashing engine 211 is implemented in a centralized fashion such that cache slice snoop requests generated by any of the multiple processors 201_1 through 201_X are processed by the same hashing engine 211 to determine the target cache slice. Alternatively, the hashing engine 211 may be implemented in a distributed fashion. For example, each processor may have its own dedicated hashing engine for determining the target cache slice for the cache slice snoop requests that it generates. In this case, notice of a failing cache slice should be broadcast to each hashing engine instance, and, in response, each hashing engine instance should be designed to determine the same new cache slice for the affected cache line addresses and implement the same hashing algorithm modification)
With respect to claim 6, the Rangarajan reference teaches the processor of claim 5, wherein the processor is partitionable to partition the cores into at least a first domain comprising the first core, the second core, the first cache slice and the second cache slice, and a second domain comprising the third core and the third cache slice, wherein the first crossbar and the second crossbar are configured to use a first hash function, and the third crossbar is configured to use a second hash function, wherein the first hash function is configured such that: for any target memory address, the first crossbar can identify the first cache bank or the second cache bank as the target cache bank, and cannot identify the third cache bank as the target cache bank; and for any target memory address, the second crossbar can identify the first cache bank or the second cache bank as the target cache bank, and cannot identify the third cache bank as the target cache bank; wherein the second hash function is configured such that, for any target memory address, the third crossbar can identify the third cache bank as the target cache bank, and cannot identify the first cache bank or the second cache bank as the target cache bank. (paragraph 22, where the hashing engine 211 is reconfigured such that its internal hashing function redirects cache line addresses that were originally being directed to cache slice 202_1 (i.e., the failing cache slice) to another, properly working cache slice. For the sake of example, assume that cache slice 202_2 is the newly appointed cache slice that will receive cache lines whose addresses originally caused them to be directed to cache slice 202_1 [The Examiner notes the use of a ‘internal hashing function’ to use within its processing system])
With respect to claim 7, the Rangarajan reference teaches the processor of claim 1, wherein the plurality of cache slices are connected in one of: a linear topology, wherein at least two cache slices are each directly connected to exactly one other cache slice, and optionally wherein at least one cache slice is directly connected to exactly two other cache slices; a ring topology, wherein each cache slice is directly connected to exactly two other cache slices to define the ring topology; a partially cross-linked ring topology, wherein each cache slice is directly connected to at least two other cache slices to define the ring topology, wherein at least two cache slices are each directly connected to exactly two other cache slices, and wherein at least two cache slices are each directly connected to at least three other cache slices; a densely cross-linked ring topology, wherein each cache slice is directly connected to at least three other cache slices, and wherein at least two cache slices are not directly connected to one another; a fully connected topology, in which each cache slice is directly connected to every other cache slice; and a hybrid topology, wherein at least one cache slice is directly connected to at least three other cache slices, and wherein at least one cache slice is directly connected to exactly one other cache slice. (paragraph 26, where network 204 is implemented with a ring architecture that includes at least two oppositely directed rings. Here, each processor may have its own associated access to the rings and an outgoing request is placed on the ring having the shortest path to the request's destination. Alternatively, access to the network 204 from the processors may be accomplished at a single point of access. Network 204 may alternatively take on various other topological forms besides ring (e.g., full mesh, nodal hop, shared media bus, etc.) [which satifies the ‘one of’ limitation])
With respect to claim 8, the Rangarajan reference teaches the processor of claim 1, wherein the first cache slice is directly connected to the first core and the second cache slice is directly connected to the second core. (see fig. 1; and paragraph 6, where when a processor looks for an item of information in its local cache and a "miss" occurs (or, if the processors 101_1 through 101_X simply do not include their own respective local cache), one of the cache slices 102_1 through 102_Y is snooped for the desired information. The particular cache slice that is snooped is determined from the address of the information (e.g., the address of the desired cache line); and paragraph 7, where the request is then directed over network 104 to the cache agent for the appropriate cache slice (e.g. cache agent 103_1 if cache slice 102_1 is the targeted slice). The cache agent snoops the targeted cache slice, and, if the desired cache line is found it is sent over network 104 to processor 101_1)
Claims 9-15 are the method implementation of claims 1-8, and rejected under a similar rationale as shown in the rejections above.
Claim 16 is “a method of manufacturing, using an integrated circuit manufacturing system, a processor as claimed in claim 1, the method comprising inputting to an integrated circuit manufacturing system an integrated circuit definition dataset that, when processed in said integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture said graphics processing system” implementation of claims 1-8, and rejected under a similar rationale as shown in the rejections above. The Examiner notes paragraph 10 of the Rangarajan reference discusses manufacturing of a processor.
Claim 17 is “a non-transitory computer readable storage medium having stored thereon computer readable code configured to cause the method of claim 9 to be performed when the code is run” implementation of claims 1-8, and rejected under a similar rationale as shown in the rejections above. The Examiner notes paragraph 52 of the Rangarajan reference discusses program code such as machine-executable instructions that cause a machine that executes instructions to perform certain functions.
Claim 18 is “a non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a processor” implementation of claims 1-8, and rejected under a similar rationale as shown in the rejections above. The Examiner notes paragraph 52 of the Rangarajan reference discusses program code such as machine-executable instructions that cause a machine that executes instructions to perform certain functions.
Claim 19 is “a non-transitory computer readable storage medium having stored thereon a computer readable description of a processor as claimed in claim 1that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the processor”implementation of claims 1-8, and rejected under a similar rationale as shown in the rejections above. The Examiner notes paragraph 52 of the Rangarajan reference discusses program code such as machine-executable instructions that cause a machine that executes instructions to perform certain functions.
Claim 20 is “an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable description of a processor as claimed in claim 1; a layout processing system configured to process the computer readable description so as to generate a circuit layout description of an integrated circuit embodying the processor; and an integrated circuit generation system configured to manufacture the processor according to the circuit layout description” implementation of claims 1-8, and rejected under a similar rationale as shown in the rejections above. The Examiner notes paragraph 10 of the Rangarajan reference discusses manufacturing of a processor.
3. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Gandhi (US 20200089611), which teaches a method, computer readable medium, and system that are disclosed for a distributed cache that provides multiple processing units with fast access to a portion of data, which is stored in local memory. The distributed cache is composed of multiple smaller caches, and each of the smaller caches is associated with at least one processing unit. In addition to a shared crossbar network through which data is transferred between processing units and the smaller caches, a dedicated connection is provided between two or more smaller caches that form a partner cache set. Transferring data through the dedicated connections reduces congestion on the shared crossbar network. Reducing congestion on the shared crossbar network increases the available bandwidth and allows the number of processing units to increase. A coherence protocol is defined for accessing data stored in the distributed cache and for transferring data between the smaller caches of a partner cache set;
LeCrone (US 10482023), which teaches processing an I/O operation may include the host selecting one of the available paths over which to send each I/O operation to the data storage system. The selected path may be to a particular director that has responsibility for cache slot allocation and locally accessing the cache slot predicted to include the data of the I/O operation. The host may understand the cache slot allocation algorithm used on the data storage system and how cache slots are allocated for particular logical devices and tracks or locations on the logical devices. The host may direct I/Os down a path to a particular director that has, or will allocate, the cache slot used for the I/Os. There may be multiple directors in a data storage system including a distributed global memory. Each director may locally access a group of cache slots and communicate over a fabric to access the distributed global memory; and
Gu (US 20190026225), which teaches a multiple chip multiprocessor cache coherence operation method and a multiple chip multiprocessor. The method includes: receiving a write request for a first data block; finding, in an on-chip directory of the first processor chip, an on-chip directory entry corresponding to the first data block based on an identifier of the first data block, determining, from the found on-chip directory entry, a core identifier of a processor core storing the first data block, sending, to the processor core corresponding to the core identifier, an instruction message for deleting the first data block, skipping sending an inter-chip directory query request for the first data block, and instructing the first processor core to write the to-be-written data into a private cache of the first processor core.
4. CLOSING COMMENTS
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
Prosecution Insights