DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/2/2025 and 9/25/2025 were filed after the mailing date of the application on 6/2/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 15, and 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kumagai (US Patent Pub. # 2025/0126375) in view of Matsuda (US Patent Pub. # 2009/0295968)
As to claim 1, Kumagai (Fig. 2teaches a photoelectric conversion apparatus comprising:
a plurality of substrates including a first substrate (semiconductor substrate 150) and a second substrate (semiconductor substrate 350) (Para 259);
a plurality of pixels (pixel 100) each including a photoelectric conversion element (photoelectric conversion unit 111) configured to generate a charge based on an amount of light received, a floating diffusion (charge holding unit 112) configured to output a signal based on the charge, and a first source-follower circuit (amplification unit 118 and constant current circuit 105) configured to amplify the signal output from the floating diffusion (112), the first source-follower circuit including an amplification transistor (118) and a first transistor (MOS transistor 108) configured to drive the amplification transistor (Para 107, 109, 117, 120 and 122);
a second source-follower circuit (post-stage circuit 120) configured to amplify (second amplification unit 122) a signal output from the first source-follower circuit (118 and 105) (Para 129 and 130); and
a signal processing circuit (control unit 40 and column signal processing unit 30) configured to process a signal output from the second source-follower circuit (120) (Para 105 and 106),
wherein the photoelectric conversion element (100) is disposed on the first substrate (150), and wherein the signal processing circuit (50) is disposed on the second substrate (Para 259).
Kumagai does not teach a first holding circuit electrically connected to a gate electrode of the first transistor. Matsuda teaches a first holding circuit (sample-and-hold type bias section 9) electrically connected to a gate electrode of the first transistor (bias current transistors M41 to M43). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a sample-and-hold type bias section as taught by Matsuda to the photodetection device of Kumagai, to suppress the white transverse stripping (Para 9 and 10 of Matsuda).
As to claim 3, Kumagai teaches wherein each of the plurality of pixels (100) includes a memory circuit (signal level holding circuit 130) configured to hold the signal output (first output node 101) from the first source-follower circuit (118 and 105), and wherein a first capacitive element included in the first holding circuit has a capacitance lower than a capacitance of a third capacitive element included in the memory circuit (the capacitance of the capacitors is a matter of obvious design optimization) (Para 130).
As to claim 4, Matsuda teaches a bias output circuit (current setting input transistor M40) configured to supply a bias voltage (Vbias) to the gate electrode of the first transistor (M41); and a bias control circuit (9) configured to control connection between the gate electrode and the bias output circuit (M40), wherein the bias output circuit (M40) is electrically connected to the first holding circuit (9) via the bias control circuit (control section 12) (Para 45).
As to claim 5, Matsuda teaches wherein the bias control circuit (9) is configured to electrically disconnect the gate electrode from the bias output circuit (M40) at timing when the floating diffusion outputs the signal based on the charge (Para 46).
As to claim 15, Matsuda teaches further comprising a plurality of first holding circuits, wherein each of the plurality of first holding circuits (9) is electrically connected to the gate electrode of the first transistor (M41, M42, M43) included in each of the plurality of pixels (100) (Para 44).
As to claim 20, Kumagai (Fig. 32) teaches further comprising a third substrate (250) on which the first transistor is disposed, wherein the first substrate(150), the third substrate (250), and the second substrate (350) are bonded in this order (Para 272).
As to claim 21, Kumagai (Fig. 32) teaches wherein the signal processing circuit (column signal processing unit 30) includes an analog-to-digital conversion circuit (analog-digital conversion) (Para 105).
As to claim 22, Matsuda teaches wherein the first transistor (M41) and the first holding circuit (9) are both supplied with a reference voltage (VDD) from a common reference voltage line (Vbias) (Para 45).
As to claim 23, Matsuda teaches wherein the first transistor (M41) and the first holding circuit (9) are supplied with a reference voltage (reference current input terminal Iref) from respective different reference voltage lines(Vbias) (Para 45).
Claims 2, 16-19, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kumagai (US Patent Pub. # 2025/0126375) in view of Matsuda (US Patent Pub. # 2009/0295968) and further in view of Totsuka (US Patent Pub. # 2020/0389617).
As to claim 2, note the discussion above in regards to claim 1. Kumagai in view of Matsuda do not specifically teach a second transistor configured to drive the second source-follower circuit; and a second holding circuit electrically connected to a gate electrode of the second transistor, wherein a first capacitive element included in the first holding circuit has a capacitance lower than a capacitance of a second capacitive element included in the second holding circuit. Totsuka teaches a second transistor (N-type load transistor (second transistor) MN5) configured to drive the second source-follower circuit (input transistor MP5); and a second holding circuit (holding capacitor C3) electrically connected to a gate electrode of the second transistor (MN5), wherein a first capacitive element included in the first holding circuit has a capacitance lower than a capacitance of a second capacitive element included in the second holding circuit (the capacitance of the capacitors is a matter of obvious design optimization) (Para 55). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a source ground circuit as taught by Totsuka to the photodetection device of Kumagai in view of Matsuda, to provide a technique for the configuration and arrangement of the analog-to-digital conversion units in an imaging device with stacked structure (Para 4 of Totsuka).
As to claim 16, Totsuka teaches a second transistor (N-type load transistor (second transistor) MN5) configured to drive the second source-follower circuit (input transistor MP5); and a second holding circuit (holding capacitor C3) electrically connected to a gate electrode of the second transistor (MN5) (Para 55), Kumagai (Fig. 26B) teaches wherein the first holding circuit and the second holding circuit are disposed on different substrates (150 and 350) (Para 259).
As to claim 17, Kumagai (Fig. 26B) teaches wherein the first holding circuit is disposed on the first substrate (150), and the second holding circuit is disposed on the second substrate (350) (Para 259).
As to claim 18, Totsuka teaches a second transistor (N-type load transistor (second transistor) MN5) configured to drive the second source-follower circuit (input transistor MP5); and a second holding circuit (holding capacitor C3) electrically connected to a gate electrode of the second transistor (MN5) (Para 55). Kumagai (Fig. 26A) teaches wherein the first holding circuit and the second holding circuit are disposed on a same substrate (150) (Para 258).
As to claim 19, Kumagai (Fig. 26A) teaches wherein the first holding circuit and the second holding circuit are disposed on the second substrate (150) (Para 258).
As to claim 24, note the discussion above in regards to claim 1. Kumagai in view of Masuda do not teach a display apparatus configured to display information acquired by the photoelectric conversion apparatus, a storage apparatus configured to store the information acquired by the photoelectric conversion apparatus, and a mechanical apparatus configured to operate based on the information acquired by the photoelectric conversion apparatus. Totsuka teaches a display apparatus (display) configured to display information acquired by the photoelectric conversion apparatus (Para 105), a storage apparatus (memory unit 1010) configured to store the information acquired by the photoelectric conversion apparatus (Para 101), and a mechanical apparatus (vehicle) configured to operate based on the information acquired by the photoelectric conversion apparatus (Para 104-107).
Claims 6-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kumagai (US Patent Pub. # 2025/0126375) in view of Matsuda (US Patent Pub. # 2009/0295968) and further in view of Hikosaka (US Patent Pub. # 2014/0263966).
As to claim 6, note the discussion above in regards to claim 1 Kumagai in view of Matsuda do not teach wherein the plurality of pixels includes a first pixel and a second pixel, and wherein the first holding circuit is electrically connected to the gate electrode of the first transistor included in the first pixel and the gate electrode of the first transistor included in the second pixel. Hikosaka (Fig. 3) teaches wherein the plurality of pixels includes a first pixel and a second pixel (two-pixels per cell), and wherein the first holding circuit (column constant current source) is electrically connected to the gate electrode of the first transistor included in the first pixel and the gate electrode of the first transistor included in the second pixel (a common voltage holding circuit provided for every two columns). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have provided a column constant current source as taught by Hikosaka to the photodetection device of Kumagai in view of Matsuda, to maintain, at a certain level, a load current to be supplied to the amplifier transistor in the pixel circuit (Para 5 of Hikosaka).
As to claim 7, Kumagai (Fig. 1) teaches wherein the first pixel (100) and the second pixel (100) adjoin each other (Para 103).
As to claim 8, Kumagai teaches wherein in a plan view, the first holding circuit (105) is located between the first pixel (100A) and the second pixel (100B) (Para 210 and 211).
As to claim 9, Kumagai teaches wherein in a plan view, the first holding circuit (105) is located between the photoelectric conversion element (PD) of the first pixel (100A) and the photoelectric conversion element (PD) of the second pixel (100B) (Para 210 and 211).
As to claim 10, Kumagai teaches further comprising a first bonding portion (bonding pad 278) and a second bonding portion configured to bond the first substrate to a substrate different from the first substrate, wherein in a plan view, the first holding circuit is located between the first bonding portion overlapping the first pixel and the second bonding portion overlapping the second pixel (Para 771).
As to claim 11, Kumagai teaches wherein the plurality of pixels includes a third pixel (100B) and a fourth pixel (100D), wherein the first (100A) and second pixels (100C) are disposed in a first row, wherein the third (100B) and fourth pixels (100D) are disposed in a second row, wherein the first (100A) and third pixels (100B) are disposed in a first column, wherein the second (100C) and fourth pixels (100D) are disposed in a second column, and wherein the first holding circuit (105) is electrically connected to the gate electrode of the first transistor included in the third pixel and the gate electrode of the first transistor included in the fourth pixel (Pars 216 and 217).
As to claim 12, Kumagai teaches wherein in a plan view, the first holding circuit (105) is located in a region surrounded by the first pixel (100A), the second pixel (100C), the third pixel (100B), and the fourth pixel (100D) (Para 218).
As to claim 13, Kumagai teaches wherein in a plan view, the first holding circuit(105) is located in a region surrounded by the photoelectric conversion element (PD) of the first pixel (100A), the photoelectric conversion element (PD) of the second pixel (100C), the photoelectric conversion element (PD) of the third pixel (100B), and the photoelectric conversion element (PD) of the fourth pixel (100D) (Para 218).
As to claim 14, Kumagai teaches further comprising a first bonding portion (bonding pad 278), a second bonding portion (278), a third bonding portion (278), and a fourth bonding portion (278) configured to bond the first substrate (150) to a substrate different from the first substrate (150), wherein in a plan view, the first holding circuit (105) is located in a region surrounded by the first bonding portion (278) overlapping the first pixel, the second bonding portion overlapping the second pixel, the third bonding portion overlapping the third pixel, and the fourth bonding portion overlapping the fourth pixel (Para 771).
Conclusion
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/CHRISTOPHER K PETERSON/Primary Examiner, Art Unit 2637 7/24/2026
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