Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/5/26 was considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xi Suping (CN115512635 A, cited by Applicant, machine translation enclosed, hereinafter “Xi”). Regarding claim 1, Xi discloses a display panel, comprising (abstract, Fig. 2, display device with display panel 01 and shift register circuit 100): a substrate (Fig. 2, machine translation page 4, lines 25-30; substrate of display panel 01 where cascaded shift registers 100 are formed on, and with display area AA and non-display area of the display panel 01); and a driving circuit and a first output line located on one side of the substrate, wherein at least part of the first output line extends along a first direction (Figs. 2-3, machine translation page 4, lines 25-32; cascaded shift registers 100 in shift register circuit 10 as a driving circuit; a first output line L1/L2/Out connecting with scan line CL/SL formed in a first “X” cartesian coordinate direction); the driving circuit comprises a plurality of driving units disposed in cascade, the plurality of driving units are arranged along a second direction, and the second direction intersects with the first direction (Fig. 2, machine translation page 4, lines 25-32; cascaded shift registers 100 in shift register circuit 10 as a driving circuit (formed of first output unit 11, second output unit 12, first capacitance C1, and second capacitance C2) with scan lines CL/SL formed in a first “X” direction and shift registers 100 arranged in a second “Y” cartesian coordinate direction that intersects the X direction); at least one driving unit of the plurality of driving units comprises a first output terminal and an output module, the first output line is connected to the first output terminal of the driving unit at a current stage, the output module comprises a first capacitor, and the first capacitor is electrically connected to the first output terminal (Figs. 2-5, machine translation page 4, line 25 to page 5, line 15; the first one of the cascaded shift register circuits 100 be a driving unit that has a first output terminal OUT and an output module formed from transistors T1 or 11, capacitor C1, first capacitor C2 electrically connected to output terminal OUT, and T2 or 12 including lines connecting components to each other and to the OUT terminal); and along a direction perpendicular to a plane of the substrate, the first output line at least partially overlaps with at least one electrode plate of the first capacitor (Fig. 4, machine translation page 5, lines 1-15, the second plate F2 of the first sub-capacitance C01 of the first capacitor C1 and the third plate F3 of the second sub-capacitance C02 of the second capacitor C2 may be provided in the same layer as and is electrically connected to the output terminal OUT of the shift register 100. The second plate F2 and the third plate F3 and at least parts of the second plate F2 and third plate F3 multiplex the output terminal OUT in a direction (Z direction) perpendicular to a direction perpendicular to an XY plane direction of the substrate of the display panel 01, the first output line extending from output terminal OUT overlaps with output line extending from output terminal OUT at ML in Fig. 4).
Regarding claim 2, Xi discloses the display panel according to claim 1, further comprising a pixel circuit, wherein the pixel circuit receives a first control signal (Xi, Figs. 1 and 5-6, machine translation page 5, lines 48-64; OUT signal from shift register 100 is a first control signal); and the at least one driving unit further comprises a first control signal output terminal, and the first control signal output terminal is configured to output the first control signal under the control of the first output terminal (Xi, Figs. 1 and 5-6, machine translation page 5, lines 48-64; OUT signal from shift register 100 is a first control signal that is output from OUT terminal based on Transistors T1 and T2 being ON or OFF in different stages t1-t3).
Regarding claim 5, Xi discloses the display panel according to claim 1, wherein the first output line comprises a first connection portion, along the direction perpendicular to the plane of the substrate, the first connection portion overlaps with the at least one electrode plate of the first capacitor, and the first connection portion is located on one side of the at least one electrode plate of the first capacitor away from the substrate (Xi, Fig. 9, first output line L1 has a first connection portion in a contact hole as a part formed along a direction perpendicular to a plane of the substrate (lowest layer in Fig. 9) which overlaps the electrode plate F2/F3 of the first capacitor C1; the first connection portion is located on one side (upper) of the at least one electrode plate F2/F3 of the first capacitor C1 away from the substrate).
Regarding claim 6, Xi discloses the display panel according to claim 5, wherein a first electrode plate of the first capacitor is electrically connected to the first output terminal, the first connection portion is located on one side of the first electrode plate away from the substrate, and the first connection portion is electrically connected to the first electrode plate through a via hole (Xi, Fig. 9, machine translation page 6, lines 30-48, a first electrode plate F2/F3 of the first capacitor C1 is electrically connected to the first output terminal L1 (wider part), the first connection portion is located on one side (upper) of the first electrode plate F2/F3 away from the substrate (lowest layer), and the first connection portion L1 is electrically connected to the first electrode plate F2/F3 through a via hole (narrow portion of L1 in Fig. 9 is via hole)).
Regarding claim 7, Xi discloses the display panel according to claim 6, but does not explicitly disclose wherein the first connection portion is electrically connected to the first electrode plate through at least two via holes, and two via holes of the at least two via holes are spaced apart from each other (Xi, Figs. 3 and 9, L1 via hole first connection portion for each of C1 capacitors C01 and C02 have separate via holes that are spaced from each other and are connected to the first electrode plate F2/F3).
Regarding claim 8, Xi discloses the display panel according to claim 5, wherein a first electrode plate of the first capacitor is electrically connected to the first output terminal, a second electrode plate of the first capacitor is electrically connected to a second level signal terminal, the first electrode plate is located on one side of the second electrode plate away from the substrate, and at least part of the first electrode plate is reused as the first connection portion (Xi, Figs. 3 and 9, machine translation, page 6, lines 30-59, a first electrode plate F2/F3 of the first capacitor C1 is electrically connected to the first output terminal L1, a second electrode plate F1 of the first capacitor is electrically connected to a second level signal terminal of first control unit 13, the first electrode plate F2/F3 is located on one side (upper) of the second electrode plate F1 away from the substrate (lowest layer in Fig. 9), and at least part of the first electrode plate F2/F3 is reused as the first connection portion when connecting to L1).
Regarding claim 9, Xi discloses the display panel according to claim 5, wherein a width of the first connection portion in the first direction is greater than a line width of at least one other part of the first output line (Xi, Fig. 9, a width of the first connection portion L1 in the first direction at wider upper part is greater than a line width of at least one other part (in the via hole) of the first output line L1).
Regarding claim 20, Xi discloses a display apparatus, comprising a display panel, wherein the display panel comprises (abstract, Fig. 2, display device as display apparatus with display panel 01 and shift register circuit 100): a substrate (Fig. 2, machine translation page 4, lines 25-30; substrate of display panel 01 where cascaded shift registers 100 are formed on, and with display area AA and non-display area of the display panel 01); and a driving circuit and a first output line located on one side of the substrate, wherein at least part of the first output line extends along a first direction (Figs. 2-3, machine translation page 4, lines 25-32; cascaded shift registers 100 in shift register circuit 10 as a driving circuit first a first output line connecting with scan line CL/SL formed in a first “X” cartesian coordinate direction); the driving circuit comprises a plurality of driving units disposed in cascade, the plurality of driving units are arranged along a second direction, and the second direction intersects with the first direction (Fig. 2, machine translation page 4, lines 25-32; cascaded shift registers 100 in shift register circuit 10 as a driving circuit (formed of first output unit 11, second output unit 12, first capacitance C1, and second capacitance C2) with scan lines CL/SL formed in a first “X” direction and shift registers 100 arranged in a second “Y” cartesian coordinate direction that intersects the X direction); at least one driving unit of the plurality of driving units comprises a first output terminal and an output module, the first output line is connected to the first output terminal of the driving unit at a current stage, the output module comprises a first capacitor, and the first capacitor is electrically connected to the first output terminal (Figs. 2-5, machine translation page 4, line 25 to page 5, line 15; the first one of the cascaded shift register circuits 100 be a driving unit that has a first output terminal OUT and an output module formed from transistors T1 or 11, capacitor C1, first capacitor C2 electrically connected to output terminal OUT, and T2 or 12 including lines connecting components to each other and to the OUT terminal); and along a direction perpendicular to a plane of the substrate, the first output line at least partially overlaps with at least one electrode plate of the first capacitor (Fig. 4, machine translation page 5, lines 1-15, the second plate F2 of the first sub-capacitance C01 of the first capacitor C1 and the third plate F3 of the second sub-capacitance C02 of the second capacitor C2 may be provided in the same layer as and is electrically connected to the output terminal OUT of the shift register 100. The second plate F2 and the third plate F3 and at least parts of the second plate F2 and third plate F3 multiplex the output terminal OUT in a direction (Z direction) perpendicular to a direction perpendicular to an XY plane direction of the substrate of the display panel 01, the first output line extending from output terminal OUT overlaps with output line extending from output terminal OUT at ML in Fig. 4).
Allowable Subject Matter
Claims 3-4 and 10-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 3, Xi discloses the display panel according to claim 2, but does not explicitly disclose wherein the output module comprises a first output module and a second output module; the first output module electrically connects the first output terminal and a first level signal terminal in response to a signal of a first node and electrically connects the first output terminal and a second level signal terminal in response to a signal of a second node; and the second output module electrically connects the first control signal output terminal and a first control signal input terminal in response to the signal of the first node, and electrically connects the first control signal output terminal and a second control signal input terminal in response to a signal of the first output terminal.
Claims 4 and 10-19 are objected to based on their dependency from claim 3.
Conclusion
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JOSEPH PATRICK FOX
Examiner
Art Unit 2622
/JOSEPH P FOX/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622