DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 5-7, 9 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5-7, 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xi Suping (CN115512635 A, cited by Applicant, see machine translation, hereinafter “Xi”) in view of Zhu et al. (CN 115831033, hereinafter “Zhu”, machine translation enclosed).
Regarding claim 1, Xi discloses a display panel, comprising (abstract, Fig. 2, display device with display panel 01 and shift register circuit 100): a substrate (Fig. 2, machine translation page 4, lines 25-30; substrate of display panel 01 where cascaded shift registers 100 are formed on, and with display area AA and non-display area of the display panel 01); and a driving circuit and a first output line located on one side of the substrate, wherein at least part of the first output line extends along a first direction (Figs. 2-3, machine translation page 4, lines 25-32; cascaded shift registers 100 in shift register circuit 10 as a driving circuit; a first output line L1/L2/Out connecting with scan line CL/SL formed in a first “X” cartesian coordinate direction); the driving circuit comprises a plurality of driving units disposed in cascade, the plurality of driving units are arranged along a second direction, and the second direction intersects with the first direction (Fig. 2, machine translation page 4, lines 25-32; cascaded shift registers 100 in shift register circuit 10 as a driving circuit (formed of first output unit 11, second output unit 12, first capacitance C1, and second capacitance C2) with scan lines CL/SL formed in a first “X” direction and shift registers 100 arranged in a second “Y” cartesian coordinate direction that intersects the X direction); at least one driving unit of the plurality of driving units comprises a first output terminal and an output module, the first output line is connected to the first output terminal of the driving unit at a current stage, the output module comprises a first capacitor, and the first capacitor is electrically connected to the first output terminal (Figs. 2-5, machine translation page 4, line 25 to page 5, line 15; the first one of the cascaded shift register circuits 100 be a driving unit that has a first output terminal OUT and an output module formed from transistors T1 or 11, capacitor C1, first capacitor C2 electrically connected to output terminal OUT, and T2 or 12 including lines connecting components to each other and to the OUT terminal); and along a direction perpendicular to a plane of the substrate, the first output line at least partially overlaps with at least one electrode plate of the first capacitor (Fig. 4, machine translation page 5, lines 1-15, the second plate F2 of the first sub-capacitance C01 of the first capacitor C1 and the third plate F3 of the second sub-capacitance C02 of the second capacitor C2 may be provided in the same layer as and is electrically connected to the output terminal OUT of the shift register 100. The second plate F2 and the third plate F3 and at least parts of the second plate F2 and third plate F3 multiplex the output terminal OUT in a direction (Z direction) perpendicular to a direction perpendicular to an XY plane direction of the substrate of the display panel 01, the first output line extending from output terminal OUT overlaps with output line extending from output terminal OUT at ML in Fig. 4). Xi does not explicitly disclose the first capacitor comprises a first electrode plate and a second electrode plate; the first output line is located on a side of the first electrode plate away from the substrate and on a side of the second electrode plate away from the substrate, and the first output line is disposed in a different layer from the first electrode plate and the second electrode plate.
Zhu teaches the first capacitor comprises a first electrode plate and a second electrode plate (Fig. 6, machine translation, page 10, third paragraph, first capacitor C1 has a first electrode plate 303 and a second electrode plate 221); the first output line is located on a side of the first electrode plate away from the substrate and on a side of the second electrode plate away from the substrate, and the first output line is disposed in a different layer from the first electrode plate and the second electrode plate (Fig. 6, machine translation, page 10, first to third paragraphs, the first output line 40 is located on an upper side of the first electrode plate 303 away from the substrate 101 and on an upper side of the second electrode plate 221 away from the substrate 101, and the first output line 40 is disposed in a different layer from the first electrode plate 303 and the second electrode plate 221; see also Fig. 7 showing C1 connected to output line OUT). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Xi to have the first capacitor comprises a first electrode plate and a second electrode plate; and the first output line is located on a side of the first electrode plate away from the substrate and on a side of the second electrode plate away from the substrate, and the first output line is disposed in a different layer from the first electrode plate and the second electrode plate, such as taught by Zhu, for the purpose of improving stability of the shift register output end out the output signal (Zhu, machine translation page 9, fifth paragraph). Regarding claim 2, Xi as modified by Zhu discloses the display panel according to claim 1, further comprising a pixel circuit, wherein the pixel circuit receives a first control signal (Xi, Figs. 1 and 5-6, machine translation page 5, lines 48-64; OUT signal from shift register 100 is a first control signal); and the at least one driving unit further comprises a first control signal output terminal, and the first control signal output terminal is configured to output the first control signal under the control of the first output terminal (Xi, Figs. 1 and 5-6, machine translation page 5, lines 48-64; OUT signal from shift register 100 is a first control signal that is output from OUT terminal based on Transistors T1 and T2 being ON or OFF in different stages t1-t3).
Regarding claim 5, Xi as modified by Zhu discloses the display panel according to claim 1, wherein the first output line comprises a first connection portion, along the direction perpendicular to the plane of the substrate, the first connection portion overlaps with the at least one electrode plate of the first capacitor, and the first connection portion is located on one side of the at least one electrode plate of the first capacitor away from the substrate (Zhu, Fig. 6, machine translation, page 6, first three paragraphs, first output line 40 has a first connection portion in a contact hole at bottom part of 40 as a part formed along a direction perpendicular to a plane of the substrate 101 which overlaps the second electrode plate 221 of the first capacitor C1; the first connection portion is located on one side (upper) of the second electrode plate 221 of the first capacitor C1 away from the substrate 101). The motivation is the same as in claim 1.
Regarding claim 6, Xi as modified by Zhu discloses the display panel according to claim 5, wherein the first electrode plate of the first capacitor is electrically connected to the first output terminal, the first connection portion is located on one side of the first electrode plate away from the substrate, and the first connection portion is electrically connected to the first electrode plate through a via hole (Zhu, Fig. 6, machine translation page 6, first three paragraphs, a first electrode plate 303 of the first capacitor C1 is electrically connected to the first output terminal at lower part of 40, the first connection portion is located on one side (upper) of the first electrode plate 303 away from the substrate 101, and the first connection portion is electrically connected to the first electrode plate 303 through a via hole at 40).
The motivation is the same as in claim 1.
Regarding claim 7, Xi as modified by Zhu discloses the display panel according to claim 6, wherein the first connection portion is electrically connected to the first electrode plate through at least two via holes, and two via holes of the at least two via holes are spaced apart from each other (Zhu, Fig. 5, machine translation page 9 last paragraph, via holes for first connection portion for each of C1 capacitors have separate via holes that are spaced from each other and are connected to the first electrode plate 303).
The motivation is the same as in claim 1.
Regarding claim 9, Xi as modified by Zhu discloses the display panel according to claim 5, wherein a width of the first connection portion in the first direction is greater than a line width of at least one other part of the first output line (Zhu, Fig. 6, a width of the first connection portion 40 in the first direction at wider upper part of 40 is greater than a line width of at least one other part (in the via hole) of the first output line 40). The motivation is the same as in claim 1.
Regarding claim 20, Xi discloses a display apparatus, comprising a display panel, wherein the display panel comprises (abstract, Fig. 2, display device as display apparatus with display panel 01 and shift register circuit 100): a substrate (Fig. 2, machine translation page 4, lines 25-30; substrate of display panel 01 where cascaded shift registers 100 are formed on, and with display area AA and non-display area of the display panel 01); and a driving circuit and a first output line located on one side of the substrate, wherein at least part of the first output line extends along a first direction (Figs. 2-3, machine translation page 4, lines 25-32; cascaded shift registers 100 in shift register circuit 10 as a driving circuit first a first output line connecting with scan line CL/SL formed in a first “X” cartesian coordinate direction); the driving circuit comprises a plurality of driving units disposed in cascade, the plurality of driving units are arranged along a second direction, and the second direction intersects with the first direction (Fig. 2, machine translation page 4, lines 25-32; cascaded shift registers 100 in shift register circuit 10 as a driving circuit (formed of first output unit 11, second output unit 12, first capacitance C1, and second capacitance C2) with scan lines CL/SL formed in a first “X” direction and shift registers 100 arranged in a second “Y” cartesian coordinate direction that intersects the X direction); at least one driving unit of the plurality of driving units comprises a first output terminal and an output module, the first output line is connected to the first output terminal of the driving unit at a current stage, the output module comprises a first capacitor, and the first capacitor is electrically connected to the first output terminal (Figs. 2-5, machine translation page 4, line 25 to page 5, line 15; the first one of the cascaded shift register circuits 100 be a driving unit that has a first output terminal OUT and an output module formed from transistors T1 or 11, capacitor C1, first capacitor C2 electrically connected to output terminal OUT, and T2 or 12 including lines connecting components to each other and to the OUT terminal); and along a direction perpendicular to a plane of the substrate, the first output line at least partially overlaps with at least one electrode plate of the first capacitor (Fig. 4, machine translation page 5, lines 1-15, the second plate F2 of the first sub-capacitance C01 of the first capacitor C1 and the third plate F3 of the second sub-capacitance C02 of the second capacitor C2 may be provided in the same layer as and is electrically connected to the output terminal OUT of the shift register 100. The second plate F2 and the third plate F3 and at least parts of the second plate F2 and third plate F3 multiplex the output terminal OUT in a direction (Z direction) perpendicular to a direction perpendicular to an XY plane direction of the substrate of the display panel 01, the first output line extending from output terminal OUT overlaps with output line extending from output terminal OUT at ML in Fig. 4). Xi does not explicitly disclose the first capacitor comprises a first electrode plate and a second electrode plate; the first output line is located on a side of the first electrode plate away from the substrate and on a side of the second electrode plate away from the substrate, and the first output line is disposed in a different layer from the first electrode plate and the second electrode plate.
Zhu teaches the first capacitor comprises a first electrode plate and a second electrode plate (Fig. 6, machine translation, page 10, third paragraph, first capacitor C1 has a first electrode plate 303 and a second electrode plate 221); the first output line is located on a side of the first electrode plate away from the substrate and on a side of the second electrode plate away from the substrate, and the first output line is disposed in a different layer from the first electrode plate and the second electrode plate (Fig. 6, machine translation, page 10, first to third paragraphs, the first output line 40 is located on an upper side of the first electrode plate 303 away from the substrate 101 and on an upper side of the second electrode plate 221 away from the substrate 101, and the first output line 40 is disposed in a different layer from the first electrode plate 303 and the second electrode plate 221; see also Fig. 7 showing C1 connected to output line OUT). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Xi to have the first capacitor comprises a first electrode plate and a second electrode plate; and the first output line is located on a side of the first electrode plate away from the substrate and on a side of the second electrode plate away from the substrate, and the first output line is disposed in a different layer from the first electrode plate and the second electrode plate, such as taught by Zhu, for the purpose of improving stability of the shift register output end out the output signal (Zhu, machine translation page 9, fifth paragraph).
Allowable Subject Matter
Claim 21 is allowed.
Claims 3-4 and 10-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 3, Xi discloses the display panel according to claim 2, but does not explicitly disclose wherein the output module comprises a first output module and a second output module; the first output module electrically connects the first output terminal and a first level signal terminal in response to a signal of a first node and electrically connects the first output terminal and a second level signal terminal in response to a signal of a second node; and the second output module electrically connects the first control signal output terminal and a first control signal input terminal in response to the signal of the first node, and electrically connects the first control signal output terminal and a second control signal input terminal in response to a signal of the first output terminal.
Claims 4 and 10-19 are objected to based on their dependency from claim 3.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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JOSEPH PATRICK FOX
Examiner
Art Unit 2622
/JOSEPH P FOX/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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