Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “an upper controller” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 19/225,780 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the examined application claim is anticipated by the reference claims.
Claim mapping: the examined application claim is compared by the reference claim in parenthesis. The differences are underlined.
An inverter driving apparatus configured to drive an inverter including a plurality of power modules connected in parallel, the apparatus comprising: (An apparatus for driving an inverter comprising a plurality of power modules connected in parallel, the apparatus comprising:)
a gate driver configured to output a control signal to the plurality of power modules and monitor a threshold voltage of each of the plurality of power modules; and (a gate driver configured to output a gate voltage to the plurality of power modules and to monitor a threshold voltage of each of the plurality of power modules; and)
a controller configured to control the gate driver in response to an instruction input from an upper controller (a controller configured to output a Pulse Width Modulation (PWM) signal to the gate driver in response to a command input from an upper controller);
wherein the controller is configured to change a first Pulse Width Modulation (PWM) signal generated based on the instruction (output a Pulse Width Modulation (PWM) signal to the gate driver in response to a command) and based on the threshold voltage for each of the plurality of power modules provided by the gate driver to generate a second PWM signal (and to output a voltage control signal), and to output the second PWM signal to the gate driver (and to output a voltage control signal to the gate driver based on the threshold voltage of each of the plurality of power modules; wherein the gate driver is configured to output the gate voltage, based on a feedback gate voltage that includes feedback regarding the gate voltage, the PWM signal, and the voltage control signal).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 and 10-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zarabadi (US 2024/0106369).
Regarding claims 1, 13 and 19, Zarabadi discloses an inverter driving apparatus, a method and a vehicle (FIG 1-12)(¶[0043]) configured to drive an inverter including a plurality of power modules (140, 145, specifically 144 and 146 phase switches or power device switches) connected in parallel (¶[0103]), the apparatus comprising: a gate driver (142, 146 gate driver, ¶[0052]) configured to output a control signal to the plurality of power modules and monitor (¶[0052]) a threshold voltage (¶[0052]) of each of the plurality of power modules; and a controller (130, 135, PWM controller, ¶[0043]) configured to control the gate driver (142, 146) in response to an instruction input from an upper controller (300 ¶[0057]-[0071] via 120 and 125 ¶[0055]); wherein the controller (130, 135) is configured to change a first Pulse Width Modulation (PWM) signal (PWM is updated based on the communication between the controllers and the gate drivers ¶[0043]-[0045]) and generated based on the instruction (¶[0043]-[0045], and based on the threshold voltage for each of the plurality of power modules provided by the gate driver to generate a second PWM signal (updated PWM signal based on the continuous measurement ¶[0052]), and to output the second PWM signal to the gate driver (142, 148 ¶[0052]).
Regarding claims 2|1, 14|13 and 20|19 Zarabadi discloses the apparatus wherein the controller is configured to change a generation point of the first PWM signal or change a duty of the first PWM signal based on a first delay determined based on the threshold voltage (¶[0103]-[0105]) of each of the plurality of power modules to generate the second PWM signal (¶[0052]).
Regarding claims 3|2|1 and 15|14|13, Zarabadi discloses the apparatus wherein: the controller is configured to apply the first delay to a count serving as a reference for the generation point of the first PWM signal to generate the second PWM signal; and the second PWM signal is generated with a second delay equal to the first delay, relative to the first PWM signal (¶[0052] “computation of the optimum gate-drive turn-on and tun-off voltage profiles ...” ¶[0103]-[0105]).
Regarding claims 4|2|1 and 16|14|13, Zarabadi discloses the apparatus wherein the controller is configured to apply the first delay to at least one of a turn-on point and a turn-off point of the first PWM signal to generate the second PWM signal having a longer duty than the first PWM signal (¶[0052] “optimum” includes a longer duty as well as shorter duty ¶[0103]-[0105]).
Regarding claims 5|4|2|1 and 17|16|14|13, Zarabadi discloses the apparatus wherein: the controller is configured to apply the first delay to the turn-on point and turn-off point of the first PWM signal; and the turn-on point of the second PWM signal is delayed relative to the turn-on point of the first PWM signal by the first delay, and the turn-off point of the second PWM signal is delayed relative to the turn-off point of the first PWM signal by the first delay (¶[0043],[0048],[0103],[0104],[0106]).
Regarding claims 6|4|2|1 and 18|16|14|13, Zarabadi discloses the apparatus wherein: the controller is configured to apply the first delay to the turn-on point of the first PWM signal; and the turn-on point of the second PWM signal is delayed relative to the turn-on point of the first PWM signal by the first delay (¶[0043],[0048],[0103],[0104],[0106]).
Regarding claim 7|1, Zarabadi discloses the apparatus wherein the controller is configured to determine the first delay based on slope characteristics of a gate-source voltage of the plurality of power modules (¶[0094]-[0097]).
Regarding claim 8|7|1, Zarabadi implies the apparatus wherein the controller is configured to determine the first delay based on: delay =(Vth1-Vth2)/dVgs/dt (Vth1>Vth2), where Vth1 is a threshold voltage of a first power module, Vth2 is a threshold voltage of a second power module, and dVgs/dt is current flowing through a gate resistor Rg (¶[0103]-[0104]).
Regarding claim 10|1, Zarabadi discloses the apparatus wherein the gate driver includes a threshold voltage monitoring circuit configured to monitor the threshold voltages of the plurality of power modules, to convert the monitored threshold voltages into digital signals, and to provide the digital signals to the controller (¶[0089]-[0098]).
Regarding claim 11|1, Zarabadi discloses the apparatus wherein: the inverter includes a plurality of module groups including a plurality of power modules connected in parallel; the gate driver is connected to each of the plurality of module groups; and the gate driver is configured to monitor the threshold voltages for the plurality of power modules within the plurality of module groups (¶[0089]-[0098]).
Regarding claim 12, Zarabadi discloses the apparatus wherein the gate driver is configured to monitor the voltage of a gate resistor connected between the gate driver and a gate terminal of the power module in a state where a switch element connected between the gate terminal and a drain terminal of the power module is short-circuited (¶[0089]-[0098]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zarabadi.
Regarding claim 9|1, Zarabadi discloses the apparatus wherein the controller is configured to determine the first delay corresponding to a threshold voltage based on
Zarabadi does not disclose a table including delays for each threshold voltage of each of the plurality of power modules. As know in the art, use of a table is a routine practice of determination scheme and therefore, it would have been obvious to one of ordinary skill in the art to use a table because such a modification would have been a mere substitution of art recognized equivalent determination scheme.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KR20140013277 discloses an inverter for driving a motor for converting DC form a high voltage battery to drive a motor showing a gate driver circuit, a controller, and power switches using PWM signals having a adjusted delay time.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph Chang whose telephone number is (571)272-1759. The examiner can normally be reached M-F 7:00- 17:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah M Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH CHANG/Primary Examiner, Art Unit 2836
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