Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 20, claim limitations “means for obtaining, means for allowing, means for enforcing, means for executing” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. It’s not clear from the specification which corresponding structure the means for obtaining, allowing, enforcing and executing is. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 15-18 and 20 are rejected under 35 U.S.C. 102a as being anticipated by Gogte et al. US PG-Pub 2020/0285479 (hereinafter Gogte).
As per claim 1, Gogte teaches a method, comprising:
obtaining a sequence of instructions (see abstract, stream of instructions);
allowing re-ordering of a subset of first instructions in the one sequence subject to at least one constraint (paragraph [0003]-[0005] and [0064] teaches ordering instructions based on dependencies, where the order of execution depends on dependencies between instruction. It further teaches that barrier inhabitation relaxes dependencies so that instructions after the inhabitation instruction can be executed before, after, or in parallel with other instructions, thereby increasing flexibility in scheduling and reordering [0028]. The “at least one constraint” is met by the dependency/barrier rules that determine whether an instruction can be issued/executed);
enforcing program order for at least one instruction in the one sequence (Fig. 4A-C and paragraph [0048]-[0052] teaches a barrier creation instruction that creates barrier dependencies requiring pre-barrier instructions to be sent or executed before post-barrier instructions. It expressly states that instructions prior to the barrier must be sent or executed before instructions after the barrier, thereby enforcing a particular order. In the ABCD example, a barrier between A and B requires B to wait until A has issued/executed; another barrier requires D to wait until C, showing enforcement of program order for selected instructions while not unnecessarily extending that ordering to all later instructions); and
executing the at least one sequence of instructions in accordance with the re-ordering and the enforcement (Fig. 4A-C and paragraph [0048]-[0052], see also abstract and claim 9, which teaches sending instructions to processing circuitry based on dependencies permitting some instructions to execute out of order while enforcing barrier-created ordering for others. It specifically states that instructions can be executed in order such as ABCD and that execution order depends on dependencies).
As per claim 2, Gogte teaches wherein the at least one instruction occurs before or after the subset of first instructions (Fig. 4A-C and paragraph [0048]-[0052] teaches a barrier creation instruction that creates barrier dependencies requiring pre-barrier instructions to be sent or executed before post-barrier instructions. It expressly states that instructions prior to the barrier must be sent or executed before instructions after the barrier, thereby enforcing a particular order. In the ABCD example, a barrier between A and B requires B to wait until A has issued/executed; another barrier requires D to wait until C, showing enforcement of program order for selected instructions while not unnecessarily extending that ordering to all later instructions).
As per claim 3, Gogte teaches the method of claim 1, wherein enforcing program order for the at least one instruction comprises preventing bypassing of the at least one instruction (Fig. 4A-C and paragraph [0048]-[0052]).
As per claim 4, Gogte teaches the method of claim 1, further comprising re-ordering the subset of first instructions based on the at least one constraint being satisfied (Fig. 3a-3b and paragraph [0045]-[0046] and [0064]).
As per claim 5, Gogte teaches the method of claim 1, wherein the at least one constraint is that the subset of first instructions correspond to commutative operations (Fig. 3a-3b and paragraph [0045]-[0046], ADD and MUL operations).
As per claim 6, Gogte teaches the method of claim 5, wherein the subset of first instructions produces results in a matrix register (Fig 3b and paragraph [0046]).
As per claims 15-18, they’re rejected for the same reasons set forth above in claims 1-. The processors and memory are taught by Gogte (see abstract and Fig. 1).
As per claim 20, it’s rejected for the same reasons set forth above in claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gogte in view of Sazegari et al. US PG-Pub 2018/0074824 (hereinafter Sazegari).
As per claim 7, Gogte did not specifically show the feature of claim 7. However, Sazegari teaches wherein the subset of first instructions perform matrix outer product operations and accumulate results in the matrix register. Sazegari teaches that an outer-product engine performs numerous multiplication operations in parallel on input vectors to generate a resulting outer-product matrix. Sazegari further teaches that the engine performs FMA operations to produce outer-product elements and accumulate those elements with previous element from the result matrix memory (see abstract and paragraph [0023]).
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention to apply Gogte dependency-based reordering and ordering enforcement to Sazegari’s outer-product/FMA matrix instructions because matrix-accumulation instructions benefit from flexible scheduling where operations are independent or commutative, while consumer clear/zero instruction require enforced order to preserve correctness.
As per claim 8, Gogte teaches enforcing program order for instructions that must wait on earlier instruction through dependency/barrier tracking. It discloses that barrier dependencies cause pre-barrier instructions to be set before post-barrier instructions that that this enforces a particular order. However, Gogte wasn’t specific on the results in the matrix register produced by the subset of first instructions.
However, Sazegari teaches that the outer-product result matrix is stored in output/Z memory and that instructions may include memory instructions to read and write data from the vector memories and output memory. Sazegari also teaches that the Z memory is configured to store at least one outer-product result matrix (paragraph [0022]-[0025] and [0038]-[0039]). Thus, a later instruction that reads/uses the accumulated result matrix reads on the claimed “second instruction consumes the results in the matrix register.”
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to combine Sazegari’s outer-product/FMA matrix instructions into Gogte dependency-based reordering and ordering enforcement to because matrix-accumulation instructions benefit from flexible scheduling where operations are independent or commutative, while consumer clear/zero instruction require enforced order to preserve correctness.
As per claim 9, Gogte did not specifically teach wherein the second instruction zeroes the matrix register. However, Sazegari teaches clear instruction to clear/zero the Z memory, and that Z memory stores the outer-product result matrix (paragraph [0049]).
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to integrate Sazegari teaching of clearing/zero instruction into Gogte ordering enforcement to prevent instructions from incorrectly passing matrix-producing instructions whose accumulated results must be preserved or consumed.
As per claim 10, Gogte did not specifically teach wherein the at least one instruction moves data to or from the matrix register. However, Sazegari teaches moving data to or from the matrix register (see paragraphs [0022]-[0024] and [0049]).
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to integrate Sazegari teaching of moving data to and from the matrix register into Gogte ordering enforcement to prevent instructions from incorrectly passing matrix-producing instructions whose accumulated results must be preserved or consumed.
As per claim 19, it’s rejected for the same reasons set forth above in claims 8-10.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Gogte in view of Coon et al. US Patent No. 8,225,076 (hereinafter Coon).
As per claim 11, Gogte teaches maintaining dependency information between instructions using track circuitry and storage circuitry. However, it did not specifically teach counters.
However, Coon teaches a scoreboard structure which is equivalent to a counter for tracking instruction dependencies. In particular Coon teaches storing dependency information in scoreboard memory, issuing an instruction only when the dependency mask indicates no dependency, and updating the scoreboard when instructions issue and complete (col. 3, lines 49-60 and col. 6, lines 3-29).
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to implement Gogte dependency tracking using scoreboard counter as taught by Coon. Gogte already requires tracking dependencies to determine whether instructions may be sent out of order or must remain ordered, and Coon teaches a known hardware structures for tracking such dependencies and controlling instruction issue. The combination merely substitutes a known dependency-tracking implementation for Gogte dependency tracking.
As per claim 12, Gogte teaches the underlying need to distinguish between instructions that may be bypassed/reordered and instructions that may not be bypassed due to barrier dependencies. It discloses that barrier creation causes post-barrier instructions to depend on pre-barrier instructions, while barrier inhibition relaxes those dependencies and permits post-inhibition instructions to be sent before pre-barrier instructions.
Coon teaches maintaining scoreboard/dependency state and updating that state as instructions issue and complete. Coon further teaches that an instruction may issue only when its dependency mask is zero and that scoreboard memory is updated when the instruction issues and again when execution completes.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention to implement Gogte barrier/dependency tracking using counters that track-in-flight instructions, non-bypassable instructions, and issued instructions, because such counters are a predictable hardware implementation for determining whether a later instruction may bypass an earlier instruction while maintaining correct dependency/order enforcement.
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art on record failed teach maintaining a per-instruction counter for each instruction, wherein the per- instruction counter for a given instruction is set to a value based on a sum of current values of the second and third counters when that instruction is dispatched, together with the combination of elements recited in the claims depending therefrom.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PG-Pub 2006/0212682 teaches processing utilizing novel architectural ordering scheme.
US Patent No. 5,872,948 teaches processor for out-of-order execution of instructions based upon an instruction parameter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDRISS N ALROBAYE whose telephone number is (571)270-1023. The examiner can normally be reached Mon-Fri, 8am-4:30pm.
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/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181
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