DETAILED ACTION
This action is in response to the preliminary amendment filed on 6/2/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-4 are rejected on the ground of non-statutory double patenting as being unpatentable over Claims 1-4 of U.S. Patent No. 12348129. Although the claims at issue are not identical, they are not patentably distinct from each other because: Claim 1 of the instant application states: power supply circuit, comprising: a power factor correction (PFC) circuit, for performing a power factor correction according to a first voltage to generate an intermediate voltage; a first storage capacitor, having a first end and a second end, wherein the second end is connected to an output end of the PFC circuit, and the first storage capacitor is used to store a first electrical energy related to the intermediate voltage; a boost conversion circuit, connected to the PFC circuit and used to generate an output voltage according to the intermediate voltage, wherein the boost conversion circuit comprising: a first post-stage diode; a first post-stage inductor, having a first end connected to the first end of the first storage capacitor and a second end connected to a second end of the first post-stage diode; a first post-stage transistor, having a first terminal connected to the second end of the first post-stage diode and the second end of the first post-stage inductor and a first switch, connected between the first end of the first storage capacitor and a ground end, and a second storage capacitor, having a first end connected to an first end of the first post-stage diode, and a second end connected to a second terminal of the first post-stage transistor, wherein the second storage capacitor is used to store a second electrical energy related to the output voltage, and the potential at the second end of the second storage capacitor is equivalent to the output voltage, wherein, the capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor, and the first electrical energy is completely or partially transferred as the second electrical energy. Claims 1 and 2 of US Patent 12348129 states: a power supply circuit, comprising: a power factor correction (PFC) circuit, for performing a power factor correction according to a first voltage to generate an intermediate voltage; a first storage capacitor having a second end connected to a ground end, wherein the first storage capacitor is directly or indirectly connected to the PFC circuit and used to store a first electrical energy, the first electrical energy being related to the intermediate voltage; a boost conversion circuit, connected to the PFC circuit and used to generate an output voltage according to the intermediate voltage, wherein the boost conversion circuit comprising: a first post-stage inductor having a first end connected to a first end of the first storage capacitor; a first post-stage diode having a first end selectively connected to a second end of the first post-stage inductor and having a second end connected to an output end of the PFC circuit; and a first post-stage transistor having a first end connected to the first post-stage inductor and connected to the first end of the first post-stage diode, and a second storage capacitor having a first end connected to the second end of the first post-stage diode, wherein a potential at the first end is equivalent to the output voltage, and the second storage capacitor is used to store a second electrical energy, the second electrical energy being related to the output voltage, wherein, the capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor, and the first electrical energy is completely or partially transferred as the second electrical energy, wherein the boost conversion circuit further comprising: a first switch, connected between the output end of the PFC circuit and the first end of the first storage capacitor, wherein, the first switch is used to suppress an inrush current generated by the PFC circuit. Claim 2 of the instant application states: wherein the boost conversion circuit further comprising: a first resistor, connected to the first switch in parallel. Claim 3 of US Patent 12348129 states: wherein the boost conversion circuit further comprising: a first resistor, connected to the first switch in parallel, wherein, the first storage capacitor is connected to the PFC circuit through first resistor. Claim 3 of the instant application states: wherein the PFC circuit comprising: a first front-stage diode, having a second end directly or indirectly connected to the first storage capacitor; a first front-stage transistor, having a terminal connected to a first end of the first front-stage diode; and a first front-stage inductor, connected between the first end of the first front-stage diode and an input end of the PFC circuit. Claim 4 of US Patent 12348129 states: the PFC circuit comprising: a first front-stage diode having a second end directly or indirectly connected to the first storage capacitor; a first front-stage transistor having a first end connected to a first end of the first front-stage diode; and a first front-stage inductor connected between the first end of the first front-stage diode and an input end of the PFC circuit. Claim 4 of the instant application states: a power supply circuit, comprising: a power factor correction (PFC) circuit, for performing a power factor correction according to a first voltage to generate an intermediate voltage, and the PFC circuit comprising: a first front-stage diode; a first front-stage transistor, having a terminal connected to an first end of the first front-stage diode; and a first front-stage inductor, connected between the first end of the first front-stage diode and an input end of the PFC circuit, a first storage capacitor, directly or indirectly connected to a second end of the first front-stage diode of the PFC circuit, and used to store a first electrical energy related to the intermediate voltage; a boost conversion circuit, connected to the PFC circuit and used to generate an output voltage according to the intermediate voltage, wherein the boost conversion circuit comprising: a first post-stage inductor, connected to the first storage capacitor; a first post-stage diode, connected to the first post-stage inductor; and a first post-stage transistor, connected to the first post-stage inductor and connected to the first post-stage diode, and a second storage capacitor, connected to the first post-stage diode and used to store a second electrical energy is related to the output voltage, wherein, the capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor, and the first electrical energy is completely or partially transferred as the second electrical energy. Claims 1 and 4 of US Patent 12348129 states: a power supply circuit, comprising: a power factor correction (PFC) circuit, for performing a power factor correction according to a first voltage to generate an intermediate voltage; a first storage capacitor having a second end connected to a ground end, wherein the first storage capacitor is directly or indirectly connected to the PFC circuit and used to store a first electrical energy, the first electrical energy being related to the intermediate voltage; a boost conversion circuit, connected to the PFC circuit and used to generate an output voltage according to the intermediate voltage, wherein the boost conversion circuit comprising: a first post-stage inductor having a first end connected to a first end of the first storage capacitor; a first post-stage diode having a first end selectively connected to a second end of the first post-stage inductor and having a second end connected to an output end of the PFC circuit; and a first post-stage transistor having a first end connected to the first post-stage inductor and connected to the first end of the first post-stage diode, and a second storage capacitor having a first end connected to the second end of the first post-stage diode, wherein a potential at the first end is equivalent to the output voltage, and the second storage capacitor is used to store a second electrical energy, the second electrical energy being related to the output voltage, wherein, the capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor, and the first electrical energy is completely or partially transferred as the second electrical energy, the PFC circuit comprising: a first front-stage diode having a second end directly or indirectly connected to the first storage capacitor; a first front-stage transistor having a first end connected to a first end of the first front-stage diode; and a first front-stage inductor connected between the first end of the first front-stage diode and an input end of the PFC circuit.
Conclusion
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/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
