DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-22 are present for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/07/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
RE claim 1, the limitation of that, “CMOS device” in line 8 is vague and rendering claim 1 indefinite. What is “CMOS” standing for? “CMOS” is not clearly defined in the claim 1. Correction is required.
RE claim 1, the limitation of that, “CMOS device” in line 11 is vague and rendering claim 1 indefinite. What is “CMOS” standing for? “CMOS” is not clearly defined in the claim 1. Correction is required.
Claims 2-10 are depending on claim 1 and therefore are rejected on the same basis as claim 1.
RE claim 11, the limitation of that, “CMOS device” in line 6 is vague and rendering claim 11 indefinite. What is “CMOS” standing for? “CMOS” is not clearly defined in the claim 11. Correction is required.
RE claim 11, the limitation of that, “CMOS device” in line 11 is vague and rendering claim 11 indefinite. What is “CMOS” standing for? “CMOS” is not clearly defined in the claim 11. Correction is required.
RE claim 11, the limitation of that, “CMOS device” in line 13 is vague and rendering claim 11 indefinite. What is “CMOS” standing for? “CMOS” is not clearly defined in the claim 11. Correction is required.
Claims 12-18 are depending on claim 11 and therefore are rejected on the same basis as claim 11.
RE claim 19, the limitation of that, “CMOS device” in line 4 is vague and rendering claim 19 indefinite. What is “CMOS” standing for? “CMOS” is not clearly defined in the claim 19. Correction is required.
RE claim 19, the limitation of that, “CMOS device” in line 6 is vague and rendering claim 19 indefinite. What is “CMOS” standing for? “CMOS” is not clearly defined in the claim 19. Correction is required.
Claims 20-22 are depending on claim 19 and therefore are rejected on the same basis as claim 19.
Allowable Subject Matter
Claims 1-10 are allowable over the prior art of record because none of the prior art of record teaches or fairly suggests the limitation of that, a stationary cascode section configured to receive the low-level signals and high-level signals from the data switch section, the stationary cascode section comprising a high voltage CMOS device configured to generate a cascode pass through current, in the environment of claim 1. The closest prior art of record is Chiou et al (USPN 5,386,328). Chiou et al (USPN 5,386,328) disclose that a write driver to operate inductive heads for magnetic recording. The inductive recording head is coupled between first and second outputs of a first write driver block. The first and second outputs of the first write driver block are coupled to first and second inputs of a second write driver block, respectively. First and second current sources are coupled to third and fourth inputs of the second write driver block, respectively. A first switching block is coupled to the first current source and to the third input of the second write driver block. A second switching block is coupled to the second current source and to the fourth input of the second write driver block. A first input signal is provided toa first input of the first write driver block and to the first switching block. A second input signal is provided to a second input of the first write driver block and to the second switching block. The second output of the first write driver block, the inductive recording head and the first input of the second write driver block form a first current path when the first input signal is greater than the second input signal. Conversely, the first output of the first write driver block, the inductive recording head and the second input of the second write driver block form a second current path when the second input signal is greater. The first and second input signals may be CMOS or differential ECL signals.
Claims 11-18 are allowable over the prior art of record because none of the prior art of record teaches or fairly suggests the limitation of that, a write driver coupled to the low-level driver and to the high-level driver and configured to generate a write current, the write driver comprising a high voltage CMOS device, in the environment of claim 11. The closest prior art of record is Chiou et al (USPN 5,386,328). Chiou et al (USPN 5,386,328) disclose that a write driver to operate inductive heads for magnetic recording. The inductive recording head is coupled between first and second outputs of a first write driver block. The first and second outputs of the first write driver block are coupled to first and second inputs of a second write driver block, respectively. First and second current sources are coupled to third and fourth inputs of the second write driver block, respectively. A first switching block is coupled to the first current source and to the third input of the second write driver block. A second switching block is coupled to the second current source and to the fourth input of the second write driver block. A first input signal is provided toa first input of the first write driver block and to the first switching block. A second input signal is provided to a second input of the first write driver block and to the second switching block. The second output of the first write driver block, the inductive recording head and the first input of the second write driver block form a first current path when the first input signal is greater than the second input signal. Conversely, the first output of the first write driver block, the inductive recording head and the second input of the second write driver block form a second current path when the second input signal is greater. The first and second input signals may be CMOS or differential ECL signals.
Claims 19-22 are allowable over the prior art of record because none of the prior art of record teaches or fairly suggests the limitation of that, receiving, by a stationary cascode section comprising a high voltage CMOS device, the low-level signal and the high-level signal, and generating, by the stationary cascode section, a cascode pass through current, in the environment of claim 19. The closest prior art of record is Chiou et al (USPN 5,386,328). Chiou et al (USPN 5,386,328) disclose that a write driver to operate inductive heads for magnetic recording. The inductive recording head is coupled between first and second outputs of a first write driver block. The first and second outputs of the first write driver block are coupled to first and second inputs of a second write driver block, respectively. First and second current sources are coupled to third and fourth inputs of the second write driver block, respectively. A first switching block is coupled to the first current source and to the third input of the second write driver block. A second switching block is coupled to the second current source and to the fourth input of the second write driver block. A first input signal is provided toa first input of the first write driver block and to the first switching block. A second input signal is provided to a second input of the first write driver block and to the second switching block. The second output of the first write driver block, the inductive recording head and the first input of the second write driver block form a first current path when the first input signal is greater than the second input signal. Conversely, the first output of the first write driver block, the inductive recording head and the second input of the second write driver block form a second current path when the second input signal is greater. The first and second input signals may be CMOS or differential ECL signals.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Contreras et al (US 2008/0112085)
Kuehlwein et al (US 2006/0171054)
Contreras et al (USPN 9,275,656)
Poss et al (US 2023/0197108)
Contreras et al (USPN 9,153,248)
Any inquiry concerning this communication from the examiner should be directed to FRED TZENG whose telephone number is 571-272-7565. The examiner can normally be reached on weekdays from 2:0 pm to 10:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached on 571-272-0666. The fax phone numbers for the organization where this application or proceeding is assigned are 571-273-8300 for regular communications and 571-273-7565 for After Final communications.
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/FRED TZENG/ Primary Examiner, Art Unit 2625
FFT
February 01, 2026