DETAILED ACTION
Claims 1-20 are pending.
Priority: May 13, 2022(Continuation of US Patent No.11,989,126)
Assignee: Micron
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim(s) 1, 2, 5, 8, 9, 12, 15, 16, 19 are objected to because of the following informalities:
Inconsistent verb forms in claims 1, 8, and 15.
The claims should be conformed as follows:
Claim 1: following “the processing device to,” use “determine,” “store,” “associate,” and “send.”
Claim 8: as a method claim, use parallel gerunds—“determining,” “storing,” “associating,” and “sending.”
Claim 15: following “cause the processing device to,” use “determine,” “store,” “associate,” and “send.”
Incorrect expansion of CXL in claims 5, 12, and 19
Claims 5, 12, and 19 use “computer express link (CXL).” The accepted name, and the terminology used elsewhere in the application, is “Compute Express Link (CXL).” The inconsistent expansion should be corrected by objection. The acronym itself makes the intended technology reasonably apparent, so the defect ordinarily would not justify a substantive indefiniteness rejection.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-17 of U.S. Patent No. 11,989,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the corresponding ‘126 claims either fall wholly within the broader scope of the instant claims or render the remaining differences obvious, as shown below.
Likewise, claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-20 of U.S. Patent No. 12,332,786. Although the claims at issue are not identical, they are not patentably distinct from each other because the corresponding ‘786 claims either fall wholly within the broader scope of the instant claims or render the remaining differences obvious, as shown below.
19/226,962(Instant)
1. A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to: determining a state of a cache line stored on the memory device; responsive to determining that the cache line is in a modified state, store the cache line in an active log memory buffer associated with the memory device; and associating, with the active log memory buffer, a flag indicating that the active log memory buffer is full; and sending a status message to a host system.
11,989,126(Parent)
1
Analysis
126 claim 1 recites the same memory device/processing device architecture, storage responsive to a modified-state determination, the active-buffer full determination and flag, and a status message. Its base-address, empty-buffer-list, metadata, physical-region, and message-content limitations merely narrow the patented claim relative to 725 claim 1. The only arguable distinction is whether “responsive to determining” itself requires the processing device to perform the determination.
12,332,786(parent)
2
Analysis
786 claim 2 includes the core claim-1 system and expressly requires indicating the active log memory buffer as full. Using a flag to implement that binary full indication is a predictable choice. 786 also adds synchronization and request/status-request limitations, making its claimed embodiment narrower in other respects.
19/226,962(Instant)
2. The system of claim 1, wherein the memory device is further configured to: responsive to determining that the cache line is in a modified state, invalidate the cache line; append the modified cache line and metadata associated with the modified cache line to the active log memory buffer; and associate a synchronization record with the active log memory buffer prior to indicating the active log memory buffer as full log memory buffer.
11,989,126(Parent)
2
Analysis
126 claim 2 adds the same invalidation, append of the modified cache line and metadata, and synchronization record before the buffer is indicated full. It also contains additional request/status-request limitations, which do not create patentable distinctness for the broader 725 claim.
12,332,786(parent)
2
Analysis
The synchronization, invalidation, append, and synchronization-record operations are materially the same. The principal difference is 725’s express flag; a flag predictably implements 786’s full-buffer indication.
19/226,962(Instant)
3. The system of claim 2, wherein the metadata comprises a cache line status flag indicating whether the cache line is in a modified state and a memory address of the modified cache line.
11,989,126(Parent)
2, 3
Analysis
725 claim 3 combines the synchronization sequence of 126 claim 2 with the metadata definition of 126 claim 3. Both refine the same claim-1 logging system, are technically compatible, and produce no new or unexpected interaction.
12,332,786(parent)
2,3
Analysis
725 claim 3 combines the synchronization sequence of 786 claim 2 with the metadata definition of 786 claim 3 and expressly uses a flag for the full indication. The combined refinements are compatible and predictable.
19/226,962(Instant)
4. The system of claim 1, wherein the memory device is further configured to: store a list of full log memory buffers, wherein the list is accessible by the host system.
11,989,126(Parent)
4
Analysis
126 claim 4 recites the same list of full log memory buffers. “Visible to the host processor” is narrower than “accessible by the host system.”
12,332,786(parent)
2, 4
Analysis
786 claim 4 claims the same host-visible list of full log buffers, and claim 2 claims full-buffer indication. Using a flag for that indication and making the list accessible to the broader host system are predictable variations.
19/226,962(Instant)
5. The system of claim 1, wherein the system comprises a computer express link (CXL) device and wherein the processing device is a memory controller of the CXL device.
11,989,126(Parent)
5
Analysis
The CXL-device and CXL-memory-controller limitation is materially identical.
12,332,786(parent)
2, 5
Analysis
19/226,962(Instant)
6. The system of claim 5, wherein the CXL device comprises one of a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), and a resistive random access memory (RRAM).
11,989,126(Parent)
6
Analysis
The recited DRAM, SDRAM, FeRAM, MRAM, and RRAM alternatives are identical.
12,332,786(parent)
2, 6
Analysis
786 claim 5 claims the same CXL device/controller in the claim-1 system; claim 2 supplies the full-buffer indication. Replacing the indication implementation with a flag is predictable.
19/226,962(Instant)
7. The system of claim 1, wherein the processing device is operatively coupled to the host system, and an interface between the host system and the processing device comprises one of: a compute express link (CXL) or a communication link that allows cache line granularity updates and shares coherency control with the processing device.
11,989,126(Parent)
7
Analysis
The CXL/communication-link alternatives and shared-coherency/cache-line-update functions are materially identical; “host processor” is encompassed by “host system.”
12,332,786(parent)
2, 7
Analysis
786 claim 7 claims the same CXL/coherent communication-link interface, while claim 2 supplies full-buffer indication. The 725 combination produces the expected logging behavior.
19/226,962(Instant)
8. A method comprising: determining, by a processing device, a state of a cache line stored on the memory device; responsive to determining that the cache line is in a modified state, store the cache line in an active log memory buffer associated with the memory device; and associating, with the active log memory buffer, a flag indicating that the active log memory buffer is full; and sending a status message to a host system.
11,989,126(Parent)
8
Analysis
126 claim 8 recites the same logging method, including the full-buffer flag and status message, with additional narrowing base-address, empty-buffer-list, metadata, physical-region, and message-content limitations.
12,332,786(parent)
9
Analysis
786 claim 9 includes the core claim-8 method and expressly requires indicating the active buffer as full. Expressly using a flag for that indication is a predictable implementation.
19/226,962(Instant)
9. The method of claim 8, further comprising: responsive to determining that the cache line is in the modified state, invalidating the cache line; appending the cache line and metadata associated with the cache line to the active log memory buffer; and associating a synchronization record with the active log memory buffer prior to indicating the active log memory buffer as full log memory buffer.
11,989,126(Parent)
9
Analysis
126 claim 9 adds the same invalidation, append, and synchronization-record operations, plus additional request/status-request steps.
12,332,786(parent)
9
Analysis
The invalidation, append, and synchronization-record steps are materially the same. 725’s express flag is an obvious implementation of 786’s full-buffer indication.
19/226,962(Instant)
10. The method of claim 9, wherein the metadata comprises a cache line status flag indicating whether the cache line is in the modified state and a memory address of the cache line.
11,989,126(Parent)
9 & 10
Analysis
725 claim 10 combines the synchronization method of 126 claim 9 with the metadata definition of 126 claim 10. Applying both compatible refinements to the same claim-8 method is a predictable aggregation.
12,332,786(parent)
9, 10
Analysis
725 claim 10 combines 786 claim 9’s synchronization sequence and full indication with 786 claim 10’s metadata definition, using a predictable flag implementation.
19/226,962(Instant)
11. The method of claim 8, further comprising: storing a list of full log memory buffers, wherein the list is accessible by the host system.
11,989,126(Parent)
11
Analysis
The full-buffer-list limitation is materially identical, with “visible” narrower than “accessible.”
12,332,786(parent)
9, 11
Analysis
786 claim 11 claims the same full-buffer list and claim 9 supplies full-buffer indication. “Visible” is narrower than “accessible,” and a flag is a predictable implementation.
19/226,962(Instant)
12. The method of claim 8, wherein the processing device is a memory controller of a computer express link (CXL) device.
11,989,126(Parent)
8 & 5
Analysis
126 claim 8 claims the core method and claim 5 claims the same core system implemented as a CXL device whose processing device is its memory controller. Performing claim 8 with the claim-5 controller is the expected operation of that claimed apparatus.
12,332,786(parent)
9, 12
Analysis
786 claim 12 claims the same CXL memory controller in method form and claim 9 supplies full-buffer indication. Adding the express flag does not produce a patentably distinct method.
19/226,962(Instant)
13. The method of claim 12, wherein the CXL device comprises one of a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), and a resistive random access memory (RRAM).
11,989,126(Parent)
8 & 6(also 16)
Analysis
126 claim 6 claims the identical memory-type alternatives in the CXL system, while claim 8 claims the logging method. 126 claim 16 separately claims executable instructions for the same operations on a CXL memory controller having the same memory-type alternatives. The 725 method is an obvious statutory-form variation.
12,332,786(parent)
9, 13
Analysis
786 claim 13 claims the identical memory-type alternatives and claim 9 supplies full-buffer indication. The explicit flag is a predictable status mechanism.
19/226,962(Instant)
14. The method of claim 8, wherein the processing device is operatively coupled to the host system, and an interface between the host system and the processing device comprises one of: a compute express link (CXL) or a communication link that allows cache line granularity updates and shares coherency control with the processing device.
11,989,126(Parent)
8 & 7(also 17)
Analysis
126 claim 7 claims the same interface limitation in the corresponding system, and claim 17 claims it in executable-instruction form. Applying the claim-8 method through that claimed interface is predictable and does not alter the logging result.
12,332,786(parent)
9, 14
Analysis
786 claim 14 claims the same interface in method form and claim 9 supplies full-buffer indication. The express flag is an obvious implementation.
19/226,962(Instant)
15. A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to: determining a state of a cache line stored on the memory device; responsive to determining that the cache line is in a modified state, store the cache line in an active log memory buffer associated with the memory device; and associating, with the active log memory buffer, a flag indicating that the active log memory buffer is full; and sending a status message to a host system.
11,989,126(Parent)
12
Analysis
126 claim 12 is a narrower computer-readable-medium claim. It expressly reads cache-line state, stores the modified line and metadata, determines the active buffer is full, associates the flag, and sends the status message, while adding base-address, buffer-list, initiation, and session-ID limitations.
12,332,786(parent)
16
Analysis
786 claim 16 includes the core CRM of claim 15 and expressly requires indicating the active buffer as full. A flag is a predictable implementation of that claimed indication.
19/226,962(Instant)
16. The non-transitory computer-readable storage medium of claim 1, further comprising executable instructions that, when executed by the processing device, cause the processing device to: responsive to determining that the cache line is in the modified state, invalidate the cache line; append the cache line and the metadata associated with the cache line to the active log memory buffer; and associate a synchronization record with the active log memory buffer prior to indicating the active log memory buffer as full log memory buffer.
11,989,126(Parent)
13
Analysis
126 claim 13 adds the same invalidation, append, and synchronization-record operations, plus additional synchronization/status-request limitations.
12,332,786(parent)
16
Analysis
The synchronization, invalidation, append, and synchronization-record instructions are materially the same; the difference is 725’s explicit flag implementation.
19/226,962(Instant)
17. The non-transitory computer-readable storage medium of claim 16, wherein the metadata comprises a cache line status flag indicating whether the cache line is in a modified state and a memory address of the modified cache line.
11,989,126(Parent)
13, 14
Analysis
725 claim 17 combines the synchronization sequence of 126 claim 13 with the metadata definition of 126 claim 14. The refinements address the same record appended to the same active log buffer and are directly compatible.
12,332,786(parent)
16, 17
Analysis
725 claim 17 combines the synchronization/full-indication instructions of 786 claim 16 with the metadata definition of claim 17 and uses a predictable flag implementation.
19/226,962(Instant)
18. The non-transitory computer-readable storage medium of claim 15, further comprising executable instructions that, when executed by the processing device, cause the processing device to: store a list of full log memory buffers, wherein the list is accessible by the host system.
11,989,126(Parent)
15
Analysis
The full-buffer-list limitation is materially identical, with “visible” narrower than “accessible.”
12,332,786(parent)
16, 18
Analysis
786 claim 18 claims the same full-buffer list and claim 16 supplies full-buffer indication. The flag and broader “accessible by host system” wording are predictable variations.
19/226,962(Instant)
19. The non-transitory computer-readable storage medium of claim 15, wherein the processing device is a memory controller of a computer express link (CXL) device.
11,989,126(Parent)
17
Analysis
126 claim 16 is a narrower CRM species requiring the processing device to be the memory controller of a CXL device and additionally specifying memory type. That narrower species falls within 725 claim 19.
12,332,786(parent)
16, 19
Analysis
786 claim 19 claims the same CXL memory controller in CRM form and claim 16 supplies full-buffer indication. Using a flag for the indication is predictable.
19/226,962(Instant)
20. The non-transitory computer-readable storage medium of claim 15, wherein the processing device is operatively coupled to the host system, and an interface between the host system and the processing device comprises one of: a compute express link (CXL) or a communication link that allows cache line granularity updates and shares coherency control with the processing device.
11,989,126(Parent)
17
Analysis
The claimed host/processing-device interface and its alternatives are materially identical.
12,332,786(parent)
16, 20
Analysis
786 claim 20 claims the same interface in CRM form and claim 16 supplies full-buffer indication. The express flag does not create patentable distinctness.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 7-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A. Claims 8–14: “the memory device” lacks express antecedent basis
Recommended correction: “determining, by a processing device, a state of a cache line stored on a memory device.”
B. Claims 15–20: the same “memory device” defect appears in the medium claim.
Recommended correction: replace the first occurrence of “the memory device” in claim 15 with “a memory device.”
C. Claims 16–17: “the metadata” lacks antecedent basis.
Recommended correction: “append the cache line and metadata associated with the cache line to the active log memory buffer.”
D. Claims 7, 14, and 20: “shares coherency control” is ambiguous.
Claims 7, 14, and 20 recite a communication link that “allows cache line granularity updates and shares coherency control with the processing device.” The grammar makes the communication link itself the actor that “shares” control, but the claim does not identify the other participant in the sharing relationship or define what constitutes “coherency control”. The language admits multiple readings. It could mean that the host and processing device participate in a common coherency protocol; that the communication link distributes coherency-management functions; or that the memory device and processing device jointly control cache coherence. Those alternatives may have different technical scopes.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim(s) 16-17 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 16 begins: “The non-transitory computer-readable storage medium of claim 1 . . . .” Claim 1 is a system claim, not a computer-readable-medium claim. Claim 16 consequently does not incorporate the same statutory class or subject matter that it purports to further limit. The intended dependency is plainly claim 15, the independent computer-readable-medium claim.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 8, 11, 15, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grayson et al.(20120317367), and further in view of Wang et al.(20190179764).
As per claim 1, Grayson discloses:
A system(Grayson, [0017 -- FIG. 1, in block diagram form, is a data processing system]) comprising:
a memory device(Grayson, [0021 -- FIG. 3 illustrates, in block diagram form, system cache 26 in accordance with one embodiment of the present invention. System cache 26 includes cache control circuitry 40 and a cache array 42 bidirectionally coupled to cache control circuitry], [0017 -- Memory controller 28 is bidirectionally coupled to each of system cache 26 and system memory 30.]);
and a processing device, operatively coupled with the memory device(Grayson, [0017 -- System cache 26 is also bidirectionally coupled to cache cleaning circuitry 24 via conductor 25, outside of system interconnect 20. Memory controller 28 is bidirectionally coupled to each of system cache 26 and system memory ]), to:
determining a state of a cache line stored on the memory device(Grayson, [0030 -- This access can be from any master in system 10. Flow proceeds to decision diamond 62 in which it is determined if the current access is one that causes a cache line within system 10 to go dirty or is one that indicates an intent to make a cache line dirty as a result of a subsequent access], [0031 -- Therefore, if no match occurs, flow proceeds to decision diamond 68 in which it is determined if the current access is one that causes a cache line to go dirty]);
and associating, with the active log memory buffer, a flag indicating that the active log memory buffer is full(Grayson, [0035 -- If there is no clean currently in progress, flow proceeds to decision diamond 86 where it is determined if there is a tracking entry within tracking array 46 whose count value meets or exceeds a predetermined count threshold; Flow proceeds to block 90 in which clean in progress indicator 55 is set to indicate that a clean is now in progress.]);
and sending a status message to a host system(Grayson, [0025 -- . Similarly, if system cache 26 is not present, cache cleaning circuitry 24, upon a certain number of dirty cache lines corresponding to a same tracked region being achieved, can request the caches of the processors (such as cache 14 and/or 18) to flush or clean its cache lines which correspond to the selected tracked region. This may be done, for example, by broadcasting a flush or clean command to the masters, such as processor], [0028 -- it may be a processor identifier to identify cache 14 or 18. Even without system cache 26, the identifier field may not be needed if, for example, system interconnect 20 can broadcast information to all masters.], [0036 -- In the case of the cache lines being present in other caches, such as cache 14 or cache 18, the clean or flush transaction can be sent to the appropriate cache by either broadcasting the clean or flush transaction or by using the processor indicator of the selected state for cache field of the selected tracking entry to provide the clean or flush transaction to the appropriate processor cache]).
Grayson does not explicitly disclose the following however Wang discloses:
responsive to determining that the cache line is in a modified state, store the cache line in an active log memory buffer associated with the memory device(Wang, [0039 -- After the data is written to the cache line 200, if the dirty bit associated with the cache line is in a dirty cache line entry 302 in the dirty bit tracker cache 152, the dirty bit is changed from a logical ‘0’ (clean) to a logical ‘1’ (dirty)]);
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Wang into the system of Grayson for the benefit of an apparatus that uses the dirty cache line entries to quickly and efficiently track locations of the dirty cache lines in the cache(Wang, 0031).
As per claim 4, the system of claim 1 is incorporated, in addition, Grayson discloses:
wherein the memory device is further configured to:
store a list of full log memory buffers, wherein the list is accessible by the host system(Grayson, [0024 -- Tracking array 46 includes Z sets (set 0-set Z-1), in which each set includes X ways (way 0-way X-1). The intersection of a set and a way provides a tracking array entry. Each tracking entry of tracking array 46 includes a tag, status information, a tracking bitfield, and a count value]).
As per claim 8, Grayson discloses:
A method comprising:
determining, by a processing device, a state of a cache line stored on the memory device(Grayson, [0030 -- This access can be from any master in system 10. Flow proceeds to decision diamond 62 in which it is determined if the current access is one that causes a cache line within system 10 to go dirty or is one that indicates an intent to make a cache line dirty as a result of a subsequent access], [0031 -- Therefore, if no match occurs, flow proceeds to decision diamond 68 in which it is determined if the current access is one that causes a cache line to go dirty]);
and associating, with the active log memory buffer, a flag indicating that the active log memory buffer is full(Grayson, [0035 -- If there is no clean currently in progress, flow proceeds to decision diamond 86 where it is determined if there is a tracking entry within tracking array 46 whose count value meets or exceeds a predetermined count threshold; Flow proceeds to block 90 in which clean in progress indicator 55 is set to indicate that a clean is now in progress.]);
and sending a status message to a host system(Grayson, [0025 -- . Similarly, if system cache 26 is not present, cache cleaning circuitry 24, upon a certain number of dirty cache lines corresponding to a same tracked region being achieved, can request the caches of the processors (such as cache 14 and/or 18) to flush or clean its cache lines which correspond to the selected tracked region. This may be done, for example, by broadcasting a flush or clean command to the masters, such as processor], [0028 -- it may be a processor identifier to identify cache 14 or 18. Even without system cache 26, the identifier field may not be needed if, for example, system interconnect 20 can broadcast information to all masters.], [0036 -- In the case of the cache lines being present in other caches, such as cache 14 or cache 18, the clean or flush transaction can be sent to the appropriate cache by either broadcasting the clean or flush transaction or by using the processor indicator of the selected state for cache field of the selected tracking entry to provide the clean or flush transaction to the appropriate processor cache]).
Grayson does not explicitly disclose the following, however Wang discloses:
responsive to determining that the cache line is in a modified state, store the cache line in an active log memory buffer associated with the memory device(Wang, [0039 -- After the data is written to the cache line 200, if the dirty bit associated with the cache line is in a dirty cache line entry 302 in the dirty bit tracker cache 152, the dirty bit is changed from a logical ‘0’ (clean) to a logical ‘1’ (dirty)]);
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Wang into the system of Grayson for the benefit of an apparatus that uses the dirty cache line entries to quickly and efficiently track locations of the dirty cache lines in the cache(Wang, 0031).
Claim(s) 11 is/are directed to method steps that are implemented by the system features of claim(s) 4 respectively, and therefore similar mappings are incorporated.
As per claim 15, Grayson discloses:
A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device(Grayson, [0018 -- In operation, multiple masters coupled to system interconnect 20, such as processors 12 and 16 or peripherals 22, may access system memory 30 for reading and writing data. Accesses to system memory 30 are controlled by memory controller 28 and gated by system cache 26. That is, in the illustrated embodiment, accesses to system memory 30 are first provided via system cache 26. In one embodiment, cache cleaning circuitry 24 monitors the writes performed by these masters to system memory]), cause the processing device to:
determining a state of a cache line stored on the memory device(Grayson, [0030 -- This access can be from any master in system 10. Flow proceeds to decision diamond 62 in which it is determined if the current access is one that causes a cache line within system 10 to go dirty or is one that indicates an intent to make a cache line dirty as a result of a subsequent access], [0031 -- Therefore, if no match occurs, flow proceeds to decision diamond 68 in which it is determined if the current access is one that causes a cache line to go dirty]);
and associating, with the active log memory buffer, a flag indicating that the active log memory buffer is full(Grayson, [0035 -- If there is no clean currently in progress, flow proceeds to decision diamond 86 where it is determined if there is a tracking entry within tracking array 46 whose count value meets or exceeds a predetermined count threshold; Flow proceeds to block 90 in which clean in progress indicator 55 is set to indicate that a clean is now in progress.]);
and sending a status message to a host system(Grayson, [0025 -- . Similarly, if system cache 26 is not present, cache cleaning circuitry 24, upon a certain number of dirty cache lines corresponding to a same tracked region being achieved, can request the caches of the processors (such as cache 14 and/or 18) to flush or clean its cache lines which correspond to the selected tracked region. This may be done, for example, by broadcasting a flush or clean command to the masters, such as processor], [0028 -- it may be a processor identifier to identify cache 14 or 18. Even without system cache 26, the identifier field may not be needed if, for example, system interconnect 20 can broadcast information to all masters.], [0036 -- In the case of the cache lines being present in other caches, such as cache 14 or cache 18, the clean or flush transaction can be sent to the appropriate cache by either broadcasting the clean or flush transaction or by using the processor indicator of the selected state for cache field of the selected tracking entry to provide the clean or flush transaction to the appropriate processor cache]).
Grayson does not explicitly disclose the following, however Wang discloses:
responsive to determining that the cache line is in a modified state, store the cache line in an active log memory buffer associated with the memory device(Wang, [0039 -- After the data is written to the cache line 200, if the dirty bit associated with the cache line is in a dirty cache line entry 302 in the dirty bit tracker cache 152, the dirty bit is changed from a logical ‘0’ (clean) to a logical ‘1’ (dirty)]);
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Wang into the system of Grayson for the benefit of an apparatus that uses the dirty cache line entries to quickly and efficiently track locations of the dirty cache lines in the cache(Wang, 0031).
Claim(s) 18 is/are directed to CRM processing device features that are implemented by the system features of claim(s) 4 respectively, and therefore similar mappings are incorporated.
Claim(s) 2-3, 9-10, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grayson et al.(20120317367), and further in view of Wang et al.(20170179764), and further in view of Hahn et al.(20230153027),
As per claim 2, the system of claim 1 is incorporated, in addition, Grayson, in view of Wang does not disclose the following, however Hahn discloses:
wherein the memory device is further configured to:
responsive to determining that the cache line is in a modified state, invalidate the cache line(Hahn, [0048 -- If a threshold has been met at 516, then the data is mirrored to the memory device at 518 as HMB cache, the HMB log is emptied at 520, and the delta data is deleted from SRAM at 522 as the HMB cache and the HMB are identical at this point in time]);
append the modified cache line and metadata associated with the modified cache line to the active log memory buffer(Hahn, [0048 -- If the link is active at 512, then the delta data is written to HMB]);
and associate a synchronization record with the active log memory buffer prior to indicating the active log memory buffer as full log memory buffer(Hahn, [0048 -- If a threshold has been met at 516, then the data is mirrored to the memory device at 518 as HMB cache]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Hahn into the system of Grayson, Wang for the benefit of a memory device and controller coupled to the memory device, where the controller is configured to determine whether a link is active between a host memory buffer (HMB) and the controller and write data into a cache, and thus provides a balance between controller cost and performance. (Hahn, 0002).
As per claim 3, the system of claim 2 is incorporated, in addition, Grayson does not explicitly disclose the following, however Wang discloses:
wherein the metadata comprises a cache line status flag indicating whether the cache line is in a modified state and a memory address of the modified cache line(Wang, [0033 -- Each bit in the dirty bit vector 304 corresponds to one of the cache lines 200 in the eight consecutive cache rows 400 in the cache 136. The state of the dirty bit in the dirty bit vector 304 indicates whether the corresponding cache line 200 in the cache 136 is dirty or clean.], [0028 -- The metadata and Error Correction Code (ECC) 204 includes ECC 214, tag 206, valid bit 208 and dirty bit ]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Wang into the system of Grayson for the benefit of an apparatus that uses the dirty cache line entries to quickly and efficiently track locations of the dirty cache lines in the cache(Wang, 0031).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Hahn into the system of Grayson, Wang for the benefit of a memory device and controller coupled to the memory device, where the controller is configured to determine whether a link is active between a host memory buffer (HMB) and the controller and write data into a cache, and thus provides a balance between controller cost and performance. (Hahn, 0002).
Claim(s) 9-10 are directed to method steps that are implemented by the system features of claim(s) 2-3 respectively, and therefore similar mappings are incorporated.
Claim(s) 16-17 are directed to CRM processing device features that are implemented by the system features of claim(s) 2-3 respectively, and therefore similar mappings are incorporated.
Claim(s) 5-7, 12-14, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Grayson et al.(20120317367), and further in view of Wang et al.(20170179764), and further in view of Malladi et al.(20210374056),
As per claim 5, the system of claim 1 is incorporated, in addition, Grayson in view of Wang does not explicitly disclose the following, however Malladi discloses:
wherein the system comprises a computer express link (CXL) device and wherein the processing device is a memory controller of the CXL device(Malladi, [0081 -- Each of the servers 105 may include a plurality of memory modules 135 connected to the server-linking switch 112 through the enhanced capability CXL switch 130 and through a plurality of PCIe connectors]).
Therefore it would have been been obvious to a POSITA at the time of filing to incorporate the features of Malladi into the system of Grayson, Wang for the benefit of allowing processing resource of a server to access a memory resource of another server while minimizing processing resources of the server. Obtains system that reduces power consumption and bandwidth of devices on a network, and increases speed and/or efficiency of communications between devices(Malladi, 0012).
As per claim 6, the system of claim 5 is incorporated, in addition, Grayson in view of Wang does not disclose the following, however Malladi discloses:
wherein the CXL device comprises one of a dynamic random granular access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a ferroelectric random access memory (FeRAM), a magnetic random access memory (MRAM), and a resistive random access memory (RRAM)(Malladi, [0058 -- Each of the memory modules 135 may have a CXL interface and may include a controller 137 (e.g., an FPGA, an ASIC, a processor, and/or the like) for translating between CXL packets and the memory interface of the memory dies, e.g., the signals suitable for the memory technology of the memory in the memory module 135. As used herein, the “memory interface” of the memory dies is the interface that is native to the technology of the memory dies, e.g., in the case of DRAM e.g., the memory interface may be word lines and bit lines], [0067 -- The memory modules 135 may be grouped by type, form factor, or technology type (e.g., DDR4, DRAM, LDPPR, high bandwidth memory (HBM), or NAND flash, or other persistent storage (e.g., solid state drives incorporating NAND flash)). Each memory module may have a CXL interface and include an interface circuit for translating between CXL packets and signals suitable for the memory in the memory module 135. In some embodiments, these interface circuits are instead in the enhanced capability CXL switch 130, and each of the memory modules 135 has an interface that is the native interface of the memory in the memory module ]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Malladi into the system of Grayson, Wang for the benefit of allowing processing resource of a server to access a memory resource of another server while minimizing processing resources of the server. Obtains system that reduces power consumption and bandwidth of devices on a network, and increases speed and/or efficiency of communications between devices(Malladi, 0012).
As per claim 7, the system of claim 1 is incorporated, in addition, Grayson in view of Wang does not explicitly disclose the following, however Malladi discloses:
wherein the processing device is operatively coupled to the host system, and an interface between the host system and the processing device comprises one of: a compute express link (CXL) or a communication link that allows cache line granularity updates and shares coherency control with the processing device(Malladi, [0007 -- In another embodiment, the cache coherent protocol can include a compute express link (CXL) protocol and wherein the device further comprises a profiler that determines at least one capability associated with the device and provides the capability to a host.], [0081 -- The server-linking switch 112 may operate as a master, and each of the enhanced capability CXL switches 130 may operate as a slave, as discussed in further detail below.], [0085 -- Such a load-store interface may extend the coherence domain beyond an individual server, or CPU or host, and may involve a physical medium that is either electrical or optical (e.g., an optical connection with electrical-to-optical transceivers at both ends).]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Malladi into the system of Grayson, Wang for the benefit of allowing processing resource of a server to access a memory resource of another server while minimizing processing resources of the server. Obtains system that reduces power consumption and bandwidth of devices on a network, and increases speed and/or efficiency of communications between devices(Malladi, 0012).
Claim(s) 12-14 are directed to method steps that are implemented by the system features of claim(s) 5-7 respectively, and therefore similar mappings are incorporated.
Claim(s) 19-20 is/are directed to CRM processing device features that are implemented by the system features of claim(s) 5, 7, respectively, and therefore similar mappings are incorporated.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Moon et al.(20170192888) where the memory system comprises a nonvolatile memory that is electrically connected to a data bus. A dynamic random access memory (DRAM) is connected to the data bus. The DRAM is configured to load data of a cache line that caches data stored in the nonvolatile memory and to store a dirty flag. A memory controller is configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of the cache line with data of the nonvolatile memory in units of the cache units based on the dirty flag(Moon, abstract).
Calciu et al.(20200034200) where the method involves receiving a request for a page from running application. A page for the running application is obtained from a remote host responsible for the page. Determination is made to check whether a cache line of the page is dirty due to the activities of the running application by monitoring cache coherence events relating to the cache line of the page. Dirty cache lines of the page are periodically copied to the remote host. Determination is made to check whether number of dirty cache lines in a page exceeds a threshold. A page is marked as dirty when the number of dirty cache lines in a page exceeds the threshold(Calciu, abstract).
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights