DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office Action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Election/Restrictions
Applicant's election without traverse of Species I: Figure 3 in the reply filed on 04/29/2026 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent 12,356,814 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
The following is an example for comparing claim 1 of this application and claims 1 and 14 of U.S. Patent 12,356,814 B2:
Claim 1 of this application
Claims 1 and 14 of U.S. Patent 12,356,814 B2
1. A display panel, comprising:
a pixel driving circuit, wherein the pixel driving circuit comprises a driving transistor and an eighth transistor, a first terminal of the eighth transistor is connected to a first terminal of the driving transistor, a second terminal of the eighth transistor is connected to a third initial signal line, and wherein the display panel further comprises:
a base substrate;
a first active layer, located on a side of the base substrate, wherein the first active layer comprises an eighth active portion, a second active portion, a ninth active portion, a tenth active portion, and an eleventh active portion, the eighth active portion is connected between the ninth active portion and the tenth active portion, the eleventh active portion is connected to a side of the second active portion, the eighth active portion is used to form a channel region of the eighth transistor, the second active portion is used to form a channel region of the driving transistor, and the ninth active portion is electrically connected to the eleventh active portion;
a plurality of pixel driving circuits, the plurality of pixel driving circuits comprising a first pixel driving circuit and a second pixel driving circuit arranged adjacently in the first direction, wherein the first pixel driving circuit is at least partially mirror-symmetrical with the second pixel driving circuit;
a fourth conductive layer, located on a side of the first conductive layer away from the base substrate, the fourth conductive layer comprising a first bridge part, and the first bridge part being connected to the third initial signal line and the tenth active portion respectively through via holes; and
the third initial signal line, electrically connected to the tenth active portion.
1. A display panel, wherein the display panel comprises a pixel driving circuit, the pixel driving circuit comprises a driving transistor and an eighth transistor, a first terminal of the eighth transistor is connected to a first terminal of the driving transistor, a second terminal of the eighth transistor is connected to a third initial signal line, and the display panel further comprises:
a base substrate;
a first active layer, located on a side of the base substrate, wherein the first active layer comprises an eighth active portion, a second active portion, a ninth active portion, a tenth active portion, and an eleventh active portion, the eighth active portion is connected between the ninth active portion and the tenth active portion, the eleventh active portion is connected to a side of the second active portion, the eighth active portion is used to form a channel region of the eighth transistor, the second active portion is used to form a channel region of the driving transistor, and the ninth active portion is electrically connected to the eleventh active portion; a first conductive layer, located on a side of the first active layer away from the base substrate, wherein the first conductive layer comprises a first reset signal line and a first conductive portion, an orthographic projection on the base substrate of the first reset signal line extends along a first direction and covers an orthographic projection on the base substrate of the eighth active portion, a partial structure of the first reset signal line is used to form a gate of the eighth transistor, an orthographic projection on the base substrate of the first conductive portion covers an orthographic projection on the base substrate of the second active portion, and the first conductive portion is used to form a gate of the driving transistor; and the third initial signal line, electrically connected to the tenth active portion.
14. The display panel according to claim 1, wherein the display panel comprises a plurality of pixel driving circuits, the plurality of pixel driving circuits comprising a first pixel driving circuit and a second pixel driving circuit arranged adjacently in the first direction; and the first pixel driving circuit is at least partially mirror-symmetrical with the second pixel driving circuit.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows: Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1 and 14 of U.S. Patent 12,356,814 B2, either singularly or in combination, contains each and every element and/or render each and every element of claim 1 of the instant application obvious. The claims of the instant application therefore are not patently distinct from the issued patent claims and as such are unpatentable over obvious-type double patenting.
Claims 2-20 are similarly rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent 12,356,814 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
EXAMINER’S NOTE
The claims are allowable over prior art, and will be allowed once the afore-mentioned double patenting rejection is resolved.
U.S. Patent Application Publication 2024/0257734 A1 to Zhang et al. discloses a first pixel driving circuit, wherein the first pixel driving circuit comprises a low-temperature polysilicon transistor and an oxide transistor. The display panel further comprises: a base substrate, a first conductive layer and a third conductive layer, wherein the first conductive layer comprises a first gate line, and part of the structure of the first gate line is used for forming a gate electrode of the low-temperature polysilicon transistor; the third conductive layer comprises a second gate line, and part of the structure of the second gate line is used for forming a gate electrode of the oxide transistor; and the orthographic projection of the first gate line on the base substrate extends in a first direction.
Foreign Publication CN 107610651 A to Xiang et al. discloses a pixel circuit that comprises a light emitting element, a driving transistor, a first reset module, a second reset module, a data writing module, a threshold compensating module and a holding module. Referring to FIG. 4, on the basis of the above embodiment, the data writing module includes a first transistor M1, and the threshold compensation module includes a second transistor M2. The reset module includes a sixth transistor M6. The first electrode of the first transistor M1 is electrically connected to the data line data, the second electrode is electrically connected to the first electrode of the driving transistor 12, and the gate is electrically connected to the first scan line S1. The first electrode of the transistor M2 is electrically connected to the second electrode of the driving transistor 12, the second electrode is electrically connected to the gate of the driving transistor 12, and the gate is electrically connected to the first scan line S1; the first electrode of the sixth transistor M6 is connected to The third level signal line Vref3 is electrically connected, the second electrode is electrically connected to the gate of the driving transistor 12, and the gate is electrically connected to the second scan line S2; the first electrode of the first capacitor Cst1 and the gate of the driving transistor 12 are electrically connected. Connecting, the second electrode of the first capacitor Cst1 is electrically connected to the first level signal line PVDD; the second electrode of the light emitting device 11 is electrically connected to the second level signal line PVEE. The light emitting control module includes a fourth transistor M4 and a fifth transistor M5. The first electrode of the fourth transistor M4 is electrically connected to the first level signal line PVEE, the second electrode is electrically connected to the first electrode of the driving transistor 12, and the gate electrode is electrically connected. The first light emitting signal line Emit1 is electrically connected; the first electrode of the fifth transistor M5 is electrically connected to the second electrode of the driving transistor 12, the second electrode is electrically connected to the first electrode of the light emitting element 11, and the gate is electrically connected to the first light emitting signal line. Emit1 is electrically connected. The second reset module includes a seventh transistor M7; the first electrode of the seventh transistor M7 is electrically connected to the third level signal line Vref3, the second electrode is electrically connected to the first electrode of the drive transistor 12, and the gate and the first control signal Line K1 is electrically connected.
However, none of the above teach or fairly suggest the display panel and associated with it the display device as claimed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABHISHEK SARMA whose telephone number is (571)272-9887. The examiner can normally be reached on Mon - Fri 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached on 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ABHISHEK SARMA/
Primary Examiner, Art Unit 2621
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