DETAILED ACTION
This is a first office action in response to application No. 19/227,200 filed on 06/03/2025, in which claims 1 - 15 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC §102
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okutani “US 2005/0286307”.
Re-claim 1, Okutani teaches a data driver (fig. 6; 2-1) comprising:
an output circuit (fig. 6; 206) configured to output a pixel data as an image data voltage in analog form; (par. [0046] The D/A converter 205 performs D/A conversions upon the shifted video signals D.sub.1', D.sub.2', . . . , D.sub.384', using the multi-gradation voltages such as 64 gradation voltages to generate analog voltages AV.sub.1, AV.sub.2, . . . , AV.sub.384 which are applied via the output buffer 206 to the switch circuit 207.)
a selection circuit (figs. 6 & 7A-7B; 203A) configured to connect one of an output end of the output circuit (fig. 6; 206 and par. [0046]) or a wire for transmitting a black data voltage to a data line; (par. [0059] Thus, when the reset signal RST is low (="0"), the data latch circuit 203A is reset, so that the black data BD is applied to the data lines DL.sub.1, DL.sub.2, . . . , DL.sub.384. and par. [0062] Next, at time t2, when a reset signal RST is changed from high to low, reset-type D-type latch circuits LC1 of the data latch circuit 203A are reset, so that the data latch circuit 203A generates black data (=000000). As a result, the black data is supplied via the level shifter 204 and the D/A converter 205 to the output buffer 206. Thus, a black voltage corresponding to the black data is applied to the data line DL.sub.1.) and par. [0062]) and
a control circuit (it is well known that all electronic devices have a control circuit) configured to control the selection circuit (figs. 6 & 7A-7B; 203A) so that the image data voltage and the black data voltage are alternately output at a time interval. (fig. 9 and par. [0065] Thus, in FIG. 9, a gradation voltage and a black voltage are alternately switched. In this case, the polarity of the gradation voltage is opposite to that of the black voltage during one strobe signal period, thus removing the residual image effect of a moving image.)
Re-claim 9, Okutani teaches a display device (fig. 1) comprising:
a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged; (fig. 1 and par. [0036] drive the 3840 data lines DL, ten data line drivers 2-1, 2-2, . . . , 2-10 each for driving 384 data lines are provided along a horizontal edge of the LCD panel 1. On the other hand, in order to drive the 1024 scan lines SL, four gate line drivers 3-1, 3-2, 3-3 and 3-4 each for driving 256 gate lines are provided along a vertical edge of the LCD panel 1.)
a data driver configured to output a data voltage to the plurality of data lines; (fig. 1; data line drivers 2-1, 2-2, . . . , 2-10) and
a gate driver configured to output a gate signal to the plurality of gate lines; (fig. 1; gate line drivers 3-1, 3-2, 3-3 and 3-4)
wherein the data driver comprises:
an output circuit (fig. 6; 206) configured to output a pixel data as an image data voltage in analog form; (par. [0046] The D/A converter 205 performs D/A conversions upon the shifted video signals D.sub.1', D.sub.2', . . . , D.sub.384', using the multi-gradation voltages such as 64 gradation voltages to generate analog voltages AV.sub.1, AV.sub.2, . . . , AV.sub.384 which are applied via the output buffer 206 to the switch circuit 207.)
a selection circuit (figs. 6 & 7A-7B; 203A) configured to connect one of an output end of the output circuit (fig. 6; 206 and par. [0046]) or a wire for transmitting a black data voltage to a data line; (par. [0059] Thus, when the reset signal RST is low (="0"), the data latch circuit 203A is reset, so that the black data BD is applied to the data lines DL.sub.1, DL.sub.2, . . . , DL.sub.384. and par. [0062] Next, at time t2, when a reset signal RST is changed from high to low, reset-type D-type latch circuits LC1 of the data latch circuit 203A are reset, so that the data latch circuit 203A generates black data (=000000). As a result, the black data is supplied via the level shifter 204 and the D/A converter 205 to the output buffer 206. Thus, a black voltage corresponding to the black data is applied to the data line DL.sub.1.) and par. [0062]) and
a control circuit (it is well known that all electronic devices have a control circuit) configured to control the selection circuit so that the image data voltage and the black data voltage are alternately output at a predetermined time interval. (fig. 9 and par. [0065] Thus, in FIG. 9, a gradation voltage and a black voltage are alternately switched. In this case, the polarity of the gradation voltage is opposite to that of the black voltage during one strobe signal period, thus removing the residual image effect of a moving image.)
Claim Rejections - 35 USC §103
4 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 2 - 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Okutani “US 2005/0286307” in view of Takasugi “US 2020/0082762”.
Re-claim 2, Okutani teaches all the limitations of claim 1 but does not explicitly teach wherein the control circuit is configured to control the selection circuit such that, during each frame period, the image data voltage is output at the first output timing of a gate signal and the black data voltage is output at the second output timing elapsed by the predetermined time interval from the first output timing.
However, Takasugi teaches wherein the control circuit is configured to control the selection circuit such that, during each frame period, the image data voltage is output at the first output timing of a gate signal (fig.1 and par. [0034-0039] The gate lines GL1 to GLn may include a plurality of lines respectively providing gate signals. and par. [0042] The shift register 500 generates gate signals, while sequentially shifting the gate clocks output from the level shifter 400.) and the black data voltage is output at the second output timing elapsed by the predetermined time interval from the first output timing. (fig. 3 and par. [0049] Referring to FIG. 3, the first scan signal SCAN1 and the first sense signal SEN1 are set to an output period of 1H or more and overlap driving is performed. The output period of the first scan signal SCAN1 and the first sense signal SEN1 refers to a period maintained at a turn-on voltage. The 1H period refers to a period of writing a data voltage into the pixels arranged in one pixel line HL. Each of the scan signals SCAN includes a scan signal SCI for an image (or an image scan signal SCI) and a scan signal SCB for BDI (or a BDI scan signal SCB). The image scan signal SCI is synchronized with a timing for writing an image data voltage in IDW driving or a timing for writing a data voltage for sensing in SDW driving. The BDI scan signal SCB is synchronized with a timing for writing a black image in BDI driving.)
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of the combination with the teachings of Takasugi for improving concentration of brightness deviation among certain pixel lines. (par. [0095])
Re-claim 3, Okutani in view of Takasugi teaches all the limitations of claim 2, Takasugi teaches wherein the time interval is set to nx horizontal period, where n is a natural number. (par. [0005] The timing controller controls operations of the data driver and the gate driver to sequentially write an image data voltages to n (n is a natural number greater than 1)
Re-claim 10, is rejected as applied to claim 2 above because the scope and contents of the recited limitations are substantially the same.
7. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Okutani “US 2005/0286307” in view of Lee “US 2010/0045644”.
Re-claim 8, Okutani teaches all the limitations of claim 1 but does not explicitly teach wherein the selection circuit includes: a plurality of first switches connected between the output end of the output circuit and the data line; and
a plurality of second switches connected between the wire and the data line.
However, Lee teaches wherein the selection circuit includes: a plurality of first switches connected between the output end of the output circuit and the data line; and a plurality of second switches connected between the wire and the data line. (fig. 9 and par. [0081])
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of the combination with the teachings of improving the image display quality. (par. [0087])
8. Claims 4 - 7 and 11 - 15 are rejected under 35 U.S.C. 103 as being unpatentable over Okutani “US 2005/0286307” in view of Takasugi “US 2020/0082762” and further in view of Lee “US 2013/0208021”.
Re-claim 4, Okutani in view of Takasugi teaches all the limitations of claim 2 but do not explicitly teach wherein the control circuit is configured to control the selection circuit such that, for a red sub-pixel, the red image data voltage is output at the first output timing and the black data voltage is output at the second output timing.
However, Lee teaches wherein the control circuit (fig. 4; 5) is configured to control the selection circuit such that, for a red sub-pixel, the red image data voltage is output at the first output timing (fig. 8A and 10A; red data R11, R21, R31 and R41) and the black data voltage is output at the second output timing. (fig. 8A and 10A; black data)
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of the combination with the teachings of Lee in order to image data preventing the disruptive pattern in the image display according to the image data may be provided. (par. [0206])
Re-claim 5, Okutani and Takasugi in view of Lee teaches all the limitations of claim 4, Lee teaches wherein the control circuit is configured to control the selection circuit such that, for a green sub-pixel, a green image data voltage is output at the first output timing (fig. 8A and 10A; green data G12, G22, G32 and G42) and the same image data voltage as the green image data voltage is output at the second output timing. (par. [0148])
Re-claim 6, Okutani and Takasugi in view of Lee teaches all the limitations of claim 5, Lee teaches wherein the control circuit is configured to control the selection circuit such that, for a blue sub-pixel, a blue image data voltage is output at the first output timing (fig. 8A and 10A; blue data B11, B21, B31 and B41) and the same image data voltage as the blue image data voltage is output at the second output timing. (par. [0148])
Re-claim 7, Okutani and Takasugi in view of Lee teaches all the limitations of claim 6, Lee teaches a memory in which pixel data corresponding to the green image data voltage (fig. 8A and 10A; green data G12, G22, G32 and G42) and the blue image data voltage (fig. 8A and 10A; blue data B11, B21, B31 and B41) that are output at the first output timing are stored. (par. [0087] the output data B11, B21, B31, and B41 transmitted to the first pixels corresponding to the third pixel column are the blue data emitting the blue light, and the output data G12, G22, G32, and G42 transmitted to the first pixels corresponding to the fifth pixel column is the green data emitting the green light.)
Re-claim 11, Okutani in view of Takasugi teaches all the limitations of claim 10 but do not explicitly teach wherein each of the plurality of pixels includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and
the control circuit is configured to control the selection circuit such that, when the image data voltage is output to a red sub-pixel, a red image data voltage is output at the first output timing and the black data voltage is output at the second output timing.
However, Lee teaches wherein each of the plurality of pixels includes a red sub-pixel, (fig. 8A and 10A; red data R11, R21, R31 and R41) a green sub-pixel, (fig. 8A and 10A; green data G12, G22, G32 and G42) and a blue sub-pixel, (fig. 8A and 10A; blue data B11, B21, B31 and B41) and
the control circuit (fig. 4; 5) is configured to control the selection circuit such that, when the image data voltage is output to a red sub-pixel, a red image data voltage is output at the first output timing (fig. 8A and 10A; red data R11, R21, R31 and R41) and the black data voltage is output at the second output timing. (fig. 8A and 10A; black data)
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of the combination with the teachings of Lee in order to image data preventing the disruptive pattern in the image display according to the image data may be provided. (par. [0206])
Re-claims 12 - 14, are rejected as applied to claims 5 - 7 above because the scope and contents of the recited limitations are substantially the same.
Re-claim 15, Okutani and Takasugi in view of Lee teaches all the limitations of claim 11, Lee teaches wherein the red sub-pixel, (fig. 9A; R11) the green sub- pixel, (fig. 9A; G12) and the blue sub-pixel (fig. 9A; B11) are commonly connected to one gate line, (fig. 9A; S1) and are respectively connected to different data lines. (fig. 9A; D1, D2 and D3)
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sosina Abebe whose telephone number is (571) 270-7929. The examiner can normally be reached on Mon-Friday from 9:00-5:30 If attempts to reach the examiner by telephone are unsuccessful, the examiner's Supervisor, Temesghen Ghebretinsae can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/S.A/Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 6/1/26B
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