DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 4, 8 – 12, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (U.S. PG Pub 2024/0282235).
Regarding Claim 1, Kim et al. teach a data driver (Figure 1, Elements 120. Paragraph 58) comprising:
an output circuit (Figure 1, Elements 122. Paragraph 58) configured to alternately output a first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) corresponding to first image data (Figures 13A and 13B, Elements +R, +G, and +B. Paragraphs 166 and 178), and a second image data voltage (Figures 13A and 13B, Element Vtarget - Vos. Paragraphs 166 and 178) corresponding to second image data (Figures 13A and 13B, Elements -R, -G, and -B. Paragraphs 166 and 178) obtained by inverting a phase (Paragraphs 166 - 170 and 178) of the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) with respect to a voltage, during one frame period (Figures 13A and 13B, Element Nth frame. Paragraphs 181 - 182); and
a control circuit (Figure 5, Element 550. Paragraph 113) configured to supply the first image data (Figures 13A and 13B, Elements +R, +G, and +B. Paragraphs 166 and 178) and the second image data (Figures 13A and 13B, Elements -R, -G, and -B. Paragraphs 166 and 178).
Regarding Claim 2, Kim et al. teach the data driver (Figure 1, Elements 120. Paragraph 58) according to claim 1 (See Above), further comprising:
a gamma voltage generation circuit (Figure 5, Element 540. Paragraph 112) configured to generate gamma voltages for each gray- level based on a high-potential gamma voltage (Figure 5, Element VGAH. Paragraph 112) and a low-potential gamma voltage (Figure 5, Element VGAL. Paragraph 112) and to supply the generated gamma voltages for each gray-level to the output circuit (Figure 1, Elements 122. Paragraph 58),
wherein the output circuit (Figure 1, Elements 122. Paragraph 58) is configured to convert the first image data (Figures 13A and 13B, Elements +R, +G, and +B. Paragraphs 166 and 178) and the second image data (Figures 13A and 13B, Elements -R, -G, and -B. Paragraphs 166 and 178) into the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) and the second image data voltage (Figures 13A and 13B, Element Vtarget - Vos. Paragraphs 166 and 178) based on the gamma voltage for each gray-level.
Regarding Claim 3, Kim et al. teach the data driver (Figure 1, Elements 120. Paragraph 58) according to claim 2 (See Above), wherein the one frame period (Figures 13A and 13B, Element Nth frame. Paragraphs 181 - 182) includes a first period (Figures 13A and 13B, Element Input1, Sub-Element H. Paragraph 179) and a second period (Figures 13A and 13B, Element Input1, Sub-Element L. Paragraph 179), and
wherein the output circuit (Figure 1, Elements 122. Paragraph 58) is configured to:
output the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) during the first period (Figures 13A and 13B, Element Input1, Sub-Element H. Paragraph 179), and
output the second image data voltage (Figures 13A and 13B, Element Vtarget - Vos. Paragraphs 166 and 178) obtained by inverting a phase (Paragraphs 166 - 170 and 178) of the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) with respect to a reference voltage (Figure 13, Element Vtarget. Paragraphs 166 and 178) during the second period (Figures 13A and 13B, Element Input1, Sub-Element L. Paragraph 179).
Regarding Claim 4, Kim et al. teach the data driver (Figure 1, Elements 120. Paragraph 58) according to claim 3 (See Above), wherein the output circuit (Figure 1, Elements 122. Paragraph 58) is configured to output the second image data voltage (Figures 13A and 13B, Element Vtarget - Vos. Paragraphs 166 and 178) obtained by inverting a phase (Paragraphs 166 - 170 and 178) of the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) at a voltage higher than the reference voltage (Figure 13, Element Vtarget. Paragraphs 166 and 178) by an offset (Figure 13, Element Vos. Paragraphs 166 and 178).
Regarding Claim 8, Kim et al. teach the data driver (Figure 1, Elements 120. Paragraph 58) according to claim 3 (See Above), wherein the control circuit (Figure 5, Element 550. Paragraph 113) is configured to set the high-potential gamma voltage (Figure 5, Element VGAH. Paragraph 112) and the low-potential gamma voltage (Figure 5, Element VGAL. Paragraph 112) to be same during the first period (Figures 13A and 13B, Element Input1, Sub-Element H. Paragraph 179) and the second period (Figures 13A and 13B, Element Input1, Sub-Element L. Paragraph 179), and
wherein the high-potential gamma voltage (Figure 5, Element VGAH. Paragraph 112) is set to be higher than the reference voltage (Figure 13, Element Vtarget. Paragraphs 166 and 178), and
the low-potential gamma voltage (Figure 5, Element VGAL. Paragraph 112) is set to be lower than the reference voltage (Figure 13, Element Vtarget. Paragraphs 166 and 178).
Regarding Claim 9, Kim et al. teach a display device comprising:
a pixel array (Figure 1, Element AA. Paragraph 54) including a plurality of data lines (Figure 1, Elements DL. Paragraph 57), a plurality of gate lines (Figure 1, Elements SL. Paragraph 57), and a plurality of pixel circuits (Figure 1, Elements SP. Paragraph 56);
a data driver (Figure 1, Elements 120. Paragraph 58) configured to output a first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) and a second image data voltage (Figures 13A and 13B, Element Vtarget - Vos. Paragraphs 166 and 178) to the plurality of data lines (Figure 1, Elements DL. Paragraph 57);
a gate driver (Figure 1, Elements 130. Paragraph 62) configured to output gate signals to the plurality of gate lines (Figure 1, Elements SL. Paragraph 57); and
a timing controller (Figure 1, Elements 140. Paragraph 64) configured to control the data driver (Figure 1, Elements 120. Paragraph 58) and the gate driver (Figure 1, Elements 130. Paragraph 62),
wherein the data driver (Figure 1, Elements 120. Paragraph 58) includes:
an output circuit (Figure 1, Elements 122. Paragraph 58) configured to output a first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) corresponding to first image data (Figures 13A and 13B, Elements +R, +G, and +B. Paragraphs 166 and 178), and a second image data voltage (Figures 13A and 13B, Element Vtarget - Vos. Paragraphs 166 and 178) corresponding to second image data (Figures 13A and 13B, Elements -R, -G, and -B. Paragraphs 166 and 178) obtained by inverting a phase (Paragraphs 166 - 170 and 178) of the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) with respect to a voltage during one frame period (Figures 13A and 13B, Element Nth frame. Paragraphs 181 - 182); and
a control circuit (Figure 5, Element 550. Paragraph 113) configured to supply the first image data (Figures 13A and 13B, Elements +R, +G, and +B. Paragraphs 166 and 178) and the second image data (Figures 13A and 13B, Elements -R, -G, and -B. Paragraphs 166 and 178).
Regarding Claim 10, Kim et al. teach the display device according to claim 9 (See Above), wherein the data driver (Figure 1, Elements 120. Paragraph 58) further includes:
a gamma voltage generation circuit (Figure 5, Element 540. Paragraph 112) configured to generate gamma voltages for each gray-level based on a high-potential gamma voltage (Figure 5, Element VGAH. Paragraph 112) and a low-potential gamma voltage (Figure 5, Element VGAL. Paragraph 112), and to supply the generated gamma voltages for each gray-level to the output circuit (Figure 1, Elements 122. Paragraph 58), and
wherein the output circuit (Figure 1, Elements 122. Paragraph 58) is configured to convert the first image data (Figures 13A and 13B, Elements +R, +G, and +B. Paragraphs 166 and 178) and the second image data (Figures 13A and 13B, Elements -R, -G, and -B. Paragraphs 166 and 178) into the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) and the second image data voltage (Figures 13A and 13B, Element Vtarget - Vos. Paragraphs 166 and 178) based on the gamma voltages for each gray-level.
Regarding Claim 11, Kim et al. teach the display device according to claim 10 (See Above), wherein the one frame period (Figures 13A and 13B, Element Nth frame. Paragraphs 181 - 182) includes a first period (Figures 13A and 13B, Element Input1, Sub-Element H. Paragraph 179) and a second period (Figures 13A and 13B, Element Input1, Sub-Element L. Paragraph 179), and
wherein the output circuit (Figure 1, Elements 122. Paragraph 58) is configured to:
output the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) during the first period (Figures 13A and 13B, Element Input1, Sub-Element H. Paragraph 179), and
output the second image data voltage (Figures 13A and 13B, Element Vtarget - Vos. Paragraphs 166 and 178) obtained by inverting a phase (Paragraphs 166 - 170 and 178) of the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) with respect to a reference voltage (Figure 13, Element Vtarget. Paragraphs 166 and 178) during the second period (Figures 13A and 13B, Element Input1, Sub-Element L. Paragraph 179).
Regarding Claim 12, Kim et al. teach the display device according to claim 11 (See Above), wherein the output circuit (Figure 1, Elements 122. Paragraph 58) is configured to output the second image data voltage (Figures 13A and 13B, Element Vtarget - Vos. Paragraphs 166 and 178) obtained by inverting a phase (Paragraphs 166 - 170 and 178) of the first image data voltage (Figures 13A and 13B, Element Vtarget + Vos. Paragraphs 166 and 178) at a voltage higher than the reference voltage (Figure 13, Element Vtarget. Paragraphs 166 and 178) by an offset (Figure 13, Element Vos. Paragraphs 166 and 178).
Regarding Claim 16, Kim et al. teach the display device according to claim 11 (See Above), wherein the control circuit (Figure 5, Element 550. Paragraph 113) is configured to set the high-potential gamma voltage (Figure 5, Element VGAH. Paragraph 112) and the low-potential gamma voltage (Figure 5, Element VGAL. Paragraph 112) to be same during the first period (Figures 13A and 13B, Element Input1, Sub-Element H. Paragraph 179) and the second period (Figures 13A and 13B, Element Input1, Sub-Element L. Paragraph 179), and
wherein the high-potential gamma voltage (Figure 5, Element VGAH. Paragraph 112) is set to be higher than the reference voltage (Figure 13, Element Vtarget. Paragraphs 166 and 178), and
the low-potential gamma voltage (Figure 5, Element VGAL. Paragraph 112) is set to be lower than the reference voltage (Figure 13, Element Vtarget. Paragraphs 166 and 178).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 – 6 and 13 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. PG Pub 2024/0282235) in view of Chen et al. (U.S. PG Pub 2020/0410950).
Regarding Claim 5, Kim et al. teach the data driver (Figure 1, Elements 120. Paragraph 58) according to claim 3 (See Above). Kim et al. is silent with regards to wherein the control circuit is configured to: set the high-potential gamma voltage and the low-potential gamma voltage as a first high-potential gamma voltage and a first low-potential gamma voltage during the first period, and set the high-potential gamma voltage and the low-potential gamma voltage as a second high-potential gamma voltage and a second low-potential gamma voltage, which are different from the first high-potential gamma voltage and the first low-potential gamma voltage, during the second period.
Chen et al. teach wherein the control circuit (Figure 1, Element 10. Paragraph 15) is configured to:
set the high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element High. Paragraphs 19 – 22) and the low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Low. Paragraphs 19 – 22) as a first high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm High. Paragraphs 19 – 22) and a first low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm Low. Paragraphs 19 – 22) during the first period (Figure 2, Element Polarity Indication Signal = 0. Paragraph 21), and
set the high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element High. Paragraphs 19 – 22) and the low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Low. Paragraphs 19 – 22) as a second high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vpm High. Paragraphs 19 – 22) and a second low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vpm Low. Paragraphs 19 – 22), which are different from the first high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm High. Paragraphs 19 – 22) and the first low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm Low. Paragraphs 19 – 22), during the second period (Figure 2, Element Polarity Indication Signal = 1. Paragraph 21).
I would have been obvious to a person of ordinary skill in the art to modify the teachings of the data driving circuit of Kim et al. with the polarity driving of Chen et al. The motivation to modify the teachings Kim et al. with the teachings of Chen et al. is to reduce the charge/discharge current to a load, as taught by Chen et al. (Paragraph 5).
Regarding Claim 6, Kim et al. in view of Chen et al. teach the data driver (Figure 1, Elements 120. Paragraph 58) according to claim 5 (See Above). Kim et al. is silent with regards to wherein the first high-potential gamma voltage and the first low-potential gamma voltage are set to be lower than the reference voltage, and the second high-potential gamma voltage and the second low-potential gamma voltage are set to be higher than the reference voltage.
Chen et al. teach wherein the first high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm High. Paragraphs 19 – 22) and the first low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm Low. Paragraphs 19 – 22) are set to be lower than (Seen in Figure 2) the reference voltage (Figure 2, Element not labeled, but in between the first and second data voltage signal. Paragraph 17), and
the second high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vpm High. Paragraphs 19 – 22) and the second low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vpm Low. Paragraphs 19 – 22) are set to be higher than (Seen in Figure 2) the reference voltage (Figure 2, Element not labeled, but in between the first and second data voltage signal. Paragraph 17).
I would have been obvious to a person of ordinary skill in the art to modify the teachings of the data driving circuit of Kim et al. with the polarity driving of Chen et al. The motivation to modify the teachings Kim et al. with the teachings of Chen et al. is to reduce the charge/discharge current to a load, as taught by Chen et al. (Paragraph 5).
Regarding Claim 13, Kim et al. teach the display device according to claim 11 (See Above). Kim et al. is silent with regards to wherein the control circuit is configured to: set the high-potential gamma voltage and the low-potential gamma voltage as a first high-potential gamma voltage and a first low-potential gamma voltage during the first period, and set them as a second high-potential gamma voltage and a second low-potential gamma voltage, which are different from the first high-potential gamma voltage and the first low-potential gamma voltage, during the second period.
Chen et al. teach wherein the control circuit (Figure 1, Element 10. Paragraph 15) is configured to:
set the high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element High. Paragraphs 19 – 22) and the low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Low. Paragraphs 19 – 22) as a first high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm High. Paragraphs 19 – 22) and a first low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm Low. Paragraphs 19 – 22) during the first period (Figure 2, Element Polarity Indication Signal = 0. Paragraph 21), and
set them as a second high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vpm High. Paragraphs 19 – 22) and a second low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vpm Low. Paragraphs 19 – 22), which are different from the first high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm High. Paragraphs 19 – 22) and the first low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm Low. Paragraphs 19 – 22), during the second period (Figure 2, Element Polarity Indication Signal = 1. Paragraph 21).
I would have been obvious to a person of ordinary skill in the art to modify the teachings of the data driving circuit of Kim et al. with the polarity driving of Chen et al. The motivation to modify the teachings Kim et al. with the teachings of Chen et al. is to reduce the charge/discharge current to a load, as taught by Chen et al. (Paragraph 5).
Regarding Claim 14, Kim et al. in view of Chen et al. teach the display device according to claim 13 (See Above). Kim et al. is silent with regards to wherein the first high-potential gamma voltage and the first low-potential gamma voltage are set to be lower than the reference voltage, and the second high-potential gamma voltage and the second low-potential gamma voltage are set to be higher than the reference voltage.
Chen et al. teach wherein the first high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm High. Paragraphs 19 – 22) and the first low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vnm Low. Paragraphs 19 – 22) are set to be lower than (Seen in Figure 2) the reference voltage (Figure 2, Element not labeled, but in between the first and second data voltage signal. Paragraph 17), and
the second high-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vpm High. Paragraphs 19 – 22) and the second low-potential gamma voltage (Figure 2, Element upper diagram, Sub-Element Vpm Low. Paragraphs 19 – 22) are set to be higher than (Seen in Figure 2) the reference voltage (Figure 2, Element not labeled, but in between the first and second data voltage signal. Paragraph 17).
I would have been obvious to a person of ordinary skill in the art to modify the teachings of the data driving circuit of Kim et al. with the polarity driving of Chen et al. The motivation to modify the teachings Kim et al. with the teachings of Chen et al. is to reduce the charge/discharge current to a load, as taught by Chen et al. (Paragraph 5).
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. PG Pub 2024/0282235) in view of Jeon et al. (U.S. PG Pub 2020/0013344).
Regarding Claim 7, Kim et al. teach the data driver (Figure 1, Elements 120. Paragraph 58) according to claim 3 (See Above). Kim et al. is silent with regards to wherein the reference voltage is applied as a first reference voltage during the first period, and is applied as a second reference voltage different from the first reference voltage during the second period.
Jeon et al. teach wherein the reference voltage (Figure 2, Element GMA_V. Paragraph 41) is applied as a first reference voltage (Figure 5, Element Vref (8V). Paragraphs 83 – 84) during the first period (Figure 5), and is applied as a second reference voltage (Figure 10, Element Vref (7V). Paragraphs 108 – 109) different from the first reference voltage (Figure 5, Element Vref (8V). Paragraphs 83 – 84) during the second period (Figure 10).
I would have been obvious to a person of ordinary skill in the art to modify the teachings of the data driving circuit of Kim et al. with the references voltage of Jeon et al. The motivation to modify the teachings Kim et al. with the teachings of Jeon et al. is to improve image quality, as taught by Jeon et al. (Paragraph 9).
Regarding Claim 15, Kim et al. teach the display device according to claim 11 (See Above). Kim et al. is silent with regards to wherein the reference voltage is applied as a first reference voltage during the first period, and is applied as a second reference voltage different from the first reference voltage during the second period.
Jeon et al. teach wherein the reference voltage (Figure 2, Element GMA_V. Paragraph 41) is applied as a first reference voltage (Figure 5, Element Vref (8V). Paragraphs 83 – 84) during the first period (Figure 5), and is applied as a second reference voltage (Figure 10, Element Vref (7V). Paragraphs 108 – 109) different from the first reference voltage (Figure 5, Element Vref (8V). Paragraphs 83 – 84) during the second period (Figure 10).
I would have been obvious to a person of ordinary skill in the art to modify the teachings of the data driving circuit of Kim et al. with the references voltage of Jeon et al. The motivation to modify the teachings Kim et al. with the teachings of Jeon et al. is to improve image quality, as taught by Jeon et al. (Paragraph 9).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Koh (U.S. PG Pub 2023/0230534) teach a display device configured to provide data voltage to the data line in different periods of the frame, similar to the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW B SCHNIREL whose telephone number is (571)270-7690. The examiner can normally be reached Monday - Friday, 10 - 6 EST.
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/A.B.S/Examiner, Art Unit 2625 /WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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