Prosecution Insights
Last updated: August 17, 2026
Application No. 19/227,353

PRE-READ ALGORITHM FOR A SEQUENTIAL READ OPERATION OF A MEMORY SYSTEM

Non-Final OA §103
Filed
Jun 03, 2025
Priority
Jun 12, 2024 — provisional 63/659,234
Examiner
KHAN, MASUD K
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
390 granted / 447 resolved
+32.2% vs TC avg
Moderate +7% lift
Without
With
+6.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
476
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
63.7%
+23.7% vs TC avg
§102
16.7%
-23.3% vs TC avg
§112
10.9%
-29.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 447 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-3, 8, 11-13, 16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHENG et al. [CN106339326A] in view of Olbrich et al. [US 8,738,841 B2] and in further view of Chow et al. [US 8,108,590 B2]. Claim 1 is rejected over ZHENG, Olbrich and Chow. ZHENG teaches “A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:” as “ In this way, the SSD can access the actual storage array of the flash memory” [Spec] “store a first command in a command queue, the first command indicating to read a first set of data from at least one of the one or more memory devices of the memory system;” as “The re-established sequential read command stream is consistent with each thread-initiated sequential read request of the host, and Sequential Read Streams 1, 2, and 3 correspond to the command streams of threads 1, 2, and 3 of the host terminal, respectively.” [Spec] “transmit, based at least in part on executing the first command, a second command to read a second set of data from at least one of the one or more memory devices;” as “then the data of the N block sizes continues to be read to the FLASH read channel to set the pre-read buffer according to the logical block address sequence of the previous read command;” [Spec] “receive, after setting the value of the flag, a third command to read the at least subset of the second set of data; and” as “in order to play the advantage of sequential read performance of the SSD, a read command reordering module is added to the SSD, a received command is reordered inside the SSD, and a corresponding read command stream group Sequential Read Stream is established according to the continuity of the access address of the read command. The re-established sequential read command stream is consistent with each thread-initiated sequential read request of the host, and Sequential Read Streams 1, 2, and 3 correspond to the command streams of threads 1, 2, and 3 of the host terminal, respectively.” [Spec] ZHENG does not explicitly teach store the second set of data in a buffer of the memory system based at least in part on receiving the second set of data, wherein the buffer comprises a plurality of portions and at least a subset of the second set of data is stored in a first portion of the plurality of portions; set a value of a flag associated with the first portion based at least in part on storing the at least subset of the second set of data in the first portion, the value of the flag indicating that the at least subset of the second set of data has been transferred to the first portion; transmit the subset of the second set of data based at least in part on the third command and the value of the flag. However, Olbrich teaches “store the second set of data in a buffer of the memory system” as “Each Flash Port includes a Flash HEMi and a Stage Buffer (e.g., Flash Port 0 304 contains Flash HEMi 0 307 and Flash Stage Buffer 0 308).” [Col 6, lines 52-55] “based at least in part on receiving the second set of data, wherein the buffer comprises a plurality of portions and” as “ In the currently preferred embodiment, each Flash Stage Buffer is a dual port SRAM that can handle one read and one write concurrently,” [Col 6, lines 63-65] “at least a subset of the second set of data is stored in a first portion of the plurality of portions;” as “wherein the second set of buffers are further configured to store data read from any subset of the buffers in the set of flash stage buffers in logical block address order.” [Claim 14] ZHENG and Olbrich are analogous arts because they teach I/O system and storage management. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of ZHENG and Olbrich before him/her, to modify the teachings of ZHENG to include the teachings of Olbrich with the motivation of it is advantageous to stripe LBAs across Flash Groups, since this maximizes the likelihood that a single transaction will address data held on more than one Flash Group, thereby allowing multiple flash reads or writes relevant to the transaction to occur simultaneously. [Olbrich, Col 19, lines 45-50] The combination of ZHENG and Olbrich does not explicitly teach set a value of a flag associated with the first portion based at least in part on storing the at least subset of the second set of data in the first portion, the value of the flag indicating that the at least subset of the second set of data has been transferred to the first portion; transmit the subset of the second set of data based at least in part on the third command and the value of the flag. However, Chow teaches “set a value of a flag associated with the first portion based at least in part on storing the at least subset of the second set of data in the first portion, the value of the flag indicating that the at least subset of the second set of data has been transferred to the first portion;” as “The data valid flag (DVF) is set when there is valid data in the AFB, but cleared when no valid data is in the AFB.” [Col 6, lines 52-54] “transmit the subset of the second set of data based at least in part on the third command and the value of the flag.” as “FIG. 9 is a flowchart of selecting an available Aggregating Flash Block (AFB) for receiving host data remaining in the page buffer when the host sends a STOP command. ” [Col 10, lines 59-61] ZHENG, Olbrich and Chow are analogous arts because they teach I/O system and storage management. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of ZHENG, Olbrich and Chow before him/her, to modify the teachings of combination of ZHENG and Olbrich to include the teachings of Chow with the motivation of the electronic data flash card has a small volume but a large storage capability, thereby resulting in convenience during data transfer; and second, because everyone has a unique fingerprint, the electronic data flash card only permits authorized persons to access the data files stored therein, thereby resulting in enhanced security. [Chow, Col 15, line 65 – Col 16, line 5] Claim 2 is rejected over ZHENG, Olbrich and Chow. ZHENG teaches “determine whether the third command corresponds to a first type of command, the first type of command comprising a sequential read command, wherein transmitting the subset of the second set of data is based at least in part on determining that the third command corresponds to the first type of command.” as “ The re-established sequential read command stream is consistent with each thread-initiated sequential read request of the host, and Sequential Read Streams 1, 2, and 3 correspond to the command streams of threads 1, 2, and 3 of the host terminal, respectively.” [Spec] Claim 3 is rejected over ZHENG, Olbrich and Chow. ZHENG teaches “determine whether the third command comprises a read command for the at least subset of the second set of data, wherein transmitting the at least subset of the second set of data is based at least in part on determining that the third command comprises the read command.” as “ The method for improving sequential read performance of a solid state disk is characterized in that a read command accessed by a logical block address accessed by a read command is grouped into a same read command stream group.” [Spec] Claim 8 is rejected over ZHENG, Olbrich and Chow. ZHENG does not explicitly teach communicate a host read data transfer module request to an interface between the memory system and a host system, wherein identifying the value of the flag is based at least in part on the host read data transfer module request. However, Olbrich teaches “communicate a host read data transfer module request to an interface between the memory system and a host system, wherein identifying the value of the flag is based at least in part on the host read data transfer module request.” as “Open Flag 3508 is set when the SuperBlock is opened for writing.” [Col 48, lines 40-41] Claim 11 is rejected over ZHENG, Olbrich and Chow under the same rationale of rejection of claim 1. Claim 12 is rejected over ZHENG, Olbrich and Chow under the same rationale of rejection of claim 2. Claim 13 is rejected over ZHENG, Olbrich and Chow under the same rationale of rejection of claim 3. Claim 17 is rejected over ZHENG, Olbrich and Chow under the same rationale of rejection of claim 8. Claim 18 is rejected over ZHENG, Olbrich and Chow under the same rationale of rejection of claim 1. Claim 19 is rejected over ZHENG, Olbrich and Chow under the same rationale of rejection of claim 2. Claim 20 is rejected over ZHENG, Olbrich and Chow under the same rationale of rejection of claim 3. Claim(s) 7, 10 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHENG et al. [CN106339326A] in view of Olbrich et al. [US 8,738,841 B2] in further view of Chow et al. [US 8,108,590 B2] and yet in further view of Parks et al. [US 2017/0301386 A1]. Claim 7 is rejected over ZHENG, Olbrich, Chow and Parks. The combination of ZHENG, Olbrich and Chow does not explicitly teach refrain from performing a read task corresponding to the third command based at least in part on determining that the third command corresponds to the at least subset of the second set of data and the value of the flag. However, Parks teaches “refrain from performing a read task corresponding to the third command based at least in part on determining that the third command corresponds to the at least subset of the second set of data and the value of the flag.” as “If the flag is set, the DRAM controller refrains from reading the DRAM and returns a value of zero.” [Abstract] ZHENG, Olbrich, Chow and Parks are analogous arts because they teach I/O system and storage management. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of ZHENG, Olbrich, Chow and Parks before him/her, to modify the teachings of combination of ZHENG, Olbrich and Chow to include the teachings of Parks with the motivation of less power may be consumed because the DRAM block need not be refreshed to maintain a zero value; [Parks, ¶0026] Claim 10 is rejected over ZHENG, Olbrich, Chow and Parks. The combination of ZHENG, Olbrich and Chow does not explicitly teach wherein each portion of the plurality of portions are configured to store 64 kilobytes of data. However, Parks teaches “wherein each portion of the plurality of portions are configured to store 64 kilobytes of data.” as “ common page sizes are 4 KB, 64 KB, 1 MB, 16 MB, 256 MB, 1 GB and 2 GB.” [¶0013] ZHENG, Olbrich, Chow and Parks are analogous arts because they teach I/O system and storage management. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of ZHENG, Olbrich, Chow and Parks before him/her, to modify the teachings of combination of ZHENG, Olbrich and Chow to include the teachings of Parks with the motivation of less power may be consumed because the DRAM block need not be refreshed to maintain a zero value; [Parks, ¶0026] Claim 16 is rejected over ZHENG, Olbrich, Chow and Parks under the same rationale of rejection of claim 7. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHENG et al. [CN106339326A] in view of Olbrich et al. [US 8,738,841 B2] in further view of Chow et al. [US 8,108,590 B2] and yet in further view of BEN-RUBI. [US 2022/0283736 A1]. Claim 9 is rejected over ZHENG, Olbrich, Chow and BEN-RUBI. The combination of ZHENG, Olbrich and Chow does not explicitly teach wherein a queue depth associated with the command queue is equal to one. However, BEN-RUBI teaches “wherein a queue depth associated with the command queue is equal to one.” as “ common page sizes are 4 KB, 64 KB, 1 MB, 16 MB, 256 MB, 1 GB and 2 GB.” [¶0013] ZHENG, Olbrich, Chow and BEN-RUBI are analogous arts because they teach I/O system and storage management. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of ZHENG, Olbrich, Chow and BEN-RUBI before him/her, to modify the teachings of combination of ZHENG, Olbrich and Chow to include the teachings of BEN-RUBI with the motivation of need in the art for an improved parallel read operation [BEN-RUBI, ¶0004] Allowable Subject Matter Claims 4 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 4 and 14 recite “determine whether the fourth command corresponds to a second type of command different from a first type of command that comprises a sequential read command; and increment a counter based at least in part on determining that the fourth command corresponds to the second type of command, wherein transmitting the at least subset of the second set of data is based at least in part on determining that the value of the counter does not satisfy a threshold.” This concept is not taught by the prior arts of record. Claims 5-6 and 15 are objected because they are dependent on claims 4 and 14 respectively and includes the same subject matters of claim 4 and 14. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MASUD K KHAN/Primary Examiner, Art Unit 2132
Read full office action

Prosecution Timeline

Jun 03, 2025
Application Filed
Jun 11, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
94%
With Interview (+6.8%)
2y 4m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 447 resolved cases by this examiner. Grant probability derived from career allowance rate.

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