DETAILED ACTION
This Action is in response to Application Number 19227474 received on 6/04/2025.
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 9 and 20 are objected to because of the following informalities:
Claim 9 recites the limitation, “the network interfaces”. It is suggested that the limitation be amended to recite “the set of network interfaces” in order to remain consistent with the preceding limitations, and remove any potential antecedent basis issues.
Claim 20 includes a period instead of a semi-colon (i.e. “; and”) before the last “wherein” limitation.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11, 13, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Holl et al. (US 12556481) in view of Rimmer et al. (US 20220351326).
Regarding claims 1, Holl disclosed a method for connecting a plurality of endpoint processing units (EPUs) that perform computations that are associated with the execution of a distributed application (Holl, Fig 1, Network 134 of GPUs; Col. 3, lines 18-30, “workloads processed by GPU clusters can comprise AI/ML model training workloads... The GPUs can be connected via a switch fabric comprising multiple switches, such that there are multiple different paths through the switch fabric, with each path comprising a different switch usage sequence.”; col. 7, lines 30-35, “The HPC service or data center 130 can be equipped with a network load balancer 132 and a network 134. The network 134 may be referred to as a back end network and can comprise a cluster of connected processors such as the GPUs 141, 142, 143 and a switch fabric 145.”), the method comprising:
configuring a plurality of forwarding elements that are part of a network to communicatively connect each particular EPU to a set of two or more other EPUs to pass the results of the particular EPU's computations to other EPUs in the set of EPUs of the particular EPU (Holl, col. 7, lines 59-67, Holl disclosed load balancer 132 balancing loads on communication paths through the switch fabric “either by instructing a GPU 141, 142, 143 to report synchronization data via one or more designated paths through the switch fabric 145, or by configuring/controlling the switch fabric 145 itself in a manner that causes the switch fabric 145 to direct synchronization data output from a GPU via one or more designated paths through the switch fabric 145” col. 8, lines 1-5, “FIG. 2 illustrates an example switch fabric 220 that can enable communications between multiple graphics processing units (GPUs) 261, 262, 263 in a cluster 260, wherein a load balancer 210 can configure traffic on paths through the switch fabric 220”; The switching fabric of Figure 2 connects each GPU to multiple other GPUs, as shown);
configuring each particular EPU to forward results of the particular EPU's computations to the particular EPU's set of other EPUs through one or more configured forwarding elements (Holl, col. 7, lines 59-67, Holl disclosed load balancer 132 balancing loads on communication paths through the switch fabric “either by instructing a GPU 141, 142, 143 to report synchronization data via one or more designated paths through the switch fabric 145; col. 12, lines 18-28, 52-67, Holl disclosed a chipset providing an interface between the GPU and the remainder of the devices, including NIC 612; See also col. 12, lines 1-18, Holl disclosed the GPUs can be configured to process jobs, resulting in synchronization data to be sent to the other GPUs. The GPUs 522, 524, 526 can send the synchronization data to the other GPUs along paths through the switch fabric 530 which are determined based on the CoS tags 513, 515, 517).
While Holl disclosed configuring GPUs (which have associated network interfaces controller 612) with respect to how to report synchronization data via one or more designated paths through the switch fabric, Holl did not explicitly disclose configuring a set of one or more network interfaces of each particular EPU.
In an analogous art, Rimmer disclosed configuring a set of one or more network interfaces of each particular EPU (Rimmer, [0023]-[0026] Rimmer disclosed control plane software stack. Control of system node NICs can be accomplished using a switching fabric 100 or a dedicated control network 102, to which as shown in Fig. 3, “control plane commands may be delivered to the control plane agents via network interface controller (NIC) 300 connected to the control plane via switching fabric 100 or control network 102 and the control plane agents may perform control plane operations to configure other NICs 302 (e.g., NICs integrated into one or more GPUs) in the platform.”).
One of ordinary skill would have been motivated to combine the teachings of Holl and Rimmer as they both provide for a switching fabric for GPU communication, and as such, they are within similar environments. Furthermore, Holl explicitly suggests the configuring of GPUs for communication across the switch fabric, and Rimmer provides specific implementation to achieve such.
Therefore it would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Rimmer within Holl in order to provide the GPUs of Holl with an integrated NIC that is configurable in order to provide for additional management and reduce latency of communications between GPUs (Rimmer, [0023]-[0024]).
Claim 16 recites a non-transitory machine readable medium storing a program that when executed by at least one processor configures a network to connect a plurality of graphics processing units (GPUs) that perform computations that are associated with the execution of a distributed application, the program comprising sets of instructions with limitations that are substantially similar to the limitations of claim 1.
Holl in view of Rimmer disclosed a non-transitory machine readable medium storing such a program (Holl, col. 14, lines 50-67).
Claim 16 is therefore rejected under the same rationale applied above.
Regarding claim 2, Holl and Rimmer disclosed the method of claim 1, wherein the EPUs are graphics processing units (GPUs) (Holl, col. 12, lines 1-5, “GPUs”; Rimmer, [0025]).
Regarding claim 3, Holl and Rimmer disclosed the method of claim 1, wherein the EPUs comprise at least one of graphics processing units (GPUs), tensor processing units (TPUs) and central processing units (CPUs) (Holl, col. 12, lines 1-5, “GPUs”).
Regarding claims 4 and 17, Holl and Rimmer disclosed the method of claim 1 and medium of claim 16, wherein each configured network interface of each EPU connects to at least one configured forwarding element through at least one physical network link (Holl, Fig. 6, Network Interface Controller 612 connecting to physical network link of Local Area Network 624; Fig. 2, Holl disclosed the GPUs are connected to switch fabric; It is evident that such connections are via their respective NICs 612 of Fig. 6; Rimmer, [0041]-[0043]).
Regarding claims 5 and 18, Holl and Rimmer disclosed the method of claim 4 and medium of claim 17, wherein the physical network links of the configured network interfaces include one of wired links, wireless links, and optical links (Rimmer, [0103]).
Regarding claims 6 and 19, Holl and Rimmer disclosed the method of claim 4 and medium of claim 17, wherein each EPU has at least one associated network interface (Holl, col. 12, lines 18-28, 52-67, Holl disclosed a chipset providing an interface between the GPU and the remainder of the devices, including NIC 612; Rimmer, [0041]-[0043]).
Regarding claim 7, Holl and Rimmer disclosed the method of claim 4, wherein each of a set of forwarding elements comprises:
a data plane circuit to pass data messages storing the computation results through the network (Holl col. 7, lines 50-55, “The workload subparts can be distributed among the GPUs 141, 142, 143, and each time a GPU completes processing of a subpart, it may report its results, in the form or synchronization data, to all of the other GPUs 141, 142, 143.“; lines 59-67, Holl disclosed “configuring/controlling the switch fabric 145 itself in a manner that causes the switch fabric 145 to direct synchronization data output from a GPU via one or more designated paths through the switch fabric 145.”; See col. 8, lines 11-25 defining the switch fabric as comprising switches/network devices; As such, the data planes of the switches/network elements of switch fabric direct messages through the paths; See also Rimmer, [0020], [0023]-[0024]); and
a control plane circuit to configure the data plane circuit and to configure at least a set of one or more network interfaces of a set of one or more EPUs (Holl col. 7, lines 59-67, Holl disclosed “configuring/controlling the switch fabric 145 itself in a manner that causes the switch fabric 145 to direct synchronization data output from a GPU via one or more designated paths through the switch fabric 145.”; Holl’s configuring of the switch fabric to handle traffic in the above particular manner requires providing the configuration data to the control plane of the switches in the switch fabric in order to configure the data plane of the switch/router; See col. 8, lines 11-25 defining the switch fabric as comprising switches/network devices; See also col. 8, lines 60-65, “The resulting path determinations can be sent from the load balancer 210 to the switch fabric 220 as configuration data, which configures the paths through the switch fabric 220 to be used by each of the different GPUs 261, 262, 263 when reporting synchronization data to the other GPUs.”; Additionally, col. 11, lines 19-23, Holl disclosed “the load balancer 210 can provide configuration data 410 to GPUs directly, and the GPUs can specify paths through the switch fabric 220 for their synchronization data outputs.”; As shown in Fig. 4, Configuration data 410 is provided via Switch Fabric 220, and therefore the control planes of the switches/network elements are utilized for configuring the GPUs as well; See also Rimmer, [0020], [0023]-[0024]).
Regarding claim 8, Holl and Rimmer disclosed the method of claim 7, wherein configuring the plurality of forwarding elements comprises providing configuration data to the control plane circuits of the forwarding elements (Holl col. 7, lines 59-67, Holl disclosed “configuring/controlling the switch fabric 145 itself in a manner that causes the switch fabric 145 to direct synchronization data output from a GPU via one or more designated paths through the switch fabric 145.”; Holl’s configuring the switch fabric to handle traffic in the above particular manner requires providing the configuration data to the control plane of the switches in the switch fabric; See col. 8, lines 11-25 defining the switch fabric as comprising switches/network devices; See also col. 8, lines 60-65, “The resulting path determinations can be sent from the load balancer 210 to the switch fabric 220 as configuration data, which configures the paths through the switch fabric 220 to be used by each of the different GPUs 261, 262, 263 when reporting synchronization data to the other GPUs.”; See also Rimmer, [0020], [0023]-[0024]).
Regarding claim 9, Holl and Rimmer disclosed the method of claim 8, wherein configuring the set of network interfaces of each particular EPU comprises providing configuration data to the control plane circuits of at least one configured forwarding element for the forwarding element to use to configure the network interfaces (Rimmer, [0024]-[0026], [0035], Rimmer disclosed managing the integrated NICs, including configuring, via the fabric and through use of the control plane agents connected via control plane of switching fabric/smartNIC).
Regarding claim 10, Holl and Rimmer disclosed the method of claim 8 further comprising a set of one or more control-plane (CP) proxy servers, configuring the set of network interfaces of each particular EPU comprises providing a first set of configuration data to the CP proxy server set to generate a second set of configuration data to configure the network interfaces (Rimmer, [0024] “In a system node, sockets stack delivers control plane commands to a control plane agent. The control plane agent accesses, by NIC driver APIs, NIC registers and firmware across the PCIe bus to perform control plane operations such as querying telemetry data, configuring port attributes, configuring quality of service (QoS), security specifications, etc. As shown in FIG. 3, control plane commands may be delivered to the control plane agents via network interface controller (NIC) 300 connected to the control plane via switching fabric 100 or control network 102 and the control plane agents may perform control plane operations to configure other NICs 302 (e.g., NICs integrated into one or more GPUs) in the platform. Control plane operations may include topology querying, switch status, and switch configuration. Control plane operations for primary network switches may be communicated via the primary network or via the control network”).
Regarding claim 11, Holl and Rimmer disclosed the method of claim 1, wherein configuring the plurality of forwarding elements comprises providing forwarding records to the forwarding elements to use to perform forwarding operations to forward data message flows storing said computation results (Holl, col. 7, lines 59-65, Holl disclosed the load balancing management device configuring/controlling the switch fabric 145 itself in a manner that causes the switch fabric 145 to direct synchronization data output from a GPU via one or more designated paths through the switch fabric ; The configuring to use particular paths amounts to providing forwarding records in order for the switches of the fabric to follow those designated paths; See also Rimmer, [0024], [0035]-[0036], Rimmer disclosed control plane operations including switch configuration).
Regarding claim 13, Holl and Rimmer disclosed the method of claim 1, wherein configuring the network interfaces comprises providing forwarding records to the network interfaces to use to perform forwarding operations to forward data message flows storing said computation results through the network (Holl, col. 7, lines 59-67, Holl disclosed, “The network load balancer 132 can be configured as described herein to balance loads on communication paths through the switch fabric 145…by instructing a GPU 141, 142, 143 to report synchronization data via one or more designated paths through the switch fabric 145”; Instructing to use one or more designated paths amount to providing forwarding records to follow in order to transmit such synchronization data through the designated paths; col. 11, lines 19-22, “the load balancer 210 can provide configuration data 410 to GPUs directly, and the GPUs can specify paths through the switch fabric 220 for their synchronization data outputs”).
Regarding claim 20, Holl and Rimmer disclosed the non-transitory machine readable medium of claim 17, wherein each of a set of forwarding elements comprises:
a data plane circuit to pass data messages storing the computation results through the network (Holl col. 7, lines 50-55, “The workload subparts can be distributed among the GPUs 141, 142, 143, and each time a GPU completes processing of a subpart, it may report its results, in the form or synchronization data, to all of the other GPUs 141, 142, 143.“; lines 59-67, Holl disclosed “configuring/controlling the switch fabric 145 itself in a manner that causes the switch fabric 145 to direct synchronization data output from a GPU via one or more designated paths through the switch fabric 145.”; See col. 8, lines 11-25 defining the switch fabric as comprising switches/network devices; The data planes of the switches/network elements of switch fabric direct messages through the paths as configured; See also Rimmer, [0020], [0023]-[0024]); and
a control plane circuit to configure the data plane circuit and to configure at least a set of one or more network interfaces of a set of one or more EPUs (Holl col. 7, lines 59-67, Holl disclosed “configuring/controlling the switch fabric 145 itself in a manner that causes the switch fabric 145 to direct synchronization data output from a GPU via one or more designated paths through the switch fabric 145.”; Holl’s configuring of the switch fabric to handle traffic in the above particular manner requires providing the configuration data to the control plane of the switches in the switch fabric in order to configure the data plane of the switch/router; See col. 8, lines 11-25 defining the switch fabric as comprising switches/network devices; See also col. 8, lines 60-65, “The resulting path determinations can be sent from the load balancer 210 to the switch fabric 220 as configuration data, which configures the paths through the switch fabric 220 to be used by each of the different GPUs 261, 262, 263 when reporting synchronization data to the other GPUs.”; Additionally, col. 11, lines 19-23, Holl disclosed “the load balancer 210 can provide configuration data 410 to GPUs directly, and the GPUs can specify paths through the switch fabric 220 for their synchronization data outputs.”; As shown in Fig. 4, Configuration data 410 is provided via Switch Fabric 220, and therefore the control planes of the switches/network elements are utilized for configuring the GPUs as well; See also Rimmer, [0020], [0023]-[0024]);
wherein the set of instructions for configuring the plurality of forwarding elements comprises a set of instructions for providing configuration data to the control plane circuits of the forwarding elements (Holl col. 7, lines 59-67, Holl disclosed “configuring/controlling the switch fabric 145 itself in a manner that causes the switch fabric 145 to direct synchronization data output from a GPU via one or more designated paths through the switch fabric 145.”; Holl’s configuring the switch fabric to handle traffic in the above particular manner requires providing the configuration data to the control plane of the switches in the switch fabric; See col. 8, lines 11-25 defining the switch fabric as comprising switches/network devices; See also col. 8, lines 60-65, “The resulting path determinations can be sent from the load balancer 210 to the switch fabric 220 as configuration data, which configures the paths through the switch fabric 220 to be used by each of the different GPUs 261, 262, 263 when reporting synchronization data to the other GPUs.”; See also Rimmer, [0020], [0023]-[0024]), wherein the set of instructions for configuring the set of network interfaces of each particular EPU comprises a set of instructions for providing configuration data to the control plane circuits of at least one configured forwarding element for the forwarding element to use to configure the network interfaces (Rimmer, [0024]-[0026], [0035], Rimmer disclosed managing the integrated NICs, including configuring, via the fabric and through use of the control plane agents connected via control plane of switching fabric/smartNIC).
Claim(s) 12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Holl et al. (US 12556481) in view of Rimmer et al. (US 20220351326) and further in view of Agrawal et al. (US 20240195749).
Regarding claim 12, Holl and Rimmer disclosed the method of claim 11, wherein the forwarding elements comprise ports (Rimmer, [0036], [0055] Rimmer disclosed fabric switch ports). Rimmer additionally disclosed configuring port attributes (Rimmer, [0024]).
Holl and Rimmer did not explicitly disclose wherein the forwarding records comprise match-action records that identify ports through which the forwarding elements should forward the data message flows.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed that configuring the switch fabric to explicitly utilize “designated paths” via the switch fabric requires such configuring to specify the particular ports to use in order to transmit the synchronization data of Holl along those designated ports.
In an analagous art, Agrawal disclosed a network interface device (Agrawal, [0017]) wherein the forwarding elements comprise ports and in which packet processors can be configured to perform match-action on received packets to identify packet processing rules and next hops (Agrawal, [0018]), to perform path selection involving selecting a particular port (Agrawal, [0019]).
One of ordinary skill in the art would have been motivated to combine the teachings of Holl and Rimmer with Agrawal, since the combined teachings of Holl and Rimmer explicitly disclosed configuring switches to use designated paths, and Agrawal provides specific implementation as to such configuring.
Therefore it would have been obvious to one of ordinary skill in the art to utilize the teachings of Agrawal in order to configure the network interface devices of Holl and Rimmer in order to alleviate issues with flow-based load balancing, removing potential issues of packet drop (Agrawal, [0003]), thereby increasing efficiency of the network.
Regarding claim 14, Holl and Rimmer disclosed the method of claim 13, including instructing a GPU 141, 142, 143 to report synchronization data via one or more designated paths through the switch fabric 145 (Holl, col. 7, lines 59-67).
Holl and Rimmer did not explicitly disclose wherein the network interfaces comprise ports, and forwarding records comprise match-action records that identify ports through which the network interfaces should forward the data message flows.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed that instructing the GPUs to utilize “designated paths” via the switch fabric requires such specifying the particular ports to use in order to transmit the synchronization data of Holl along those designated ports.
In an analagous art, Agrawal disclosed wherein the network interfaces comprise ports, and forwarding records comprise match-action records that identify ports through which the network interfaces should forward the data message flows (Agrawal, [0017]-[0020]).
One of ordinary skill in the art would have been motivated to combine the teachings of Holl and Rimmer with Agrawal, since the combined teachings of Holl and Rimmer explicitly disclosed configuring switches to use designated paths, and Agrawal provides specific implementation as to such configuring.
Therefore it would have been obvious to one of ordinary skill in the art to utilize the teachings of Agrawal in order to configure the network interface devices of Holl and Rimmer in order to alleviate issues with flow-based load balancing, removing potential issues of packet drop (Agrawal, [0003]), thereby increasing efficiency of the network.
Regarding claim 15, Holl and Rimmer disclosed the method of claim 1, including configuring the network interfaces to forward data message flows storing said computation results through the network (Holl, col. 7, lines 59-67, Holl disclosed instructing the GPUs 141, 142, 143 to report synchronization data via one or more designated paths through the switch fabric 145), but did not explicitly disclose wherein configuring the network interfaces comprises providing scheduling parameters to the network interfaces to use to identify time or rate for forwarding data message flows.
In an analogous art, Agrawal disclosed wherein configuring the network interfaces comprises providing scheduling parameters to the network interfaces to use to identify time or rate for forwarding data message flows (Agrawal, [0017]-[0020], configuring of network interface devices, including wherein such network interface devices may be configured to perform path selection within a scheduled transmit window, [0030] in which path selection may be based on bandwidth; [0058] Agrawal disclosed configuration; [0060] Agrawal disclosed path selection including selecting a port based on traversal of binary tree for scheduling packets for transmission).
One of ordinary skill in the art would have been motivated to combine the teachings of Holl and Rimmer with Agrawal, since the combined teachings of Holl and Rimmer explicitly disclosed configuring switches to use designated paths, and Agrawal provides specific implementation as to such configuring.
Therefore it would have been obvious to one of ordinary skill in the art to utilize the teachings of Agrawal in order to configure the network interface devices of Holl and Rimmer in order to alleviate issues with flow-based load balancing, removing potential issues of packet drop (Agrawal, [0003]), thereby increasing efficiency of the network.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY B DENNISON whose telephone number is (571)272-3910. The examiner can normally be reached M-F 8:30-5:50.
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/JERRY B DENNISON/Primary Examiner, Art Unit 2409
