DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 21 and 33 are objected to because of the following informalities:
In line 8 of claim 21, the word “a” should be inserted after the word “acquire”.
In line 8 of claim 33, the word “a” should be inserted after the word “acquire”. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-6, 21-22, 24, 27-28, and 30 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6, 12-15, 22, 26-27, and 31 of copending Application No. 19/226,451 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application and the reference application commonly claim as follows:
Application 19/227,598
Application 19/226,451
Claim 1
A phase interpolator circuit configured to generate a differential output
clock signal having a phase according to a first current control code and a
second current control code based on a first differential input clock signal
and a second differential input clock signal having a first phase difference
therebetween, the phase interpolator circuit comprising:
Claim 6
A phase interpolator circuit configured to generate a differential output
clock signal having a phase according to a first current control code and a
second current control code based on a first differential input clock signal
and a second differential input clock signal having a first phase difference
therebetween, the phase interpolator circuit comprising:
a first generation circuit configured to generate a first differential
intermediate current based on the first differential input clock signal
according to the first current control code;
a first generation circuit configured to generate a first differential
intermediate current based on the first differential input clock signal
according to the first current control code;
a second generation circuit configured to generate a second differential
intermediate current based on the second differential input clock signal
according to the second current control code;
a second generation circuit configured to generate a second differential
intermediate current based on the second differential input clock signal
according to the second current control code;
a synthesis circuit configured to synthesize the first differential
intermediate current and the second differential intermediate current to
generate the differential output clock signal;
a synthesis circuit configured to synthesize the first differential
intermediate current and the second differential intermediate current to
generate the differential output clock signal;
a correction circuit configured to correct a current amount of at least one
of the first differential intermediate current and the second differential
intermediate current based on a correction current generated according to a
correction code set according to at least an amount of shift of the first phase
difference from a certain value,
a correction circuit configured to correct a current amount of at least one
of the first differential intermediate current and the second differential
intermediate current based on a correction current generated according to a
correction code set according to at least an amount of shift of the first phase
difference from a certain value,
a common mode voltage correction circuit configured to correct a common
mode voltage in the output differential clock signal according to the
correction current.
Claim 12:
a common mode voltage correction circuit configured to inhibit variations
in a common mode voltage in the output differential clock signal, the
variations being caused according to the correction current.
Claim 2
the common mode voltage correction circuit is configured to inhibit
variations in the common mode voltage, the variations being caused
according to the correction current.
Claim 12:
a common mode voltage correction circuit configured to inhibit variations
in a common mode voltage in the output differential clock signal, the
variations being caused according to the correction current.
Claim 3
the common mode voltage correction circuit is configured to keep the sum
of currents flowing in the phase interpolator circuit constant regardless of the correction current.
Claim 13
the common mode voltage correction circuit is configured to keep the sum
of currents flowing in the phase interpolator circuit constant regardless of the correction current.
Claim 4
the common mode voltage correction circuit is configured to keep the sum
of currents flowing in the phase interpolator circuit constant regardless of the correction current.
Claim 14
the common mode voltage correction circuit is configured to inhibit the
variations in the common mode voltage according to the correction code.
Claim 5
the common mode voltage correction circuit is configured to keep the sum
of currents flowing in the phase interpolator circuit constant regardless of the correction current.
Claim 15
the common mode voltage correction circuit is configured to inhibit the
variations in the common mode voltage according to the correction code and
at least one of the first current control code and the second current control
code.
Claim 6
the first generation circuit includes first and fourth transistors configured
to operate as current sources, first and fourth gate voltages according to the
first current control code being supplied to gates of the first and fourth
transistors, respectively,
the second generation circuit includes second and fifth transistors
configured to operate as current sources, second and fifth gate voltages
according to the second current control code being supplied to gates of the
second and fifth transistors, respectively, and
the correction circuit includes third and sixth transistors configured to
operate as current sources, third and sixth gate voltages according to the
correction code being supplied to gates of the third and sixth transistors.
Claim 6
the first generation circuit includes first and fourth transistors configured
to operate as current sources, first and fourth gate voltages according to the
first current control code being supplied to gates of the first and fourth
transistors, respectively,
the second generation circuit includes second and fifth transistors
configured to operate as current sources, second and fifth gate voltages
according to the second current control code being supplied to gates of the
second and fifth transistors, respectively, and
the correction circuit includes third and sixth transistors configured to
operate as current sources, third and sixth gate voltages according to the
correction code being supplied to gates of the third and sixth transistors.
Claim 21
A reception circuit, comprising:
a phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween;
a comparator configured to use the differential output clock signal generated by the phase interpolator circuit and acquire data signal from a received signal; and
a demultiplexer circuit configured to convert an output signal of the comparator into a parallel signal,
wherein the phase interpolator circuit includes:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential intermediate current based on the second differential input clock signal according to the second current control code;
a synthesis circuit configured to synthesize the first differential intermediate current and the second differential intermediate o current to generate the differential output clock signal;
a correction circuit configured to correct a current amount of at least one of the first differential intermediate current and the second differential intermediate current based on a correction current generated according to a correction code set according to at least an amount of shift of the first phase difference from a certain value;
Claim 22
A reception circuit, comprising:
a phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween;
a comparator configured to use the differential output clock signal generated by the phase interpolator circuit and acquire data signal from a received signal; and
a demultiplexer circuit configured to convert an output signal of the comparator into a parallel signal,
wherein the phase interpolator circuit includes:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential intermediate current based on the second differential input clock signal according to the second current control code;
a synthesis circuit configured to synthesize the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal; and
a correction circuit configured to correct a current amount of at least one of the first differential intermediate current and the second differential intermediate current based on a correction current generated according to a correction code set according to at least an amount of shift of the first phase difference from a certain value,
a common mode voltage correction circuit configured to correct a common
mode voltage in the output differential clock signal according to the
correction current.
Claim 26:
a common mode voltage correction circuit configured to inhibit variations
in a common mode voltage in the output differential clock signal, the
variations being caused according to the correction current.
Claim 22
the common mode voltage correction circuit is configured to inhibit
variations in the common mode voltage, the variations being caused
according to the correction current.
Claim 26
a common mode voltage correction circuit configured to inhibit variations
in a common mode voltage in the output differential clock signal, the
variations being caused according to the correction current.
Claim 24
the first generation circuit includes first and fourth transistors configured
to operate as current sources, first and fourth gate voltages according to the
first current control code being supplied to gates of the first and fourth
transistors, respectively,
the second generation circuit includes second and fifth transistors
configured to operate as current sources, second and fifth gate voltages
according to the second current control code being supplied to gates of the
second and fifth transistors, respectively, and
the correction circuit includes third and sixth transistors configured to
operate as current sources, third and sixth gate voltages according to the
correction code being supplied to gates of the third and sixth transistors.
Claim 22
the first generation circuit includes first and fourth transistors configured
to operate as current sources, first and fourth gate voltages according to the
first current control code being supplied to gates of the first and fourth
transistors, respectively,
the second generation circuit includes second and fifth transistors
configured to operate as current sources, second and fifth gate voltages
according to the second current control code being supplied to gates of the
second and fifth transistors, respectively, and
the correction circuit includes third and sixth transistors configured to
operate as current sources, third and sixth gate voltages according to the correction code being supplied to gates of the third and sixth transistors.
Claim 27
A semiconductor integrated circuit, comprising:
a phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween;
a comparator configured to use the differential output clock signal generated by the phase interpolator circuit and acquire data from a received signal;
a demultiplexer circuit configured to perform a serial-parallel conversion on an output signal of the comparator to output a resultant signal, and
an internal circuit configured to receive an output signal of the demultiplexer circuit and perform a processing operation,
wherein the phase interpolator circuit includes:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential intermediate current based on the second differential input clock signal according to the second current control code;
a synthesis circuit configured to synthesize the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal;
a correction circuit configured to correct a current amount of at least one of the first differential intermediate current and the second differential intermediate current based on a correction current generated according to a correction code set according to at least an amount of shift of the first phase difference from a certain value;
Claim 27
A semiconductor integrated circuit, comprising:
a phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween;
a comparator configured to use the differential output clock signal generated by the phase interpolator circuit and acquire data from a received signal;
a demultiplexer circuit configured to perform a serial-parallel conversion
on an output signal of the comparator to output a resultant signal, and
an internal circuit configured to receive an output signal of the demultiplexer circuit and perform a processing operation,
wherein the phase interpolator circuit includes:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential intermediate current based on the second differential input clock signal according to the second current control code;
a synthesis circuit configured to synthesize the first differential
intermediate current and the second differential intermediate current to
generate the differential output clock signal; and
a correction circuit configured to correct a current amount of at least one of the first differential intermediate current and the second differential intermediate current based on a correction current generated according to a correction code set according to at least an amount of shift of the first phase difference from a certain value,
a common mode voltage correction circuit configured to correct a common
mode voltage in the output differential clock signal according to the
correction current.
Claim 31
a common mode voltage correction circuit configured to inhibit variations in a common mode voltage in the output differential clock signal, the variations being caused according to the correction current.
Claim 30
the first generation circuit includes first and fourth transistors configured to operate as current sources, first and fourth gate voltages according to the
first current control code being supplied to gates of the first and fourth transistors, respectively,
the second generation circuit includes second and fifth transistors configured to operate as current sources, second and fifth gate voltages according to the second current control code being supplied to gates of the second and fifth transistors, respectively, and
the correction circuit includes third and sixth transistors configured to operate as current sources, third and sixth gate voltages according to the correction code being supplied to gates of the third and sixth transistors.
Claim 27
the first generation circuit includes first and fourth transistors configured to operate as current sources, first and fourth gate voltages according to the
first current control code being supplied to gates of the first and fourth transistors, respectively,
the second generation circuit includes second and fifth transistors configured to operate as current sources, second and fifth gate voltages according to the second current control code being supplied to gates of the second and fifth transistors, respectively, and
the correction circuit includes third and sixth transistors configured to operate as current sources, third and sixth gate voltages according to the correction code being supplied to gates of the third and sixth transistors.
Claims 11-16, 33-36, and 39-42 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6, 12-15, 22, 26-27, and 31 of copending Application No. 19/226,458 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application and the claims of the reference application commonly claim as follows:
Application 19/227,598
Application 19/226,458
Claim 11
A phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween,
the phase interpolator circuit comprising:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential intermediate current based on the second differential input clock signal according to the second current control code and a correction code set according to at least an amount of shift of the first phase difference from a certain value;
a synthesis circuit configured to synthesize the first differential intermediate current and the second differential intermediate c current to generate the differential output clock signal; and
Claim 6
A phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween,
the phase interpolator circuit comprising:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential
intermediate current based on the second differential input clock signal according to the second current control code and a correction code set according to at least an amount of shift of the first phase difference from a certain value; and
a synthesis circuit configured to synthesize the first differential
intermediate current and the second differential intermediate current to
generate the differential output clock signal,
a common mode voltage correction circuit configured to correct a common mode voltage in the output differential clock signal according to a correction current generated according to the correction code.
Claim 12
a common mode voltage correction circuit configured to inhibit variations
in a common mode voltage in the output differential clock signal, the
variations being caused according to a correction current generated according
to the correction code.
Claim 12
the common mode voltage correction circuit is configured to inhibit variations in the common mode voltage, the variations being caused according to the correction current.
Claim 12
a common mode voltage correction circuit configured to inhibit variations
in a common mode voltage in the output differential clock signal, the variations being caused according to a correction current generated according to the correction code.
Claim 13
the common mode voltage correction circuit is configured to keep the sum
of currents flowing in the phase interpolator circuit constant regardless of the correction current.
Claim 13
the common mode voltage correction circuit is configured to keep the sum
of currents flowing in the phase interpolator circuit constant regardless of the correction current.
Claim 14
the common mode voltage correction circuit is configured to inhibit the
variations in the common mode voltage according to the correction code.
Claim 14
the common mode voltage correction circuit is configured to inhibit the
variations in the common mode voltage according to the correction code.
Claim 15
the common mode voltage correction circuit is configured to inhibit the variations in the common mode voltage according to the correction code and at least one of the first current control code and the second current control code.
Claim 15
the common mode voltage correction circuit is configured to inhibit the
variations in the common mode voltage according to the correction code and at least one of the first current control code and the second current control code.
Claim 16
the first generation circuit includes first and third transistors configured to
operate as current sources, first and third gate voltages according to the first
current control code being supplied to gates of the first and third transistors,
respectively,
the second generation circuit includes second and fourth transistors
configured to operate as current sources, second and fourth gate voltages
according to the second current control code and the correction code being
supplied to gates of the second and fourth transistors, respectively.
Claim 6
the first generation circuit includes first and third transistors configured to
operate as current sources, first and third gate voltages according to the first
current control code being supplied to gates of the first and third transistors,
respectively,
the second generation circuit includes second and fourth transistors
configured to operate as current sources, second and fourth gate voltages
according to the second current control code and the correction code being
supplied to gates of the second and fourth transistors, respectively.
Claim 33
A reception circuit, comprising:
a phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween;
a comparator configured to use the differential output clock signal generated by the phase interpolator circuit and acquire data signal from a received signal; and
a demultiplexer circuit configured to convert an output signal of the comparator into a parallel signal,
wherein the phase interpolator circuit includes:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential intermediate current based on the second differential input clock signal according to the second current control code and a correction code set according to at least an amount of shift of the first phase difference from a certain value;
a synthesis circuit configured to synthesize the first differential intermediate current and the second differential intermediate current to
generate the differential output clock signal;
Claim 22
A reception circuit, comprising:
a phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween;
a comparator configured to use the differential output clock signal generated by the phase interpolator circuit and acquire data signal from a received signal; and
a demultiplexer circuit configured to convert an output signal of the comparator into a parallel signal,
wherein the phase interpolator circuit includes:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential
intermediate current based on the second differential input clock signal according to the second current control code and a correction code set according to at least an amount of shift of the first phase difference from a certain value; and
a synthesis circuit configured to synthesize the first differential
intermediate current and the second differential intermediate current to
generate the differential output clock signal,
a common mode voltage correction circuit configured to correct a common mode voltage in the output differential clock signal according to a correction current generated according to the correction code.
Claim 26
a common mode voltage correction circuit configured to inhibit variations
in a common mode voltage in the output differential clock signal, the variations being caused according to a correction current generated according to the correction code.
Claim 34
the common mode voltage correction circuit is configured to inhibit variations in the common mode voltage, the variations being caused according to the correction current.
Claim 26
a common mode voltage correction circuit configured to inhibit variations in a common mode voltage in the output differential clock signal, the variations being caused according to a correction current generated according to the correction code.
Claim 35
the common mode voltage correction circuit is configured to inhibit the variations in the common mode voltage according to the correction code.
Claim 26
a common mode voltage correction circuit configured to inhibit variations in a common mode voltage in the output differential clock signal, the variations being caused according to a correction current generated according to the correction code.
Claim 36
the first generation circuit includes first and third transistors configured to
operate as current sources, first and third gate voltages according to the first
current control code being supplied to gates of the first and third transistors,
respectively,
the second generation circuit includes second and fourth transistors
configured to operate as current sources, second and fourth gate voltages
according to the second current control code and the correction code being
supplied to gates of the second and fourth transistors, respectively.
Claim 22
the first generation circuit includes first and third transistors configured to
operate as current sources, first and third gate voltages according to the first
current control code being supplied to gates of the first and third transistors,
respectively,
the second generation circuit includes second and fourth transistors
configured to operate as current sources, second and fourth gate voltages
according to the second current control code and the correction code being
supplied to gates of the second and fourth transistors, respectively.
Claim 39
A semiconductor integrated circuit, comprising:
a phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween;
a comparator configured to use the differential output clock signal generated by the phase interpolator circuit and acquire data from a received signal;
a demultiplexer circuit configured to perform a serial-parallel conversion on an output signal of the comparator to output a resultant signal, and an internal circuit configured to receive an output signal of the demultiplexer circuit and perform a processing operation,
wherein the phase interpolator circuit includes:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential intermediate current based on the second differential input clock signal according to the second current control code and a correction code set according to at least an amount of shift of the first phase difference from a certain value;
a synthesis circuit configured to synthesize the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal;
Claim 27
A semiconductor integrated circuit, comprising:
a phase interpolator circuit configured to generate a differential output clock signal having a phase according to a first current control code and a second current control code based on a first differential input clock signal and a second differential input clock signal having a first phase difference therebetween;
a comparator configured to use the differential output clock signal generated by the phase interpolator circuit and acquire data from a received signal;
a demultiplexer circuit configured to perform a serial-parallel conversion on an output signal of the comparator to output a resultant signal, and an internal circuit configured to receive an output signal of the demultiplexer circuit and perform a processing operation,
wherein the phase interpolator circuit includes:
a first generation circuit configured to generate a first differential intermediate current based on the first differential input clock signal according to the first current control code;
a second generation circuit configured to generate a second differential intermediate current based on the second differential input clock signal according to the second current control code and a correction code set according to at least an amount of shift of the first phase difference from a certain value; and
a synthesis circuit configured to synthesize the first differential intermediate current and the second differential intermediate current to generate the differential output clock signal,
a common mode voltage correction circuit configured to correct a common
mode voltage in the output differential clock signal according to a correction
current generated according to the correction code.
Claim 31
a common mode voltage correction circuit configured to inhibit variations in a common mode voltage in the output differential clock signal, the variations being caused according to a correction current generated according to the correction code.
Claim 40
the common mode voltage correction circuit is configured to inhibit variations in the common mode voltage, the variations being caused according to the correction current.
Claim 31
a common mode voltage correction circuit configured to inhibit variations in a common mode voltage in the output differential clock signal, the variations being caused according to a correction current generated according to the correction code.
Claim 41
the common mode voltage correction circuit is configured to inhibit the
variations in the common mode voltage according to the correction code.
Claim 31
a common mode voltage correction circuit configured to inhibit variations in a common mode voltage in the output differential clock signal, the variations being caused according to a correction current generated according to the correction code.
Claim 42
the first generation circuit includes first and third transistors configured to
operate as current sources, first and third gate voltages according to the first
current control code being supplied to gates of the first and third transistors,
respectively,
the second generation circuit includes second and fourth transistors
configured to operate as current sources, second and fourth gate voltages
according to the second current control code and the correction code being
supplied to gates of the second and fourth transistors, respectively.
Claim 27
the first generation circuit includes first and third transistors configured to
operate as current sources, first and third gate voltages according to the first
current control code being supplied to gates of the first and third transistors,
respectively,
the second generation circuit includes second and fourth transistors
configured to operate as current sources, second and fourth gate voltages
according to the second current control code and the correction code being
supplied to gates of the second and fourth transistors, respectively.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claims 7-10, 17-20, 23, 25-26, 29, 31-32, 37-38, and 43-44 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen (US 2018/0054192) discloses a phase interpolator having a correction circuit for correcting the common mode voltage of the differential output signals. Kano (US 12,355,449) is the parent application of the instant application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASSANDRA F COX whose telephone number is (571)272-1741. The examiner can normally be reached M-F 7:00-4:30; off alt Fridays.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CASSANDRA F COX/Primary Examiner, Art Unit 2836
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