DETAILED ACTION
This Final action is in response to an amendment filed 8/17/2026. Currently claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 was amended to recite “…registers configured to store, for each of a plurality of bit-planes, a respective illumination level indicator, in which the illumination level indicator for a least significant bit- plane of the plurality of bit-planes is different from the illumination level indicator for at least one other bit-plane of the plurality of bit-planes; and a controller coupled to the variable voltage source, to the registers, and to the control terminal of the transistor, the controller configured to adjust an output voltage of the variable voltage source based on a current illumination level indicator corresponding to a current bit- plane being displayed”.
The term “illumination level indicator” does not find support in the specification, the word “indicator” is not even mentioned in the specification, and the Remarks filed 8/17/2026 do not explain what is an illumination level indicator.
Dependent claims 2-10 inherit the issues of parent claim 1.
Claim 11 was amended to recite “a pulse width modulator (PWM) decoder configurable to: receive a frame sync signal indicating a start of display of a frame; and produce a control signal identifying a current bit-plane of the frame responsive to the frame sync signal; storage coupled to the PWM decoder, the storage including a look-up table configurable to store a power illumination indicator for bit-planes other than a least significant bit-plane of the frame, the look-up table further configurable to provide a high power signal or a low power signal responsive to the control signal based on whether the current bit- plane is the least significant bit-plane; and a controller coupled to the PWM decoder and to the storage, the controller configurable to produce a power output signal responsive to the high power signal or the low power signal”.
Similarly, Claim 18 was amended to recite “receiving, by a pulse width modulator (PWM) decoder, a frame sync signal indicating a start of display of a frame; producing, by the PWM decoder, a control signal identifying a current bit-plane of the frame responsive to the frame sync signal; providing, by a look-up table storing a power illumination indicator for bit-planes other than a least significant bit-plane of the frame, a high power signal or a low power signal responsive to the control signal based on whether the current bit-plane is the least significant bit-plane; and producing, by a controller, a power output signal responsive to the high power signal or the low power signal”.
The limitation “receive/receiving… a frame sync signal indicating a start of display of a frame” does not find in the disclosure and the Remarks filed 8/17/2026 do not explain any inherent support for the limitation. The specification as published par. 42 explain a “ once-per-frame SYNC signal 1010 will tell control section 1006 to restart the order in which least significant bits that use the process of FIG. 7 will be used over the frame time”, which is related to restart of the order of the least significant bits and not explicitly the start of a display frame.
The term “power illumination indicator” does not find support in the specification, the word “indicator” or the term “power illumination” are not even mentioned in the specification, and the Remarks filed 8/17/2026 do not explain what is a “power illumination indicator”.
The limitation “store a power illumination indicator for bit-planes other than a least significant bit-plane of the frame” does not find support in disclosure and the Remarks filed 8/17/2026 do not explain any inherent support.
The limitation “provide/providing… a high power or a low power signal responsive to the control signal based on whether the current bit-plane is the least significant bit-plane” does not find support in the specification. The specification does not explain any high power or low power signals.
Dependent claims 12-17 and 19-20 inherit the issues of their corresponding independent claim 11 or claim 18.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “DLPA2005 Power Management and LED/Lamp Driver IC” published by Texas Instruments in www.ti.com in September 2014 and revised in October 2015 (hereinafter DLPA2005).
Regarding claim 1, DLPA2005 disclose a circuit (DLPA2005’s pg. 12 diagram 7.2 inclusive of pg. 20 Fig. 9) comprising:
a variable voltage source (DLPA2005’s pgs. 12 and 20 diagrams 7.2 and Fig. 9: VLED buck-boost);
a light emitting diode (LED) (DLPA2005’s pg. 20 Fig. 9: LEDs shows as diodes);
an inductor coupled between the variable voltage source and the LED (DLPA2005’s Fig. pg. 12 diagram 7.2: see inductor of 2.2.µH between terminal L1 and VLED [to LED] through L2 and switch D);
a capacitor coupled to the inductor and to the LED (DLPA2005’s pgs. 12 and 20: see capacitor to VLED and LEDs);
a transistor having a current terminal and a control terminal (DLPA2005’s pgs. 12 and 20: see SW4-SW6), the current terminal coupled to the LED (DLPA2005’s pgs. 12 and 20: see top terminal to LED cathode);
registers (DLPA2005’s pgs. 27-28: section 7.5) configured to store, for each of a plurality of bit-planes (DLPA2005’s pg. 27: section 7.5: see registers for regulation current in Table 5), a respective illumination level indicator (DLPA2005’s pg. 27: section 7.5: see registers for regulation current for LSB or MSB in Table 5), in which the illumination level indicator for a least significant bit-plane of the plurality of bit-planes (DLPA2005’s pg. 27: section 7.5: see regulation current for LSB in Table 5, e.g. LED currents in pg. 30 Table 11) is different from the illumination level indicator for at least one other bit plane of the plurality of bit-planes (DLPA2005’s pg. 27: section 7.5: see regulation current for MSB in Table 5, e.g. LED currents in pg. 30 Table 11 for different hexadecimal bit planes); and
a controller (DLPA2005’s pg. 41 Fig. 17: Front-End Chip DLPC but also components such as the measurement system of DLPA2005 in pg. 21 Fig. 10) coupled to the variable voltage source (DPLA2005’s pg. 12, 41: see Front-End chip DLPC to DLPA controller which includes the VLED buck-boost), to the registers (DLPA2005’s pgs. 20, 41: see Front-End chip DLPC to DLPA controller which includes the map [of registers] in Fig. 9), and to the control terminal of the transistor (DLPA2005’s pgs. 20, 41: see Front-End chip DLPC to DLPA controller which includes the control terminal of SW4-SW6), the controller configured to adjust an output voltage of the variable voltage source (DLPA2005’s pg. 20: see Fig. 9 and pg. 15 under section 7.3.3) based on a current illumination level indicator (DLPA2005’s pg. 20: see Fig. 9 and pg. 15 under section 7.3.3: current control) corresponding to a current bit-plane being displayed (DLPA2005’s pg. 20: see Fig. 9: see SW4-SW6 controlled by bit-planes of Table 5 in pg. 27).
Regarding claim 2, DLPA2005 disclose wherein the LED is a first LED (DLPA2005 pg. 20: see top LED), the transistor is a first transistor (DLPA2005’s pg. 20: see SW4), and the current terminal is a first current terminal (DLPA2005’s pg. 20: see cathode of top LED to SW4), the circuit further comprising:
a second transistor (DLPA2005’s pg. 20: see SW5) having a first current terminal (DLPA2005’s pg. 20: see cathode of middle LED to SW5), a second current terminal (DLPA2005’s pg. 20: see SW5 terminal to RLIM), and a control terminal (DLPA2005’s pg.20: see gate of SW5), the second current terminal coupled to the second current terminal of the first transistor (DLPA2005’s pg. 20: see bottom terminal of SW4 and SW5 coupled together to RLIM) and the control terminal coupled to the controller (DLPA2005 pg. 20, 41: see SW5 gate which is part of the DLPA controller coupled to the Front-End chip DLPC in Fig. 17);
a second LED (DLPA2005 pg. 20: see middle LED) coupled between the inductor (DLPA2005 pg. 12: see inductor to L2 of VLED buck-boost) and the first current terminal of the second transistor (DLPA2005 pgs. 12, 20: see middle LED cathode to top of SW5);
a third transistor (DLPA2005’s pg. 20: see SW6) having a first current terminal (DLPA2005’s pg. 20: see cathode of bottom LED to SW6), a second current terminal (DLPA2005’s pg. 20: see SW6 terminal to RLIM), and a control terminal (DLPA2005’s pg.20: see gate of SW6), the second current terminal coupled to the second current terminal of the second transistor (DLPA2005’s pg. 20: see bottom terminal of SW5 and SW6 coupled together to RLIM) and the control terminal coupled to the controller (DLPA2005 pgs. 20, 41: see SW6 gate which is part of the DLPA controller coupled to the Front-End chip DLPC in Fig. 17); and
a third LED (DLPA2005 pg. 20: see bottom LED) coupled between the inductor (DLPA2005 pg. 12: see inductor to L2 of VLED buck-boost) and the first current terminal of the third transistor (DLPA2005 pgs. 12, 20: see middle LED cathode to top of SW6).
Regarding claim 3, DLPA2005 disclose wherein the first LED is a red LED, the second LED is a green LED, and the third LED is a blue LED (DLPA2005 pg. 15 Fig. 5).
Regarding claim 4, DLPA2005 disclose further comprising a resistor coupled between a second current terminal of the transistor and a ground terminal (DLPA2005 pg. 20: see RLIM between bottom terminal of SW4/SW5/SW6 and ground).
Regarding claim 6, DLPA2005 disclose further comprising a pulse width modulator (PWM) decoder (DLPA2005’s pg. 20: see Strobe Decoder which is a PWM decoder because the LEDs operate in PWM per pg. 23 section 7.3.10.6) coupled to the controller (DLPA2005 pg. 20: see Strobe Decoder which is part of the DLPA controller coupled to the Front-End chip in the circuit at the bottom of Fig. 1).
Regarding claim 7, DLPA2005 disclose wherein the transistor (DLPA2005’s pgs. 12 and 20: see SW4-SW6) is a field effect transistor (DLPA2005 pg. 4: SW4-SW6 are MOSFET).
Regarding claim 8, DLPA2005 disclose wherein the variable voltage source is a buck converter (DLPA2005’s pgs. 5, 20: section 7.3.3 and Fig. 9: VLED buck-boost).
Regarding claim 9, DLPA2005 disclose wherein the registers are a look-up table (DLPA2005’s pgs. 27-28: section 7.5).
Regarding claim 10, DLPA2005 disclose further comprising a spatial light modulator (SLM), wherein the LED is configurable to illuminate the SLM (DLPA2005’s pg. 38 section 8.1).
Allowable Subject Matter
No prior art was found to reject claims 5 and 11-20, however, the claims were not indicated as allowable due to the outstanding 112a rejection.
Response to Arguments
Applicant's arguments filed 8/17/2026 have been fully considered and they are partially persuasive as follows:
On the Remarks pg. 7, Applicant argues with respect to claim 1 that DLP2005 fails to disclose the added limitations, please see above rejection that has been adjusted to address the added limitations.
On the Remarks pg. 8, Applicant argues with respect to claim 11 that DLPA2005 does not disclose the added limitations. Please see the outstanding 112a rejection above.
On the Remarks pg. 8, Applicant argues with respect to claim 5 that the combination of DLPA2005 with Farris does not yield the domain comparison of claim 5 because Farris is directed to light flux magnitude feedback loop. This argument is persuasive and the prior rejection is withdrawn. See also outstanding 112a rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LILIANA CERULLO/Primary Examiner, Art Unit 2621
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