DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “DLPA2005 Power Management and LED/Lamp Driver IC” published by Texas Instruments in www.ti.com in September 2014 and revised in October 2015 (hereinafter DLPA2005).
Regarding claim 1, DLPA2005 disclose a circuit (DLPA2005’s pg. 12 diagram 7.2 inclusive of pg. 20 Fig. 9) comprising:
a variable voltage source (DLPA2005’s pgs. 12 and 20 diagrams 7.2 and Fig. 9: VLED buck-boost);
a light emitting diode (LED) (DLPA2005’s pg. 20 Fig. 9: LEDs shows as diodes);
an inductor coupled between the variable voltage source and the LED (DLPA2005’s Fig. pg. 12 diagram 7.2: see inductor of 2.2.µH between terminal L1 and VLED [to LED] through L2 and switch D);
a capacitor coupled to the inductor and to the LED (DLPA2005’s pgs. 12 and 20: see capacitor to VLED and LEDs);
a transistor having a current terminal and a control terminal (DLPA2005’s pgs. 12 and 20: see SW4-SW6), the current terminal coupled to the LED (DLPA2005’s pgs. 12 and 20: see top terminal to LED cathode);
registers (DLPA2005’s pgs. 27-28: section 7.5); and
a controller (DLPA2005’s pg. 41 Fig. 17: Front-End Chip DLPC but also components such as the measurement system of DLPA2005 in pg. 21 Fig. 10) coupled to the variable voltage source (DPLA2005’s pg. 12, 41: see Front-End chip DLPC to DLPA controller which includes the VLED buck-boost), to the registers (DLPA2005’s pgs. 20, 41: see Front-End chip DLPC to DLPA controller which includes the map [of registers] in Fig. 9), and to the control terminal of the transistor (DLPA2005’s pgs. 20, 41: see Front-End chip DLPC to DLPA controller which includes the control terminal of SW4-SW6).
Regarding claim 2, DLPA2005 disclose wherein the LED is a first LED (DLPA2005 pg. 20: see top LED), the transistor is a first transistor (DLPA2005’s pg. 20: see SW4), and the current terminal is a first current terminal (DLPA2005’s pg. 20: see cathode of top LED to SW4), the circuit further comprising:
a second transistor (DLPA2005’s pg. 20: see SW5) having a first current terminal (DLPA2005’s pg. 20: see cathode of middle LED to SW5), a second current terminal (DLPA2005’s pg. 20: see SW5 terminal to RLIM), and a control terminal (DLPA2005’s pg.20: see gate of SW5), the second current terminal coupled to the second current terminal of the first transistor (DLPA2005’s pg. 20: see bottom terminal of SW4 and SW5 coupled together to RLIM) and the control terminal coupled to the controller (DLPA2005 pg. 20, 41: see SW5 gate which is part of the DLPA controller coupled to the Front-End chip DLPC in Fig. 17);
a second LED (DLPA2005 pg. 20: see middle LED) coupled between the inductor (DLPA2005 pg. 12: see inductor to L2 of VLED buck-boost) and the first current terminal of the second transistor (DLPA2005 pgs. 12, 20: see middle LED cathode to top of SW5);
a third transistor (DLPA2005’s pg. 20: see SW6) having a first current terminal (DLPA2005’s pg. 20: see cathode of bottom LED to SW6), a second current terminal (DLPA2005’s pg. 20: see SW6 terminal to RLIM), and a control terminal (DLPA2005’s pg.20: see gate of SW6), the second current terminal coupled to the second current terminal of the second transistor (DLPA2005’s pg. 20: see bottom terminal of SW5 and SW6 coupled together to RLIM) and the control terminal coupled to the controller (DLPA2005 pgs. 20, 41: see SW6 gate which is part of the DLPA controller coupled to the Front-End chip DLPC in Fig. 17); and
a third LED (DLPA2005 pg. 20: see bottom LED) coupled between the inductor (DLPA2005 pg. 12: see inductor to L2 of VLED buck-boost) and the first current terminal of the third transistor (DLPA2005 pgs. 12, 20: see middle LED cathode to top of SW6).
Regarding claim 3, DLPA2005 disclose wherein the first LED is a red LED, the second LED is a green LED, and the third LED is a blue LED (DLPA2005 pg. 15 Fig. 5).
Regarding claim 4, DLPA2005 disclose further comprising a resistor coupled between a second current terminal of the transistor and a ground terminal (DLPA2005 pg. 20: see RLIM between bottom terminal of SW4/SW5/SW6 and ground).
Regarding claim 6, DLPA2005 disclose further comprising a pulse width modulator (PWM) decoder (DLPA2005’s pg. 20: see Strobe Decoder which is a PWM decoder because the LEDs operate in PWM per pg. 23 section 7.3.10.6) coupled to the controller (DLPA2005 pg. 20: see Strobe Decoder which is part of the DLPA controller coupled to the Front-End chip in the circuit at the bottom of Fig. 1).
Regarding claim 7, DLPA2005 disclose wherein the transistor (DLPA2005’s pgs. 12 and 20: see SW4-SW6) is a field effect transistor (DLPA2005 pg. 4: SW4-SW6 are MOSFET).
Regarding claim 8, DLPA2005 disclose wherein the variable voltage source is a buck converter (DLPA2005’s pgs. 5, 20: section 7.3.3 and Fig. 9: VLED buck-boost).
Regarding claim 9, DLPA2005 disclose wherein the registers are a look-up table (DLPA2005’s pgs. 27-28: section 7.5).
Regarding claim 10, DLPA2005 disclose further comprising a spatial light modulator (SLM), wherein the LED is configurable to illuminate the SLM (DLPA2005’s pg. 38 section 8.1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over DLPA2005.
Regarding claim 11, DLPA2005 A circuit comprising: a pulse width modulator (PWM) decoder (DLPA2005’s pg. 20: see Strobe Decoder which is a PWM decoder because the LEDs operate in PWM per pg. 23 section 7.3.10.6) configurable to: produce a control signal (DLPA2005’s pgs. 14-15 section 7.3.2: see e.g. SW4_IDAC[9:0] produced from LED_SEL in strobe decoder); a look-up table coupled to the PWM decoder (DLPA2005’s Fig. 9: see MAP to strobe decoder which are look-up tables per pgs. 27-28 section 7.5), the look-up table configurable to provide a high power signal or a low power signal (e.g. DLPA2005’s pg. 30: see Table 11 LED currents including high and low currents) responsive to the control signal (e.g. DLPA2005’s pg. 30: see Table 11: see SW4_IDAC[9:0] which is output from strobe decoder per pgs. 14-15 section 7.3.2); and a controller (DLPA2005’s pg. 41 Fig. 17: Front-End Chip DLPC but also components such as the measurement system of DLPA2005 in Fig. 10 [pg. 21] and IDAC in Fig. 9 [pg. 20]) coupled to the PWM decoder (DLPA2005 pg. 20: see Strobe Decoder which is part of the DLPA controller coupled to the Front-End chip in the circuit at the bottom of Fig. 1 and to IDAC) and to the look-up table (DLPA2005’s pgs. 20, 41: see Front-End chip DLPC to DLPA controller which includes the map [of registers] in Fig. 9, and MAP coupled to IDAC), the controller configurable to produce a power output signal (DLPA2005’s Fig. 9: signal from IDAC to VLED-Buck-Boost) responsive to the high power signal or the low power signal (DLPA2005’s Fig. 9: responsive to output from SW4_IDAC[9:0]).
DLPA2005 fails to explicitly disclose the PWM decoder receiving a sync signal, or producing a control signal responsive to the sync signal.
However, DLPA2005 does disclose timing signals for data transmission (DLPA2005’s pg. 10 section 6.6). Therefore, it would have been obvious to one of ordinary skill in the art, that the strobe decoder receives a sync signal, in order to obtain the predictable result of synchronized data transmission (DLPA2005’s pg. 10 section 6.6).
By doing such combination, DLPA2005 disclose:
A circuit comprising:
a pulse width modulator (PWM) decoder (DLPA2005’s pg. 20: see Strobe Decoder which is a PWM decoder because the LEDs operate in PWM per pg. 23 section 7.3.10.6) configurable to:
receive a sync signal (DLPA2005’s pgs. 14-15: section 7.3.2: strobe decoder upon combination receives a clock signal for data transmission per pg. 10 section 6.6); and
produce a control signal (DLPA2005’s pgs. 14-15 section 7.3.2: see e.g. SW4_IDAC[9:0] produced from LED_SEL in strobe decoder) responsive to the sync signal (DLPA2005’s pgs. 14-15: section 7.3.2: strobe decoder upon combination receives a clock signal for data transmission per pg. 10 section 6.6);
a look-up table coupled to the PWM decoder (DLPA2005’s Fig. 9: see MAP to strobe decoder which are look-up tables per pgs. 27-28 section 7.5), the look-up table configurable to provide a high power signal or a low power signal (e.g. DLPA2005’s pg. 30: see Table 11 LED currents including high and low currents) responsive to the control signal (e.g. DLPA2005’s pg. 30: see Table 11: see SW4_IDAC[9:0] which is output from strobe decoder per pgs. 14-15 section 7.3.2); and
a controller (DLPA2005’s pg. 41 Fig. 17: Front-End Chip DLPC but also components such as the measurement system of DLPA2005 in Fig. 10 [pg. 21] and IDAC in Fig. 9 [pg. 20]) coupled to the PWM decoder (DLPA2005 pg. 20: see Strobe Decoder which is part of the DLPA controller coupled to the Front-End chip in the circuit at the bottom of Fig. 1 and to IDAC) and to the look-up table (DLPA2005’s pgs. 20, 41: see Front-End chip DLPC to DLPA controller which includes the map [of registers] in Fig. 9, and MAP coupled to IDAC), the controller configurable to produce a power output signal (DLPA2005’s Fig. 9: signal from IDAC to VLED-Buck-Boost) responsive to the high power signal or the low power signal (DLPA2005’s Fig. 9: responsive to output from SW4_IDAC[9:0]).
Regarding claim 18, DLPA2005 disclose receiving, by a pulse width modulator (PWM) decoder (DLPA2005’s pg. 20: see Strobe Decoder which is a PWM decoder because the LEDs operate in PWM per pg. 23 section 7.3.10.6); producing, by the PWM decoder (DLPA2005’s pg. 20: see Strobe Decoder), a control signal (DLPA2005’s pgs. 14-15 section 7.3.2: see e.g. SW4_IDAC[9:0] produced from LED_SEL in strobe decoder); providing, by a look-up table (DLPA2005’s Fig. 9: see MAP to strobe decoder which are look-up tables per pgs. 27-28 section 7.5), the look-up table, a high power signal or a low power signal (e.g. DLPA2005’s pg. 30: see Table 11 LED currents including high and low currents) responsive to the control signal (e.g. DLPA2005’s pg. 30: see Table 11: see SW4_IDAC[9:0] which is output from strobe decoder per pgs. 14-15 section 7.3.2); and producing, by a controller (DLPA2005’s pg. 41 Fig. 17: Front-End Chip DLPC but also components such as the measurement system of DLPA2005 in Fig. 10 [pg. 21] and IDAC in Fig. 9 [pg. 20]), a power output signal (DLPA2005’s Fig. 9: signal from IDAC to VLED-Buck-Boost) responsive to the high power signal or the low power signal (DLPA2005’s Fig. 9: responsive to output from SW4_IDAC[9:0]).
DLPA2005 fails to explicitly disclose the PWM decoder receiving a sync signal, or producing a control signal responsive to the sync signal.
However, DLPA2005 does disclose timing signals for data transmission (DLPA2005’s pg. 10 section 6.6). Therefore, it would have been obvious to one of ordinary skill in the art, that the strobe decoder receives a sync signal, in order to obtain the predictable result of synchronized data transmission (DLPA2005’s pg. 10 section 6.6).
By doing such combination, DLPA2005 disclose:
A method comprising:
receiving, by a pulse width modulator (PWM) decoder (DLPA2005’s pg. 20: see Strobe Decoder which is a PWM decoder because the LEDs operate in PWM per pg. 23 section 7.3.10.6), a sync signal (DLPA2005’s pgs. 14-15: section 7.3.2: strobe decoder upon combination receives a clock signal for data transmission per pg. 10 section 6.6);
producing, by the PWM decoder (DLPA2005’s pg. 20: see Strobe Decoder), a control signal (DLPA2005’s pgs. 14-15 section 7.3.2: see e.g. SW4_IDAC[9:0] produced from LED_SEL in strobe decoder) responsive to the sync signal (DLPA2005’s pgs. 14-15: section 7.3.2: strobe decoder upon combination receives a clock signal for data transmission per pg. 10 section 6.6);
providing, by a look-up table (DLPA2005’s Fig. 9: see MAP to strobe decoder which are look-up tables per pgs. 27-28 section 7.5), the look-up table, a high power signal or a low power signal (e.g. DLPA2005’s pg. 30: see Table 11 LED currents including high and low currents) responsive to the control signal (e.g. DLPA2005’s pg. 30: see Table 11: see SW4_IDAC[9:0] which is output from strobe decoder per pgs. 14-15 section 7.3.2); and
producing, by a controller (DLPA2005’s pg. 41 Fig. 17: Front-End Chip DLPC but also components such as the measurement system of DLPA2005 in Fig. 10 [pg. 21] and IDAC in Fig. 9 [pg. 20]), a power output signal (DLPA2005’s Fig. 9: signal from IDAC to VLED-Buck-Boost) responsive to the high power signal or the low power signal (DLPA2005’s Fig. 9: responsive to output from SW4_IDAC[9:0]).
Regarding claims 12 and 19, DLPA2005 disclose wherein the low power signal is for a least significant bit plane (DLPA2005’s pg. 30 Table 11: see 0mA for LSB) and the high power signal is for bit planes other than the least significant bit plane (DLPA2005’s pg. 30 Table 11: see 0mA for LSB 0x000h and 101-2528mA for other bits 0x029h-0x3FFh).
Regarding claim 14, DLPA2005 disclose further comprising a buck converter (DLPA2005’s pgs. 12 and 20 diagrams 7.2 and Fig. 9: VLED buck-boost) coupled to the controller (DPLA2005’s pg. 12, 41: see Front-End chip DLPC to DLPA controller which includes the VLED buck-boost).
Regarding claim 15, DLPA2005 disclose further comprising:
a light emitting diode (LED) (DLPA2005’s pg. 20 Fig. 9: LEDs shows as diodes);
an inductor coupled between the buck converter and the LED (DLPA2005’s Fig. pg. 12 diagram 7.2: see inductor of 2.2.µH between terminal L1 and VLED [to LED] through L2 and switch D);
a capacitor coupled to the inductor and to the LED (DLPA2005’s pgs. 12 and 20: see capacitor to VLED and LEDs); and
a transistor (DLPA2005’s pgs. 12 and 20: see SW4-SW6) having a current terminal coupled to the LED (DLPA2005’s pgs. 12 and 20: see top terminal to LED cathode).
Regarding claim 16, DLPA2005 disclose wherein the current terminal is a first current terminal (DLPA2005’s pg. 20: see cathode of top LED to SW4), the circuit further comprising a resistor coupled between a second current terminal of the transistor and a ground terminal (DLPA2005 pg. 20: see RLIM between bottom terminal of SW4/SW5/SW6 and ground).
Regarding claim 17, DLPA2005 disclose wherein the LED is a first LED (DLPA2005 pg. 20: see top LED), the transistor is a first transistor (DLPA2005’s pg. 20: see SW4), and the current terminal is a first current terminal (DLPA2005’s pg. 20: see cathode of top LED to SW4), the circuit further comprising:
a second transistor (DLPA2005’s pg. 20: see SW5) having a first current terminal (DLPA2005’s pg. 20: see cathode of middle LED to SW5), a second current terminal (DLPA2005’s pg. 20: see SW5 terminal to RLIM), and a control terminal (DLPA2005’s pg.20: see gate of SW5), the second current terminal coupled to a second current terminal of the first transistor (DLPA2005’s pg. 20: see bottom terminal of SW4 and SW5 coupled together to RLIM) and the control terminal coupled to the controller (DLPA2005 pg. 20, 41: see SW5 gate which is part of the DLPA controller coupled to the Front-End chip DLPC in Fig. 17);
a second LED (DLPA2005 pg. 20: see middle LED) coupled between the inductor (DLPA2005 pg. 12: see inductor to L2 of VLED buck-boost) and the first current terminal of the second transistor (DLPA2005 pgs. 12, 20: see middle LED cathode to top of SW5);
a third transistor (DLPA2005’s pg. 20: see SW6) having a first current terminal (DLPA2005’s pg. 20: see cathode of bottom LED to SW6), a second current terminal (DLPA2005’s pg. 20: see SW6 terminal to RLIM), and a control terminal (DLPA2005’s pg.20: see gate of SW6), the second current terminal coupled to the second current terminal of the second transistor (DLPA2005’s pg. 20: see bottom terminal of SW5 and SW6 coupled together to RLIM) and the control terminal coupled to the controller (DLPA2005 pgs. 20, 41: see SW6 gate which is part of the DLPA controller coupled to the Front-End chip DLPC in Fig. 17); and
a third LED (DLPA2005 pg. 20: see bottom LED) coupled between the inductor (DLPA2005 pg. 12: see inductor to L2 of VLED buck-boost) and the first current terminal of the third transistor (DLPA2005 pgs. 12, 20: see middle LED cathode to top of SW6).
Claims 5, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over DLPA2005 in view of Farris et al. in US 2017/0135164 (hereinafter Farris).
Regarding claim 5, DLPA2005 disclose wherein the controller (DLPA2005’s pg. 41 Fig. 17: Front-End Chip DLPC but also components such as the measurement system of DLPA2005 in pg. 21 Fig. 10) is configurable to:
receive a signal from the second current terminal (DLPA2005’s pgs. 12, 20-21: see RLIM_K);
determine a current level indication (DLPA2005’s pg. 20: see RLIM_K and how RLIM is used for LED current accuracy in pg. 18 section 7.3.6) for the transistor (DLPA2005’s pgs. 20-21: SW4-SW6) responsive to the signal (DLPA2005’s pgs. 12, 20-21: see RLIM_K);
retrieve an intended level from the registers (DLPA2005’s Fig. 9: see MAP into strobe decoder which are the registers of pg. 27 section 7.5, these include regulation current [intended level] for SW4-SW6 which are the ILED of pg. 18 section 7.3.6); and
adjust a current level of the LED (DLPA2005’s pg. 15: the current is adjusted based on output from the strobe detector of Fig. 9 in pg. 20) based on the current level indication (DLPA2005’s pg. 18 section 7.3.6: RLIM).
DLPA2005 fails to explicitly disclose adjust a current level of the LED responsive to a comparison of the intended level to the current level indication.
However, in the same field of endeavor of LED drivers, Farris discloses adjusting the current level of an LED (Farris’s par. 35: control level of luminance of LED) responsive to a comparison of the intended level to the current level indication (Farris’s Fig. 10B and par. 39: step 1039 where the selected LED light flux magnitude set-point is compared against the sensed magnitude of the light flux).
Therefore, it would have been obvious to one of ordinary skill that DLPA2005 would include the adjusting based on the comparing (as disclosed by Farris), in order to obtain the predictable result of accurate control of the flux pulse magnitude (Farris’s par. 34), which is already an intended objective of DLPA2005’s by using the sensed LED voltage (DLPA2005’s pg. 18 section 7.3.6).
By doing such combination, DLP2005 in view of Farris disclose:
adjusting a current level of the LED (DLPA2005’s pg. 15: the current is adjusted based on output from the strobe detector of Fig. 9 in pg. 20) responsive to a comparison (DLPA2005 includes a comparing step 1039 upon combination with Farris’s Fig. 10B per par. 39) of the intended level (DLPA2005’s pg. 18 section 7.3.6: ILED equivalent to selected LED light flux magnitude set-point of Farris’s par. 39) to the current level indication (DLPA2005’s pg. 18 section 7.3.6: RLIM equivalent to sensed magnitude of the light flux output of Farris’s par. 39).
Regarding claim 13, DLPA2005 fails to explicitly disclose comparing the current level indication to a first current for the high power signal or a second current for the low power signal; and adjust the voltage level responsive to the comparison of the current level indication to the first current for the high power signal or the second current for the low power signal.
However, in the same field of endeavor of LED drivers, Farris discloses adjusting the current level of an LED (Farris’s par. 35: control level of luminance of LED) responsive to a comparison of the intended level to the current level indication (Farris’s Fig. 10B and par. 39: step 1039 where the selected LED light flux magnitude set-point is compared against the sensed magnitude of the light flux).
Therefore, it would have been obvious to one of ordinary skill that DLPA2005 would include the comparing step and the adjusting is based on the comparing step (as disclosed by Farris), in order to obtain the predictable result of accurate control of the flux pulse magnitude (Farris’s par. 34), which is already an intended objective of DLPA2005’s by using the sensed LED voltage (DLPA2005’s pg. 18 section 7.3.6).
By doing such combination, DLP2005 in view of Farris disclose:
wherein the controller (DLPA2005’s pg. 41 Fig. 17: Front-End Chip DLPC but also components such as the measurement system of DLPA2005 in Fig. 10 [pg. 21] and IDAC in Fig. 9 [pg. 20]) is further configurable to:
receive a current level indication (DLPA2005’s pg. 20: see RLIM_K and how RLIM is used for LED current accuracy in pg. 18 section 7.3.6) indicating a current at least one light source (DLPA2005’s Figs. 5, 0 and pg. 4: see RLIM_K);
compare (DLPA2005 includes a comparing step 1039 upon combination with Farris’s Fig. 10B per par. 39) the current level indication (DLPA2005’s pg. 18 section 7.3.6: RLIM equivalent to sensed magnitude of the light flux output of Farris’s par. 39) to a first current for the high power signal (DLPA2005’s pg. 18 section 7.3.6: ILED which is one of higher currents e.g. 101mA-2528mA [pg. 30 Table 11] equivalent to selected LED light flux magnitude set-point of Farris’s par. 39) or a second current for the low power signal (DLPA2005’s pg. 18 section 7.3.6: ILED which is a low current e.g. 0mA [pg. 30 Table 11] equivalent to selected LED light flux magnitude set-point of Farris’s par. 39); and
adjust a voltage level (DLPA2005’s pg. 15: the current is adjusted based on output from the strobe detector of Fig. 9 in pg. 20) responsive to the comparison (DLPA2005 includes a comparing step 1039 upon combination with Farris’s Fig. 10B per par. 39) of the current level indication (DLPA2005’s pg. 18 section 7.3.6: RLIM equivalent to sensed magnitude of the light flux output of Farris’s par. 39) to the first current for the high power signal or the second current for the low power signal (DLPA2005’s pg. 18 section 7.3.6: ILED which are higher or low currents [pg. 30 Table 11] equivalent to selected LED light flux magnitude set-point of Farris’s par. 39).
Regarding claim 20, DLPA2005 fails to explicitly disclose comparing… the current level indication to a first current for the high power signal or a second current for the low power signal; and adjusting… a voltage level responsive to the comparison of the current level indication to the first current for the high power signal or the second current for the low power signal.
However, in the same field of endeavor of LED drivers, Farris discloses adjusting the current level of an LED (Farris’s par. 35: control level of luminance of LED) responsive to a comparison of the intended level to the current level indication (Farris’s Fig. 10B and par. 39: step 1039 where the selected LED light flux magnitude set-point is compared against the sensed magnitude of the light flux).
Therefore, it would have been obvious to one of ordinary skill that DLPA2005 would include the comparing step and the adjusting is based on the comparing step (as disclosed by Farris), in order to obtain the predictable result of accurate control of the flux pulse magnitude (Farris’s par. 34), which is already an intended objective of DLPA2005’s by using the sensed LED voltage (DLPA2005’s pg. 18 section 7.3.6).
By doing such combination, DLP2005 in view of Farris disclose:
receiving, by the controller (DLPA2005’s pg. 41 Fig. 17: Front-End Chip DLPC but also components such as the measurement system of DLPA2005 in Fig. 10 [pg. 21] and IDAC in Fig. 9 [pg. 20]) a current level indication (DLPA2005’s pg. 20: see RLIM_K and how RLIM is used for LED current accuracy in pg. 18 section 7.3.6) indicating a current at least one light source (DLPA2005’s Figs. 5, 0 and pg. 4: see RLIM_K);
comparing (DLPA2005 includes a comparing step 1039 upon combination with Farris’s Fig. 10B per par. 39), by the controller (DLPA2005’s pg. 41 Fig. 17), the current level indication (DLPA2005’s pg. 18 section 7.3.6: RLIM equivalent to sensed magnitude of the light flux output of Farris’s par. 39) to a first current for the high power signal (DLPA2005’s pg. 18 section 7.3.6: ILED which is one of higher currents e.g. 101mA-2528mA [pg. 30 Table 11] equivalent to selected LED light flux magnitude set-point of Farris’s par. 39) or a second current for the low power signal (DLPA2005’s pg. 18 section 7.3.6: ILED which is a low current e.g. 0mA [pg. 30 Table 11] equivalent to selected LED light flux magnitude set-point of Farris’s par. 39); and
adjusting, by the controller (DLPA2005’s pg. 41 Fig. 17), a voltage level (DLPA2005’s pg. 15: the current is adjusted based on output from the strobe detector of Fig. 9 in pg. 20) responsive to the comparison (DLPA2005 includes a comparing step 1039 upon combination with Farris’s Fig. 10B per par. 39) of the current level indication (DLPA2005’s pg. 18 section 7.3.6: RLIM equivalent to sensed magnitude of the light flux output of Farris’s par. 39) to the first current for the high power signal or the second current for the low power signal (DLPA2005’s pg. 18 section 7.3.6: ILED which are higher or low currents [pg. 30 Table 11] equivalent to selected LED light flux magnitude set-point of Farris’s par. 39).
Conclusion
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/LILIANA CERULLO/Primary Examiner, Art Unit 2621