DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 08/13/2026 have been fully considered but they are not persuasive.
Applicant argues that the cited references fail to teach, disclose or suggest all limitations of claims 21, 29, and 37. Applicant distinguishes a block sample mean from an average pixel
difference between two blocks. However, the rejection relies on Chen's disclosure of
bilateral matching between two prediction blocks, Pred L0 and Pred L1, using MRSAD (See Chen, Section 1). As explained by Mironovich et al. (US 2013/0329800 A1, paragraphs [0089]-[0090] and Equation 4), MRSAD removes the difference between the mean values of the two compared blocks from their corresponding pixel differences. Mathematically, the difference between the two block means is equivalent to the average of the corresponding pixel differences.
Chen further discloses that the mean value used for MRSAD is determined at the center of the search area, corresponding to refinement motion vector (0,0), and shared across the other search positions (Section 2.1). Thus, the center of the search area identifies where the mean is determined, rather than establishing that the mean is unrelated to the differences between the two candidate blocks.
Accordingly, Applicant's distinction between a block mean and an average pixel difference does not overcome the rejection. The rejections under 35 U.S.C. §§ 102 and 103 are maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-24 and 27-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (“Non-CE9.2.1.e: Non-local-mean-based MRSAD and Row-subsampled Search Pattern for DMVR,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 13th Meeting: Marrakech, MA, 9–18 Jan. 2019, Document: JVET-M0516-v3), hereinafter referred to as “Chen.”
Regarding claim 21, Chen discloses method for decoding a picture, the method comprising:
determining an average pixel difference between two candidate video blocks associated with a current video block (See Sec. 2 disclosing that “this contribution takes the mean value from the samples at the center of the search area,” wherein the mean value corresponds to the average pixel difference between the two candidate video blocks associated with the current coding unit)
calculating, based on the average pixel difference, a mean removed sum of absolute differences (MRSAD) value for a first pixel position associated with a motion vector refinement search for the current video block (See Sec 2 disclosing that “this mean value is identical to the one computed when DMVR performs bilateral matching with a refinement motion vector equal to (0, 0),” wherein the average pixel difference at the center or initial position is used to compute the MRSAD at the first pixel position of the motion vector refinement search)
calculating, based on the same average pixel difference, respective MRSAD values for one or more other pixel positions associated with the motion vector refinement search for the current video block (See Sec. 2 disclosing “this mean value is shared over all local blocks on the search area during bilateral matching,” wherein a single average pixel difference, derived at the initial search position, is shared across all remaining candidate positions without independent per position derivation); and
performing the motion vector refinement search for the current video block based on the respective MRSAD values calculated for the first pixel position and the one or more other pixel positions (See Sec. 1 disclosing “[t]he cost function used in the matching process is row-subsampled MRSAD,” and that the minimum MRSAD cost position across all candidates position is selected as the refined motion vector).
Regarding claim 22, Chen discloses all the limitations of claim 21, and is analyzed as previously discussed with respect to that claim.
Furthermore, Chen discloses the method of claim 21, wherein calculating the MRSAD value for the first pixel position based on the average pixel difference comprises subtracting the average pixel difference from one or more pixel differences between the two candidate video blocks before summing up the one or more pixel differences (See Sec. 2 disclosing MRSAD using a shared mean value and per-sample mean-removed difference, which includes subtracting the average difference from per-pixel difference before accumulating absolute values, as evidenced by Mironovich et al. in US20130329800, ¶¶[0089] and [0090] and Eq. 4).
Regarding claim 23, Chen discloses all the limitations of claim 21, and is analyzed as previously discussed with respect to that claim.
Furthermore, Chen discloses the method of claim 21, further comprising decoding the current video block based on a motion vector derived from the motion vector refinement search (See Sec. 1 disclosing “[a]fter the matching process is done, the refined MVs are used for motion compensation in the prediction stage,” wherein the current video block is decoded based on the motion vectors derived from the refinement search).
Regarding claim 24, Chen discloses all the limitations of claim 23, and is analyzed as previously discussed with respect to that claim.
Furthermore, Chen discloses the method of claim 23, wherein the motion vector refinement search is performed as part of a decoder side motion vector refinement (DMVR) process. (See Sec. 1 disclosing that “Decoder-side Motion Vector Refinement (DMVR) is a bi-prediction technique for Merge blocks with two initially signalled motion vectors (MV) that can be further refined by using bilateral matching prediction” ).
Regarding claim 27, Chen discloses all the limitations of claim 21, and is analyzed as previously discussed with respect to that claim.
Furthermore, Chen discloses the method of claim 21, wherein the two candidate video blocks are luma video blocks (See Sec. 2 disclosing that “only the samples with even row indices (i.e. 0, ±2, ±4, …) on the search area are involved in the process of motion vector refinement,” wherein the bilateral matching is performed on luma samples consistent with Chen’s simulation tables reporting Y coding results).
Regarding claim 28, Chen discloses all the limitations of claim 21, and is analyzed as previously discussed with respect to that claim.
Furthermore, Chen discloses the method of claim 21, wherein the two candidate video blocks are of the same size (See Sec. 1 disclosing bilateral matching between prediction coding blocks in the two reference pictures during DMVR, wherein the compared prediction blocks corresponding to the current coding unit).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Abe et al. (“CE4-related: Low pipeline latency LIC " Joint Video Exploration Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 12th Meeting: Macao, CN, 03–12 Oct. 2018 Document: JVET-L0120-v2), hereinafter referred to as Abe.
Regarding claim 25, Chen discloses Chen discloses all the limitations of claim 25, and is analyzed as previously discussed with respect to that claim.
Chen does not explicitly disclose method of claim 24, further comprising applying local illumination compensation (LIC) to the current video block during the decoding of the current video block.
However, Abe from the same or similar endeavor of video compression discloses method of claim 24, further comprising applying local illumination compensation (LIC) to the current video block during the decoding of the current video block (See Abstract and Secs. 2 and 3 disclosing that “LIC process is implemented in the reconstruction stage” and that the proposed method “apply LIC process after DMVR refined MC, ” thereby applying LIC during decoding of the current block).
It would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings disclosed by Chen to add the teachings of Abe as above, in order to allow to apply LIC with DMVR while reducing the LIC pipeline latency issue (Abe, Secs. 2 and 5).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Abe, and further, in view of Bordes (“CE4-related: LIC with reduced memory buffer,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 12th Meeting: Macao, CN, 3–12 Oct. 2018 Document: JVET-L0203-v3 ), hereinafter referred to as Bordes
Regarding claim 26, Chen and Abe disclose all the limitations of claim 25, and is analyzed as previously discussed with respect to that claim.
Chen does not explicitly disclose the method of claim 25, further comprising determining one or more parameters associated with the LIC before or in parallel with the DMVR process.
However, Bordes from the same or similar endeavor of video coding discloses the method of claim 25, further comprising determining one or more parameters associated with the LIC before or in parallel with the DMVR process (See Sec. 2 disclosing that “ at the end of processing of each CU, LIC parameters are computed on bottom and right borders, for each colour component, and stored in a common LIC buffer. At the beginning of CU processing, LIC parameters are accessed in common LIC buffer corresponding to neighboring top and left”).
It would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings disclosed by Chen and Abe to add the teachings of Bordes as above, in order to reduce memory bandwidth induced by the access to additional reference frame pixels and neighbouring reconstructed pixels (Bordes, Sec. 5).
Claim 29-32 and 35-39 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Chen et al. (US20200169748A1), hereinafter referred to as Chen748.
Regarding claims 29-32, 35 and 36, these claims are rejected based on the same art and evidentiary limitations applied to the method of claims 21-24 and 27-28, since they claim analogous subject matter in the form of a device for performing the same or equivalent functionality.
Chen does not explicitly disclose a video decoding device, comprising: a processor configured perform the recited limitations.
However, Chen748from the same or similar endeavor of video coding discloses a video decoding device, comprising: a processor configured perform the recited limitations (See ¶[0090]).
It would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings disclosed by Chen to add the teachings of Chen748 as above, in order to implement a video encoder and video decoder each as any of a variety of suitable encoder and/or decoder circuitry, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware or any combinations thereof. When the techniques are implemented partially in software, a device may store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure (Chen748, ¶[0090]).
Regarding claims 37-39, these claims are rejected based on the same art and evidentiary limitations applied to the method of claims 21-23, since they claim analogous subject matter in the form of a device for performing the same or equivalent functionality.
Chen does not explicitly disclose a video encoding device, comprising: a processor configured perform the recited limitations.
However, Chen748 from the same or similar endeavor of video coding discloses a video encoding device, comprising: a processor configured perform the recited limitations (See ¶[0090]).
The Examiner notes that it is well-known in the art that video compression involves a complementary pair of systems: an encoder and a decoder. The encoder converts the source data into a compressed form, occupying a reduced number of bits prior to transmission or storage, while the decoder converts the compressed form back into a representation of the original video data by performing a reciprocal process to that of the encoder, decoding the encoded video data from the bitstream.
It would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings disclosed by Chen to add the teachings of Chen748 as above, in order to implement a video encoder and video decoder each as any of a variety of suitable encoder and/or decoder circuitry, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware or any combinations thereof. When the techniques are implemented partially in software, a device may store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure (Chen748, ¶[0090]).
Claim 33 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Abe and Chen748.
Regarding claim 33, Chen and Abel disclose all the limitations of claim 32, and is analyzed as previously discussed with respect to that claim.
Regarding claim 33, this claim is rejected based on the same art and evidentiary limitations applied to the method of claim 25, since it claims analogous subject matter in the form of device a for performing the same or equivalent functionality.
Further, this claim is rejected based on the same art and evidentiary limitations applied to the method of claim 25, since it claims analogous subject matter in the form of device a for performing the same or equivalent functionality.
Regarding claim 40, Chen and Abel disclose all the limitations of claim 39, and is analyzed as previously discussed with respect to that claim.
Further, this claim is rejected based on the same art and evidentiary limitations applied to the method of claim 25, since it claims analogous subject matter in the form of device a for performing the same or equivalent functionality.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Abe, and Bordes and further, in view of Chen748.
Regarding claim 34, this claim is rejected based on the same art and evidentiary limitations applied to the method of claim 26, since it claims analogous subject matter in the form of device a for performing the same or equivalent functionality.
Further, this claim is rejected based on the same art and evidentiary limitations applied to the method of claim 25, since it claims analogous subject matter in the form of device a for performing the same or equivalent functionality.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FABIO S LIMA whose telephone number is (571)270-0625. The examiner can normally be reached on Monday - Friday 8 am - 4 pm.
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/FABIO S LIMA/Primary Examiner, Art Unit 2486
