Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
The IDS, filed 6/4/25, has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-9, and 11-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Siau al (US20240393952, “Siau”).
As to claim 1:
Siau teaches data storage system (memory system 110; Fig. 1, 0026) comprising:
a plurality of storage areas, including a first storage area and a second storage area, for storing data (memory device having one or more memory dies, each having one or more planes; Fig. 1, 0014, 0017);
a memory device including a first channel and a second channel for communication (memory device coupled to a local media controller by one or more communication channels; Fig. 1, 3; 0015, 0022); and
a controller for transmitting an operation command to the memory device through at least one of the first channel and the second channel (memory sub-system controller 115 communicate with memory devices 130 to perform memory access operations (ex: Read, Write, Erase); 0037-0038; access to memory device is through one or more communication channels; 0015-0016, 0022), and for controlling an operation for the first storage area through the first channel during a first time period and controlling an operation for the second storage area through the second channel during a portion of the first time period (multiplexer enable multiple I/O interface to selective access the memory planes to enable access to a target; 0062, 0068; access to a plane is possible through 1 of 2 channels; Fig. 3; 0058-0061; memory access can be concurrent (within same time period) with respect to planes of independent plane groups; 0022, 0060, 0074, 0075).
As to claim 2:
Siau teaches the controller transmits an occupation request command for the first storage area to the memory device through at least one of the first channel and the second channel, checks an occupation status information of the first storage area, and controls a timing of transmitting the operation command for the first storage area based on the occupation status information of the first storage area (each memory device include status information; 0049-0050, 0053; check memory device to determine if memory device is busy with a memory operation, and control the memory operation based on the busy status; 0075, 0061).
As to claim 7:
Siau teaches the occupation status information of the first storage area is a second value, and wherein the first storage area performs an operation according to an operation command received through the second channel (controller 335 may determine that I/O interface 1 is busy (e.g., there is an on-going write command being executed on plane 0 of plane group 1 using I/O interface 1). In response to this determination, the controller 335 can transmit a command to I/O interface 2 via channel 2 to execute the read command with respect to plane 2; 0061, 0075).
As to claim 8:
Siau teaches wherein the memory device comprises: a first memory device including the first channel and the second channel and communicating with the controller through the first channel (plane group 1 accessible through channel 1; Fig. 3; 0058-0061); and a second memory device including the first channel and the second channel, and communicating with the controller through the second channel (plane group 2 accessible through channel 2; Fig. 3; 0058-0061).
As to claim 9:
Siau teaches the sum of the number of channels included in the first memory device and the number of channels included in the second memory device is greater than the number of channels included in the controller (the number of channels in controller is less than the number of memory planes; in one embodiment, only 1 channel is used for multiple memory planes; Fig. 4; 0017-0018; 0022-0025; 0066-0069).
As to claim 11:
Siau teaches the controller transmits the occupation request command before transmitting the operation command to the first memory device and the second memory device (check busy state before execute memory access operation; 0061, 0075).
As to claim 12:
Siau teaches the controller comprises: a first controller that communicates with the memory device through the first channel and accesses the plurality of storage areas; and a second controller that communicates with the memory device through the second channel and accesses the plurality of storage areas during a time period other than a time period during which the first controller accesses the plurality of storage areas (multiple media controllers access memory through different channels; Fig. 1; 0042-0044).
As to claim 13:
Siau teaches the first controller transmits a write command for the first storage area to the memory device during a first period (media controllers can perform memory access operation independently and at different time period; write operation; 0017, 0031, 0053, 0061), and wherein the second controller transmits a read command for the first storage area to the memory device during a second period subsequent to the first period (read operation; 0015, 0017,0022, 0031, 0037).
As to claim 14:
Siau teaches the first controller transmits an occupation request command for the first storage area to the memory device before transmitting the write command, and wherein the second controller transmits an occupation request command for the first storage area to the memory device before transmitting the read command (each memory device include status information; 0049-0050, 0053; check memory device to determine if memory device is busy with a memory operation, then control the read/write memory operation based on the busy status; 0075, 0061).
As to claim 15:
Siau teaches a memory device (memory system 110; Fig. 1, 0026) comprising:
a plurality of storage areas (memory device having one or more memory dies, each having one or more planes; Fig. 1, 0014, 0017); and
a switching unit that controls connection between each of the plurality of storage areas and N (an integer where N≥2) channels (multiplexer enable multiple I/O interface to selective access the memory planes to enable access to a target; 0062, 0068; access to a plane is possible through 1 of 2 channels; Fig. 3; 0058-0061), wherein the memory device receives an operation command for a first storage area through a first channel, from among the N channels, and wherein the memory device receives an operation command (controller sends memory access commands; 0037; communication to memory through channels; 0015-0016, 0022) for a second storage area different from the first storage area through a second channel during at least a portion of a period during which an operation for the first storage area is performed (memory access can be concurrent (within same time period) with respect to planes of independent plane groups; 0022, 0060, 0074, 0075).
As to claim 16:
Siau teaches the memory device sets an occupation status information of the first storage area to a first value according to an occupation request command for the first storage area received through the first channel, and wherein the memory device receives the operation command for the first storage area through the first channel (access command can be sent through a channel; 0015-0016, 0022; each memory device include status information; 0049-0050, 0053, if busy, memory indicates busy status; 0061, 0075).
As to claim 17:
Siau teaches the memory device receives the occupation request command for the first storage area through the second channel while an operation according to the operation command is performed for the first storage area, and wherein the occupation status information of the first storage area is maintained at the first value (each memory device include status information; 0049-0050, 0053, if busy, memory indicates busy status; 0061, 0075; receive commands while memory has busy status with on-going operation; 0061, 0075).
As to claim 18.:
Siau teaches the memory device receives an occupation request command for the first storage area through the second channel after the operation according to the operation command for the first storage area is terminated, wherein the occupation status information of the first storage area is changed to a second value, and wherein the operation command for the first storage area is received through the second channel after the occupation status information of the first storage area is changed to the second value (receive commands for operations through channels; 0040, 0043; when memory is not busy with other on-going operation, it can process the requested command for operation; 0061, 0075), 0017, 0042).
As to claim 19:
Siau teaches a controller (memory sub-system controller 115 (Fig. 1,3; 0040); comprising: an interface unit (I/O interfaces; 0049-0051; Fig. 2-3) that communicates with a memory device through a first channel and a second channel (channels 1-2 coupled to memory planes; Fig. 3-4; 0015-0016, 0022; multiplexer select access plane to communicate with channel; Fig. 3; 0062, 0068); and a control logic that transmits an occupation request command for a target storage area through the first channel (controller sends requests to memory interface and sends commands to memory device; 0043), checks an occupation status information of the target storage area (each memory device include status information; 0049-0050, 0053), and transmits an operation command for the target storage area through the first channel if the occupation status information of the target storage area is a first value (check memory device to determine if memory device is busy with a memory operation, then control the memory operation based on the busy status; 0075, 0061).
Allowable Subject Matter
Claims 3-6, 10, and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 3, the prior art does not further suggest the invention of claim 2, wherein, when the occupation request command is transmitted through the first channel, the controller transmits the operation command for the first storage area at a first time period if the occupation status information of the first storage area is a first value, and transmits the operation command for the first storage area at a second time period later than the first time period if the occupation status information of the first storage area is a value other than the first value.
Claims 4-5 are also allowable for incorporating the limitation of claim 3, and further limitations.
As to claim 6, the prior art does not further suggest the system of claim 2, wherein the controller transmits a command requesting confirmation of the occupation status information of the first storage area to the memory device after transmitting the occupation request command for the first storage area.
As to claim 10, the prior art does not further suggest the invention of claim 8, wherein the occupation status information of all of the plurality of storage areas included in the first memory device is set to a first value, and wherein the occupation status information of all of the plurality of storage areas included in the second memory device is set to a second value.
As to claim 20, the prior art does not further suggest the controller according to claim 19 wherein the control logic transmits the operation command at a first time period when the occupation status information of the target storage area is a first value, and transmits the operation command at a second time period after the first time period when the occupation status information of the target storage area is a second value.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20240069738 discloses accessing memory devices via switchable channels. It includes multiple controller channels, multiple memory channels, and programming mapping between them. Data is routed from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.
US20180322054 discloses a multiple data channel memory architecture system having a plurality of memories, plural independent data channels, each coupled to one of the memories, and control logic configured to selectively control the channels to access the memory.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
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