Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to application filed on 6/4/2025, claims 1-20 are pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/23/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
the following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8, 11 and 15-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kao et al., US 2024/0211014 A1.
Regarding claims 1, 15 and 18, Kao teaches a device, comprising:
a memory device configured to store data for a task comprising a first set of operations being performed at a first time period and a second set of operations being performed at a second time period (Fig.1 and Fig.3 and section 0056-0058; Processor cores 110A-N and GPU 140 are configured to execute instructions of one or more instruction set architectures (ISAs), which can include operating system instructions and user application instructions. These instructions include memory access instructions which can be translated and/or decoded into memory access requests or memory access operations targeting memory 160);
a computation engine (Fig.2; compute unit 205) coupled to the memory device (Fig.1; memory 160) and configured to perform operations of the task comprising the first set of operations and the second set of operations (Fig.1-Fig.2; section 0031-0032; in response to detecting the condition, control unit 240 evaluates a variety of parameters including one or more of the currently running task(s), types of tasks, phases of given tasks, and so on); and
a controller (memory controller 225 in the Fig.2) coupled to the memory device and the computation engine and configured to:
determine a first efficiency control metric of the first set of operations or a second efficiency control metric of the second set of operations based on one or more operational parameters of the memory device or the computation engine measured in the first time period or the second time period, respectively (section 0036; when the set of tasks comprises rendering of multiple frames, the recording unit 202 determines a need for recording parameters for a frame when the length of the frame (e.g., the amount of time it takes to render the frame, or the number of clock cycles to render the frame) exceeds that of a previously rendered frame. Further, the recording unit 202 triggers recording of the one or more parameters in response to detecting a recording condition, including but not limiting to, two or more consecutive frames taking a same (or similar) amount of time to render, two or more consecutive frames determined to have a same or similar average frequency used during rendering, rendering of two or more consecutive frames having a same or similar starting frequency, and the like);
determine, based on the first efficiency control metric or the second efficiency control metric, that the first set of operations is associated with a computation bound phase of the task and the second set of operations is associated with a memory bound phase of the task (section 0048; the system management unit 210 uses device preferences 308 to determine whether a given task is compute-bound or memory-bound. Further, the system management unit 210 ascertains the power state of a computing unit for executing the given task 312 from proposed power states 318. Based on the information on whether the task 312 is compute or memory bound, and the power state of the computing unit, the power allocation unit 215 allocates power for consumption by the computing unit, from the power budget, for executing the task 312); and determine a first operating point and a second operating point of the computation engine, wherein the computation engine is configured to perform the first set of operations under the first operating point during the first time period and perform the second set of operations under the second operating point during the second time period (claim 1; record one or more first operating frequencies of a computing unit while executing a first task; and execute a second task with one or more second operating frequencies, wherein the one or more second operating frequencies are selected for executing the second task based at least in part on the one or more first operating frequencies; section 0068; recorded operating frequencies can serve as reference operating points to determine operating frequencies for execution of a given task. For example, as described in the foregoing, operating frequencies can be identified and recorded during rendering of frames and subsequently used to set operating frequencies for rendering subsequent frames).
For claim 18, Kao further teaches the computation engine comprises a communication fabric, one or more memory controllers configured to control the memory device, a local memory, and a plurality of neural engine circuits configured to perform the operations of the task (Fig.2).
Regarding claims 2 and 16, Kao teaches the computation engine is further configured to: consume a first power in response to being operated under the first operating point to perform the first set of operations of the computation bound phase; and consume a second power in response to being operated under the second operating point to perform the second set of operations of the memory bound phase, wherein the first power is larger than the second power (section 0048; the system management unit 210 uses device preferences 308 to determine whether a given task is compute-bound or memory-bound. Further, the system management unit 210 ascertains the power state of a computing unit for executing the given task 312 from proposed power states 318. Based on the information on whether the task 312 is compute or memory bound, and the power state of the computing unit, the power allocation unit 215 allocates power for consumption by the computing unit, from the power budget, for executing the task 312).
Regarding claims 3 and 17, Kao teaches the computation engine comprises a communication fabric, a memory controller, a local memory, and a plurality of neural engine circuits configured to perform the operations of the task, and wherein the data stored in the memory device comprises input data and kernel data comprising a plurality of weights (Fig.2).
Regarding claim 4, Kao teaches the controller is further configured to periodically determine an efficiency control metric of a set of operations of the task, and wherein the first time period is equal to the second time period (section 0047; The task scheduler 302 also attempts to schedule tasks to keep the sum of the execution time of a given task plus the wait time of the given task less than or equal to the time indicated by the QoS setting of the given task).
Regarding claim 8, Kao teaches the controller is further configured to determine the first operating point and the second operating point of the computation engine based on one or more hardware limit parameters for the computation engine (section 0044-0045; The operating frequencies are then recorded and can serve as reference operating point(s) for the system management unit 210 to determine operating frequencies for execution of other subsequent tasks. taking the example of rendering of frames as described above, the stable state is deemed to be reached when respective operating frequencies at the beginning of rendering of two consecutive frames is the same. The operating frequency for the second frame is then stored as the reference operating point).
Regarding claim 11, Kao teaches the controller is further configured to determine the first operating point of the computation engine indicated by a target performance adjustment generated by a compiler based on a task performance model comprising a plurality of tasks previously performed by the computation engine (section 0065-0066; the power management unit then determines, based at least in part on the power budget, whether excess power is available to boost the operating frequencies (conditional block 606). In an implementation, the available power is either accumulated or consumed as a power credit, e.g., when operating parameters of a processing system are adjusted by the power management unit in order to save power; the power management unit is configured to operate in two modes of operation, wherein in the first mode of operation, the power management unit determines operating parameters for execution of a task based on available power (e.g., the power management mode). In the second mode of operation, the power management unit adjusts the operating parameters for a given task based at least in part on recording data available for other tasks relatively similar to the given task).
Allowable Subject Matter
Claims 5-7, 9-10, 12-14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The limitations not found in the prior art of record include the task comprises a third set of operations being performed at a third time period, and the controller is further configured to: determine the third set of operations is associated with the computation bound phase or with the memory bound phase based on a predetermined memory bandwidth threshold and a system memory bandwidth indicator, wherein the system memory bandwidth indicator is based on a ratio of a memory bandwidth used to receive data stored in the memory device for the third set of operations to a link bandwidth capacity between the computation engine and the memory device in combination with the other claimed limitations as described in the claims 5 and 19 (claims 6-7 are depended on claim 5).
The limitations not found in the prior art of record include the controller is further configured to determine the first efficiency control metric of the first set of operations based on an arithmetic intensity indicating a number of operations performed by the computation engine during the first time period for the first set of operations, a stall frequency indicating a number of stalls for the computation engine to wait for data comprising input data and kernel data from the memory device during the first time period for the first set of operations, a system memory bandwidth indicator during the first time period for the first set of operations, or a number of memory read count during the first time period to read data for the task from the memory device configured to store the data for the task in combination with the other claimed limitations as described in the claims 9 and 20 (claim 10 is depended on claim 9).
The limitations not found in the prior art of record include the target performance adjustment is generated based on a first estimate of a total time for performing the first set of operations by the computation engine, a second estimate of a total time for accessing a local memory within the computation engine for performing the first set of operations, a third estimate of a total time for accessing the memory device for performing the first set of operations, and a fourth estimate of a total execution time of the first set of operations, wherein the first estimate, the second estimate, the third estimate, and the fourth estimate are determined based on the task performance model in combination with the other claimed limitations as described in the claim 12 (claims 13-14 are depended on claim 12).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Banik et al., US 2022/0012062 A1 teaches Methods, apparatus, systems, and articles of manufacture to increase boot performance are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: during a boot process: identify a boot task that is to be performed during the boot process; execute the boot task using a first processor component; collect data corresponding to the execution of the boot task on the first processor component; categorize the boot task based on the collected data; and generate an entry for a boot table based on the categorization, the boot table used to schedule the boot task on at least one of the first processor component or a second processor component different than the first processor component based on the categorization.
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http:/Wwww.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROCIO DEL MAR PEREZ-VELEZ can be reached on 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer
Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUA J SONG/Primary Examiner, Art Unit 2133
Prosecution Insights