DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed June 4, 2025, fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because there are no references listed on the IDS. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 14 discloses a method for operating a memory device, comprising multiple steps. However, the claim language does not appear to disclose what is performing the relevant steps (e.g., “applying a program voltage”). Based on this, the claim fails to particularly point out and distinctly claim the subject matter to be regarded as the invention.
Therefore, claim 14 is rejected under 35 U.S.C. 112(b) as being indefinite.
Claims 15-20 do not appear to remedy the deficiencies of the antecedent claim 14; therefore, they are rejected by the same reasoning accordingly.
Allowable Subject Matter
Claims 1-13 are allowed.
Claims 14-20 appear to contain allowable subject matter but cannot be allowed at this time due to issues under 35 U.S.C. 112(b).
The following is a statement of reasons for the indication of allowable subject matter:
Referring to independent claim 1, the prior art of record does not appear to anticipate, explicitly teach, or fairly suggest in response to the interrupt signal, after applying the program voltage to the first word line, apply a first voltage to a first select line coupled to the first select gate transistor.
Further, it would not have been obvious to combine the above limitations with the remaining limitations of the claim.
Chou et al. (US 2019/0371398) discloses wherein a transistor generates voltage difference VDS having a value equal to a value of the drain-source voltage of the selection transistor having the same transistor bias. However, the reference does not appear to anticipate, explicitly teach, or fairly suggest the subject matter determined to be allowable.
Hsu et al. (US 2009/0190402) discloses wherein the power detection circuit detects a power interruption of the integrated nonvolatile static random access memory circuit, and the digital signal retained in the static random access memory cell is programmed to the first floating gate tunnel oxide transistor. However, the reference does not appear to anticipate, explicitly teach, or fairly suggest the subject matter determined to be allowable.
Lee (US 2007/0150770) discloses a power-up signal generating section connected to a terminal for an external source, configured to generate a power-up signal when the external source reaches a predetermined target level and to selectively interrupt a path from the external source terminal in response to a selection signal. However, the reference does not appear to anticipate, explicitly teach, or fairly suggest the subject matter determined to be allowable.
Rao et al. (US 2009/0160253) discloses the first and second sets of transistors are electrically coupled such that a single control signal from the power control logic circuit activates the first set of transistors and the second set of transistors. However, the reference does not appear to anticipate, explicitly teach, or fairly suggest the subject matter determined to be allowable.
Butts (US 5,978,460) discloses wherein lowered potential is not effective to activate the microprocessor until a first transistor is turned on by a second transistor activating a microprocessor interrupt lead. However, the reference does not appear to anticipate, explicitly teach, or fairly suggest the subject matter determined to be allowable.
Kinerk et al. (US 5,486,824) discloses wherein the output buffer of a first input/output register overdrives the corresponding column's pullup transistor to cause a second input/output register to recognize a logic low level on a column with an activated key. However, the reference does not appear to anticipate, explicitly teach, or fairly suggest the subject matter determined to be allowable.
Note that independent claims 11 and 14 contain the corresponding limitations of claim 1 as shown above; therefore, they are considered to contain allowable subject matter by the same reasoning accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chou et al. (US 2019/0371398) discloses wherein a transistor generates voltage difference VDS having a value equal to a value of the drain-source voltage of the selection transistor having the same transistor bias.
Hsu et al. (US 2009/0190402) discloses wherein the power detection circuit detects a power interruption of the integrated nonvolatile static random access memory circuit, and the digital signal retained in the static random access memory cell is programmed to the first floating gate tunnel oxide transistor.
Lee (US 2007/0150770) discloses a power-up signal generating section connected to a terminal for an external source, configured to generate a power-up signal when the external source reaches a predetermined target level and to selectively interrupt a path from the external source terminal in response to a selection signal.
Rao et al. (US 2009/0160253) discloses the first and second sets of transistors are electrically coupled such that a single control signal from the power control logic circuit activates the first set of transistors and the second set of transistors.
Butts (US 5,978,460) discloses wherein lowered potential is not effective to activate the microprocessor until a first transistor is turned on by a second transistor activating a microprocessor interrupt lead.
Kinerk et al. (US 5,486,824) discloses wherein the output buffer of a first input/output register overdrives the corresponding column's pullup transistor to cause a second input/output register to recognize a logic low level on a column with an activated key.
However, the above references do not appear to anticipate, explicitly teach, or fairly suggest the subject matter determined to be allowable.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN B ROCHE whose telephone number is (571)270-1721. The examiner can normally be reached Monday-Friday, 10:30 - 7.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.B.R/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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