DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1 – 8, 10 – 13, and 15 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Mathews et al. (US Publication Number 2020/0057579, hereinafter “Mathews”) in view of Fredenberg et al. (US Publication Number 2011/0296068, hereinafter “Fredenberg”) further in view of Kotzur et al. (US Patent Number 6,098,109, hereinafter “Kotzur”).
4. As per claim 1, Mathews teaches a controller comprising: a set of input ports to receive a plurality of requests; a set of channels (memory controller 101 receiving requests over virtual channels 110, routed to memory banks, figure 1); multiple sets of channel queues (memory banks 107 for memory 104-106, figure 1), in which each set of channel queues is associated with a respective input port of the set of input ports (association between channel and the banks handled via 103, paragraphs 32), and each set of channel queues including a channel queue for a respective channel of the set of channels (handled via the queue circuit 102, figure 1 and further seen in figure 2, paragraphs 29 and 31); and an interface coupled to the set of arbitration circuits and to the set of channels, the interface to receive requests obtained by the set of arbitration circuits, arbitrate among the received requests, and route each received request to a channel of the set of channels based on the arbitration (figure 3, arbitration circuit 103 handles the access requests across bank arbitration configured to select which bank is accessed in a given cycle, paragraph 32).
Mathews does not appear to explicitly disclose an interleave circuit to: receive the plurality of requests, and store each request of the plurality of requests in a channel queue of the set of channel queues corresponding to the input port from which the request is received; a set of arbitration circuits associated with the set of input ports, respectively, and associated with the set of channel queues of the associated input port, each of the arbitration circuits to select an arbitration algorithm from among multiple arbitration algorithms, and to arbitrate, using the selected arbitration algorithm, to select a channel queue, of the associated set of channel queues, from which to obtain a memory request.
However, Fredenberg discloses an interleave circuit to: receive the plurality of requests, and store each request of the plurality of requests in a channel queue of the set of channel queues corresponding to the input port from which the request is received (router funnels a data path associated with a plurality of channels before reaching arbiter 104, figure 1, front end circuit that sorts incoming traffic by channel for arbitration and keeping track of resource usage per requester for time slice, 110 to 112).
Mathews and Fredenberg are analogous art because they are from the same field of endeavor data arbitration.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mathews and Fredenberg before him or her, to modify the arbitration mechanism of Mathews to include the structure of Fredenberg because enhance the process of winning for data transfers.
One of ordinary skill would be motivated to make such modification in order to improve performance of the memory subsystem (paragraphs 3 – 5). Therefore, it would have been obvious to combine Fredenberg with Mathews to obtain the invention as specified in the instant claims.
Mathews/Fredenberg does not appear to explicitly disclose a set of arbitration circuits associated with the set of input ports, respectively, and associated with the set of channel queues of the associated input port, each of the arbitration circuits to select an arbitration algorithm from among multiple arbitration algorithms, and to arbitrate, using the selected arbitration algorithm, to select a channel queue, of the associated set of channel queues, from which to obtain a memory request;
However, Kotzur discloses a set of arbitration circuits associated with the set of input ports, respectively, and associated with the set of channel queues of the associated input port, each of the arbitration circuits to select an arbitration algorithm from among multiple arbitration algorithms, and to arbitrate, using the selected arbitration algorithm, to select a channel queue, of the associated set of channel queues, from which to obtain a memory request (arbitration circuits via 504 figure 4 which is seen in the HCB 402, figure 4, for priority based arbitration logic to select a port having the next highest priority which includes a plurality of algorithms including round-robin, first come first served).
Mathews/Fredenberg and Kotzur are analogous art because they are from the same field of endeavor of arbitration handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mathews/Fredenberg and Kotzur before him or her, to modify the arbitration mechanism of Mathews/Fredenberg to include the structure of Kotzur because enhance the process of winning for data transfers.
One of ordinary skill would be motivated to make such modification in order to enhance the arbitration mechanism (column 2, lines 33 – 47) Therefore, it would have been obvious to combine Kotzur with Mathews/Fredenberg to obtain the invention as specified in the instant claims.
5. As per claims 6 and 11, Mathews teaches a controller and medium comprising: a set of input ports to receive a plurality of requests, including a first input port; a set of channels (memory controller 101 receiving requests over virtual channels 110, routed to memory banks, figure 1); multiple sets of channel queues (memory banks 107 for memory 104-106, figure 1) including a first set of channel queues, in which each set of channel queues is associated with a respective input port of the set of input ports (association between channel and the banks handled via 103, paragraphs 32), the first set of channel queues being associated with the first input port, and each set of channel queues including a channel queue for a respective channel of the set of channels (handled via the queue circuit 102, figure 1 and further seen in figure 2, paragraphs 29 and 31); an interface coupled to the set of arbitration circuits and to the set of channels, the interface to receive requests obtained by the set of arbitration circuits, arbitrate among the received requests, and route each received request to a channel of the set of channels based on the arbitration (figure 3, arbitration circuit 103 handles the access requests across bank arbitration configured to select which bank is accessed in a given cycle, paragraph 32).
Mathews does not appear to explicitly disclose a set of interleave circuits coupled to the set of input ports, respectively, including a first interleave circuit coupled to the first input port; a set of arbitration circuits associated with the set of input ports, respectively, including a first arbitration circuit associated with the first input port, the set of arbitration circuits associated with the set of channel queues of the associated input port, the first arbitration circuit associated with the first set of channel queues to arbitrate among the first set of channel queues using an arbitration algorithm selected among multiple arbitration algorithms; a first buffer coupled to the first input port to store an address for each request received through the first input port; and a second buffer coupled to the first interleave circuit to store, for each request received through the first input port, at least one of a command for the request and data associated with the request.
However, Fredenberg discloses a set of interleave circuits coupled to the set of input ports, respectively, including a first interleave circuit coupled to the first input port (router funnels a data path associated with a plurality of channels before reaching arbiter 104, figure 1, front end circuit that sorts incoming traffic by channel for arbitration and keeping track of resource usage per requester for time slice, 110 to 112); a first buffer coupled to the first input port to store an address for each request received through the first input port; and a second buffer coupled to the first interleave circuit to store, for each request received through the first input port, at least one of a command for the request and data associated with the request (106, figure 1, limiting access to quantum size per access per requester per arbitration cycle and queueing up to two of the quantum burst to the protocol engine circuit at a time which requires the request body to be held in a staging store while the arbitration proceeds on the request identity).
Mathews and Fredenberg are analogous art because they are from the same field of endeavor data arbitration.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mathews and Fredenberg before him or her, to modify the arbitration mechanism of Mathews to include the structure of Fredenberg because enhance the process of winning for data transfers.
One of ordinary skill would be motivated to make such modification in order to improve performance of the memory subsystem (paragraphs 3 – 5). Therefore, it would have been obvious to combine Fredenberg with Mathews to obtain the invention as specified in the instant claims.
Mathews/Fredenberg does not appear to explicitly disclose a set of arbitration circuits associated with the set of input ports, respectively, including a first arbitration circuit associated with the first input port, the set of arbitration circuits associated with the set of channel queues of the associated input port, the first arbitration circuit associated with the first set of channel queues to arbitrate among the first set of channel queues using an arbitration algorithm selected among multiple arbitration algorithms.
However, Kotzur discloses a set of arbitration circuits associated with the set of input ports, respectively, including a first arbitration circuit associated with the first input port, the set of arbitration circuits associated with the set of channel queues of the associated input port, the first arbitration circuit associated with the first set of channel queues to arbitrate among the first set of channel queues using an arbitration algorithm selected among multiple arbitration algorithms (arbitration circuits via 504 figure 4 which is seen in the HCB 402, figure 4, for priority based arbitration logic to select a port having the next highest priority which includes a plurality of algorithms including round-robin, first come first served).
Mathews/Fredenberg and Kotzur are analogous art because they are from the same field of endeavor of arbitration handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Mathews/Fredenberg and Kotzur before him or her, to modify the arbitration mechanism of Mathews/Fredenberg to include the structure of Kotzur because enhance the process of winning for data transfers.
One of ordinary skill would be motivated to make such modification in order to enhance the arbitration mechanism (column 2, lines 33 – 47) Therefore, it would have been obvious to combine Kotzur with Mathews/Fredenberg to obtain the invention as specified in the instant claims.
6. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 1 above, as per claim 2, Mathew teaches a controller, wherein the interleave circuit is further to determine a target channel for each request of the plurality of requests based on information associated with the request and to place that request in the channel queue, of the corresponding set of channel queues, for the target channel (figures 1 and 3, requests are queued in 102 with respect to particular bank 107a…n they target which allows per bank arbitration circuit 301 to arbitrate for a given bank, the destination from request before arbitration and held in associated queue, paragraphs 30 – 34).
7. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 1 above, as per claims 3 and 17, Fredenberg teaches a controller and method, wherein the interleave circuit includes a set of interleave components coupled to the set of input ports, respectively, and to a respective set of the multiple sets of channel queues (router funnels a data path associated with a plurality of channels before reaching arbiter 104, figure 1, front end circuit that sorts incoming traffic by channel for arbitration and keeping track of resource usage per requester for time slice, 110 to 112).
8. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 1 above, as per claim 4, Mathew teaches a controller, wherein the set of arbitration circuits is a first set of arbitration circuits, the interface including a second set of arbitration circuits, the arbitration circuits of the second set of arbitration circuits respectively coupled to the arbitration circuits of the first set of arbitration circuits and to the set of channels (figures 1 and 3, requests are queued in 102 with respect to particular bank 107a…n they target which allows per bank arbitration circuit 301 to arbitrate for a given bank, the destination from request before arbitration and held in associated queue, paragraphs 30 – 34).
9. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 1 above, as per claims 5 and 7, Mathew teaches a controller, wherein each set of channel queues includes a real-time channel queue for each channel of the set of channels and a non-real-time channel queue for each channel of the set of channels (LLT vs RT handling by the memory controller, paragraph 37).
10. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 6 above, as per claim 8, Mathew teaches a controller, further comprising: a control register coupled to the first arbitration circuit, in which the control register stores a value that determines which of the multiple arbitration algorithms the first arbitration circuit is to use in arbitrating among the first set of channel queues to identify a specific request to present to the interface (arbitration circuits via 504 figure 4 which is seen in the HCB 402, figure 4, for priority based arbitration logic to select a port having the next highest priority which includes a plurality of algorithms including round-robin, first come first served).
11. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 6 above, as per claim 10, Mathew teaches a controller, wherein the interface includes a set of arbitration components respectively coupled to the set of arbitration circuits and to the set of channels (per bank arbitration among access requests from different virtual channels 110 for a given bank provided to across bank arbitration circuit 304 which is configured to select access for given cycle, figures 1 and 3).
12. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 11 above, as per claim 12, Kotzur teaches a medium, wherein the multiple arbitration algorithms include at least two of: a round-robin algorithm, request-priority-based algorithm, channel- load based algorithm, and a channel queue age-based algorithm (arbitration circuits via 504 figure 4 which is seen in the HCB 402, figure 4, for priority based arbitration logic to select a port having the next highest priority which includes a plurality of algorithms including round-robin, first come first served).
13. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 11 above, as per claim 13, Fredenberg teaches a medium, wherein the stored instructions, when executed by the processing circuitry, cause the controller to: determine which channel or channels of the set of channels are experiencing throughput below a set level (resource usage per requester tracked for reducing bank collisions and arbitration circuit measures how each destination is performing over a window, paragraphs 7 and 63).
14. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 11 above, as per claim 15, Mathew teaches a medium, wherein, for each request, the channel to which a pathway is determined is specified by an address associated with the request (destination 107a…n for per bank arbitration 301, figures 1 and 3).
15. Mathews modified by the teachings of Fredenberg/Kotzur as seen in claim 11 above, as per claim 16, Fredenberg teaches a medium, wherein the stored instructions, when executed by the processing circuitry, cause the controller to: withdraw a request for presentation to the interface, when the request is not selected within a set amount of time (106, figure 1, limiting access to quantum size per access per requester per arbitration cycle and queueing up to two of the quantum burst to the protocol engine circuit at a time which requires the request body to be held in a staging store while the arbitration proceeds on the request identity).
Allowable Subject Matter
16. Claims 9, 14, and 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
17. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bauman/Bender/Hathorn/Lam/Pandya/Theobald have teachings of channel queue arbitration.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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