Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. The Amendment filed on 07/27/2026 has been entered. Claims 1 and 19 have been amended. Claims 7 and 8 have been canceled. Claims 16 and 17 have been withdrawn from consideration. Claims 1-6 and 9-20 remain pending in the application. Rejection of claim 19 under 35 U.S.C. 112(a) (pre-AIA 35 U.S.C. 112, first paragraph) is withdrawn.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-3, 9, 12-15, and 20 are rejected under 35 U.S.C. 103 as unpatentable over LEE (US 20210288135 A1) in view of WANG (US 20190304374 A1).
Regarding claim 1, LEE (Figs. 1, 3-4, and 7-15) discloses a display substrate, comprising:
a base substrate (base substrate 100) including a display area (display area 10) and a peripheral area located on at least one side of the display area (peripheral area 20);
a pixel array, located in the display area and including a plurality of pixel units (display area comprising display an array of pixel circuits PC); and,
a scan driving module, located in a driving circuit area of the peripheral area, and including a plurality of shift register units (e.g., Figs. 1 and 3 and [0056]-[0057]; gate driver 200 comprising a plurality of shift register units 220 and located in a driving circuit area of the peripheral area 20), a plurality of signal lines being arranged in one shift register unit of the plurality of shift register units, and the plurality of signal lines extending along a first direction (e.g., Fig. 3 and [0068]-[0070]; each shift register unit 220 comprising voltage signal line 201, start signal line 202, clock signal line 203 extending in a first direction D1);
the shift register unit comprises at least two transistors arranged in the driving circuit area (e.g., Figs. 3 and 4 and [0072]-[0073]; each shift register unit 220 comprising transistors M1-M8);
active layers of the at least two transistors are formed by a continuous semiconductor layer, and an orthographic projection of one signal line of the plurality of signal lines on the base substrate at least partially overlaps an orthographic projection of the semiconductor layer on the base substrate (Figs. 7-15 and [0109], [0144]; each transistor has a corresponding active layer, e.g., in Fig. 15, a semiconductor layer comprises active layers 112 and 182 of the transistors 115 and 185, the transistors 115 and 185 corresponding to transistors M5 and M6 in Fig. 4, an orthographic projection of voltage signal line 201 partially overlaps an orthographic projection of the active layer 112 of the transistor 115);
a first electrode comprised in at least one of the at least two transistors is arranged at a first conductive layer (e.g., Fig. 15; source/drain electrode of transistor 115 and source/drain electrode of transistor 185 are arranged at a layer corresponding to a first conductive layer), and one of the plurality of signal lines is arranged at a second conductive layer, and configured to provide a DC power signal (e.g., Fig. 15 and [0068]; voltage signal line 201 is arranged at a layer corresponding to a second conductive layer and is configured to provide a constant voltage signal).
wherein the display substrate comprises a first conductive layer (e.g., Fig. 15; a first conductive layer comprising source/drain electrode of transistor 115 and source/drain electrode of transistor 185), an insulating layer (e.g., Fig. 15; insulating layer 150), and a second conductive layer (e.g., Fig. 15; a second conductive layer comprising voltage signal line 201) which are stacked, and the insulating layer (e.g., Fig. 15; insulating layer 150) is arranged between the first conductive layer (e.g., Fig. 15; first conductive layer comprising source/drain electrode of transistor 115 and source/drain electrode of transistor 185) and the second conductive layer (e.g., Fig. 15; second conductive layer comprising voltage signal line 201);
at least one signal line of the plurality of signal lines is arranged on the first conductive layer (e.g., Fig. 15; clock signal line 203 is arranged on the first conductive layer comprising the source/drain electrode of transistor 115 and the source/drain electrode of transistor 115), and at least one signal line of the plurality of signal lines is arranged on the second conductive layer (e.g., Fig. 15; voltage signal line 201 is arranged on a layer corresponding to a second conductive layer);
the shift register unit comprises at least one transistor arranged in the driving circuit area (e.g., Fig. 15 and [0109], [0144]; transistor 115 and transistor 185, corresponding to transistors M5 and M6 in Fig. 4), a first electrode of the transistor, a second electrode of the transistor and at least one of the plurality of signal lines are arranged on a same layer and formed using a same metal layer (e.g., Fig. 15 and [0108], [0114]; the source/drain electrode of transistor 115, the source/drain electrode of transistor 185, and the clock signal line 203 are arranged on a same conductive layer and formed using a same metal layer).
LEE does not expressly disclose active layers of the at least two transistors are formed by a continuous semiconductor layer. However, WANG (Figs. 1-4 and 7-10) discloses a shift register similar to that disclosed by LEE, wherein active layers of the at least two transistors are formed by a continuous semiconductor layer (e.g., Figs. 3-4, 8, and 10; each transistor has a corresponding active layer L4, active layers of the at least two transistors connected to each other (e.g., TE1 and TE2, TE4 and TE5, and TE8 and TE9) are formed by a continuous semiconductor layer). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from WANG with LEE. The combination/motivation would be to provide a shift register with a compact design and a reduced cost.
Regarding claim 2, LEE in view of WANG discloses the display substrate according to claim 1, LEE (Figs. 1, 3-4, and 7-15) discloses wherein the plurality of signal lines include all signal lines in the shift register unit (e.g., Fig. 3 and [0068]-[0070]; each shift register unit 220 comprising voltage signal line 201, start signal line 202, clock signal line 203). WANG (e.g., Figs. 2 and 4 and [0058]) discloses the same features as claimed.
Regarding claim 3, LEE in view of WANG discloses the display substrate according to claim 1, LEE (Figs. 1, 3-4, and 7-15) discloses wherein the plurality of signal lines include all signal lines overlapping an orthographic projection of the shift register unit on the base substrate (e.g., Fig. 4; voltage signal line 201, start signal line 202, clock signal line 203 overlap the shift register unit 220). WANG (e.g., Fig. 4) discloses the same features as claimed.
Regarding claim 9, LEE in view of WANG discloses the display substrate according to claim 1, LEE (Figs. 1, 3-4, and 7-15) discloses wherein the shift register unit (shift register unit 220) includes at least one transistor arranged in the driving circuit area (e.g., Figs. 15 and 4; transistor 115 or transistor 185 corresponding to transistors M5 or M6), a first electrode of the transistor and a second electrode of the transistor (source/drain electrode of transistor 115 or transistor 185) are arranged on a same layer, and at least one of the plurality of signal lines (voltage signal line 201) and the first electrode of the transistor (source/drain electrode of transistor 115 or transistor 185) are arranged at different layers (e.g., Fig. 15).
Regarding claim 12, LEE in view of WANG discloses the display substrate according to claim 1, WANG (Figs. 1-4) discloses wherein the shift register unit (shift register unit STE) comprises a fourth transistor (transistor TE8), and a fifth transistor (transistor TE9); a second electrode of the fourth transistor (transistor TE8) is coupled to a second electrode of the fifth transistor (transistor TE9); an active layer of the fourth transistor, and an active layer of the fifth transistor are formed by a continuous first semiconductor layer (e.g., Figs. 3 and 4; each of transistors TE8 and TE9 having a corresponding active layer L4, a continuous semiconductor layer comprising active layers of the transistors TE8 and TE9); the orthographic projection of the active layer of the fourth transistor on the base substrate and the orthographic projection of the active layer of the fifth transistor on the base substrate together form an L-type pattern (e.g., Fig. 4; active layer of transistor TE8 and active layer of transistor TE9 forming a L-shape pattern). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from WANG with LEE for the same reason above.
Regarding claim 13, LEE in view of WANG discloses the display substrate according to claim 12, WANG (Figs. 1-4) discloses wherein the shift register unit comprises a plurality of signal lines, and the plurality of signal lines comprises a first voltage line (clock signal lines CLK_E1 and CLK_E2 and voltage signal lines VGL and VGH); an orthographic projection of the first voltage line (high voltage signal line VGH) on the base substrate partially overlaps an orthographic projection of the first semiconductor layer (semiconductor layer comprising active layers of the transistors TE8 and TE9) on the base substrate (Fig. 4). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from WANG with LEE for the same reason above.
Regarding claim 14, LEE in view of WANG discloses the display substrate according to claim 1, WANG (Figs. 1-4) discloses wherein the shift register unit (shift register unit STE) comprises a second transistor (transistor TE1) and a third transistor (transistor TE2); a second electrode of the second transistor (transistor TE1) is coupled to a second electrode of the third transistor (transistor TE2); an active layer of the second transistor and an active layer of the third transistor are formed by a continuous fourth semiconductor layer (e.g., Figs. 3 and 4; each of transistors TE1 and TE2 having a corresponding active layer L4, a continuous semiconductor layer comprising active layers of the transistors TE1 and TE2), and an orthographic projection of the active layer of the second transistor on the base substrate and an orthographic projection of the active layer of the third transistor on the base substrate together form an I-type pattern (e.g., Fig. 4; active layer of transistor TE1 and active layer of transistor TE2 forming a I-shape pattern). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from WANG with LEE for the same reason above.
Regarding claim 15, LEE in view of WANG discloses the display substrate according to claim 14, WANG (Figs. 1-4) discloses wherein a channel of the second transistor extends along the first direction, and a channel of the third transistor extends along the first direction (Fig. 4, channels of transistors TE1 and TE2 extend in Y direction). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from WANG with LEE for the same reason above.
Regarding claim 20, LEE in view of WANG discloses a display device (LEE, Fig. 1, display device; Wang, Fig. 1, display device) comprising the display substrate according to claim 1.
5. Claims 5 and 11 are rejected under 35 U.S.C. 103 as unpatentable over LEE (US 20210288135 A1) in view of WANG (US 20190304374 A1) and further in view of KIM (US 20220148502 A1).
Regarding claim 5, LEE in view of WANG discloses the display substrate according to claim 1, but does not disclose wherein a ratio of a sumW1 of widths of the plurality of signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and W1/W2 is greater than 0.4 and less than 0.7. However, KIM (e.g., Figs. 6, 8, and 15) discloses a display device comprising a shift register similar to that disclosed by WANG, wherein each shift register unit STE comprising clock signal lines CLK1 and CLK2 and voltage signal lines VGL and VGH, and wherein a ratio of a sumW1 of widths of the plurality of signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and W1/W2 is greater than 0.4 and less than 0.7 ([0323]; 4
×
12/100=0.48). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIM to the shift register of the display device of LEE in view of WANG. The combination/motivation would be to provide an arrangement of signal lines and scan drivers to reduce non-display area.
Regarding claim 11, LEE in view of WANG discloses the display substrate according to claim 1, wherein the shift register unit comprises at least one signal line arranged in the driving circuit area, the at least one signal line is configured to provide a clock signal (clock signal lines 203 or clock signal line CLK_E); but does not disclose a ratio W4/W2 of a width W4 of at least one of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.015. However, KIM (e.g., Figs. 6, 8, and 15) discloses a display device comprising a shift register similar to that disclosed by WANG, wherein each shift register unit STE comprising clock signal lines CLK1 and CLK2, wherein a ratio W4/W2 of a width W4 of at least one of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.015 ([0323]; 12/100=0.12>0.015). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIM to the shift register of the display device of LEE in view of WANG for the same reason above.
6. Claims 4 and 6 are rejected under 35 U.S.C. 103 as unpatentable over LEE (US 20210288135 A1) in view of WANG (US 20190304374 A1) and further in view of KIM (US 20220148502 A1) and SHIN (US 20150311263 A1).
Regarding claim 4, LEE in view of WANG discloses the display substrate according to claim 1, but does not disclose wherein a ratio of a sumW1 of widths of the plurality of signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and a length of at least one pixel unit along the first direction is a pixel pitch value; the first direction intersects the second direction; a product of W1/W2 and the pixel pitch value is greater than 18um and less than 40um. However, KIM (e.g., Figs. 6, 8, and 15) discloses a display device comprising a shift register similar to that disclosed by WANG, wherein each shift register unit STE comprising clock signal lines CLK1 and CLK2 and voltage signal lines VGL and VGH, wherein a ratio of a sumW1 of widths of the plurality of signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and W1/W2 is greater than 0.15 and less than 0.5 ([0323]). SHIN further discloses a length of at least one pixel unit along the first direction is a pixel pitch value ([0035]; pixel length L=126um). Therefore, the combination of KIM and SHIN discloses a product of W1/W2 and the pixel pitch value is greater than 18um and less than 40um (e.g., W1/W2
×
L=0.16
×
126=20um). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIM and SHIN to the shift register of the display device of LEE in view of WANG. The combination/motivation would be to provide an arrangement of signal lines and scan drivers in accordance with display pixels to reduce non-display area.
Regarding claim 6, LEE in view of WANG and further in view of KIM and SHIN discloses the display substrate according to claim 4, the combination of KIM ([0323]) and SHIN ([0035]) discloses wherein a product of W1/W2 and the pixel pitch value is greater than 18um and less than or equal to 27um (e.g., W1/W2
×
L=0.16
×
126=20um). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIM and SHIN to the shift register of the display device of LEE in view of WANG for the same reason above.
7. Claim 10 is rejected under 35 U.S.C. 103 as unpatentable over LEE (US 20210288135 A1) in view of WANG (US 20190304374 A1) and further in view of KIM (US 20220148502 A1) and JEONG (US 20170062532 A1).
Regarding claim 10, LEE in view of WANG discloses the display substrate according to claim 1, wherein the shift register unit includes at least one signal line arranged in the driving circuit area, the at least one signal line is configured to provide a DC power signal (e.g., voltage signal line 201 line providing DC power); but does not disclose a ratio W3/W2 of a width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.15. However, KIM (e.g., Figs. 6, 8, and 15) discloses a display device comprising a shift register similar to that disclosed by WANG, wherein each shift register unit STE comprising clock signal lines CLK1 and CLK2 and voltage signal lines VGL and VGH, wherein a ratio W3/W2 of a width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.15 ([0323]; 12/100=0.12, close to 0.15). As another reference, JEONG (Figs. 1-2) discloses at least one signal line is configured to provide a DC power signal (e.g., VHG line 121 providing DC power) and having a width W3 of the at least one signal line in the second direction (e.g., [0036]; 30um). Therefore, the combination of KIM and JEONG discloses wherein a ratio W3/W2 of a width W3 of the at least one signal line in the second direction to the width W2 of the shift register unit in the second direction is greater than or equal to 0.15 (W3/W2=0.3). It would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from KIM and JEONG to the shift register of the display device of LEE in view of WANG for the high voltage signal transmission.
8. Claim 18 is rejected under 35 U.S.C. 103 as unpatentable over LEE (US 20210288135 A1) in view of WANG (US 20190304374 A1) and further in view of CHO (US 20220157960 A1).
Regarding claim 18, LEE in view of WANG discloses the display substrate according to claim 1, but does not disclose wherein the shift register unit includes at least two transistors arranged in the driving circuit area; active layers of the at least two transistors are formed by a continuous semiconductor layer; a shape of at least part of semiconductor pattern included in the semiconductor layer is a π type. However, CHO (e.g., Figs. 1-5) discloses two transistors are formed by a continuous semiconductor layer; a shape of at least part of semiconductor pattern included in the semiconductor layer is a π type (e.g., Figs. 1-5 and [0032], [0036], [0038], and [0051], two transistors connected with a π shape semiconductor channel pattern). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from CHO and SHIN to the shift register of the display device of LEE in view of WANG to improve the performance of transistors.
9. Claim 19 is rejected under 35 U.S.C. 103 as unpatentable over LEE (US 20210288135 A1) in view of WANG (US 20190304374 A1) and further in view of XU (CN210956110U, using US11062645B1 as a corresponding English translation).
Regarding claim 19, LEE in view of WANG discloses the display substrate according to claim 1, but does not disclose the structure of the shift register as claimed. However, XU (e.g., Fig. 6) discloses wherein the shift register unit comprises a plurality of signal lines, a plurality of transistors and a plurality of capacitors; the plurality of signal lines include: a first voltage line (voltage line VGH), a second voltage line (voltage line VGL), a first clock signal line (clock signal line CKB), a second clock signal line (clock signal line CK), and a third clock signal line (second clock signal line CK), and the plurality of transistors include: a first transistor (transistor T1), a second transistor (transistor T2), a third transistor (transistor T3), a fourth transistor (transistor T4), a fifth transistor (transistor T5), a sixth transistor (transistor T6), a seventh transistor (transistor T7), an eighth transistor (transistor T8), a ninth transistor (transistor T9), a tenth transistor (transistor T10), an eleventh transistor (transistor T11), a twelfth transistor (transistor T12) and a thirteenth transistor (transistor T13); the plurality of capacitors include: a first capacitor (capacitor C1), a second capacitor (capacitor C2) and a third capacitor (capacitor C3); a gate electrode of the first transistor (transistor T1) is coupled to the third clock signal line (second clock signal line CK), a first electrode of the first transistor (transistor T1) is coupled to an input terminal (input terminal STV), a second electrode of the first transistor (transistor T1) is coupled to a gate electrode of the second transistor (transistor T2); a first electrode of the second transistor (transistor T2) is coupled to the third clock signal line (second clock signal line CK), and a second electrode of the second transistor (transistor T2) is coupled to a second electrode of the third transistor (transistor T3); a gate electrode of the third transistor (transistor T3) is coupled to the third clock signal line (second clock signal line CK), and a first electrode of the third transistor (transistor T3) is coupled to the second voltage line (voltage line VGL); a first electrode of the fourth transistor (transistor T4) is coupled to the first clock signal line (clock signal line CKB), a second electrode of the fourth transistor (transistor T4) is coupled to a second electrode of the fifth transistor (transistor T5); a gate electrode of the fifth transistor (transistor T5) is coupled to the second electrode of the third transistor (transistor T3), and a first electrode of the fifth transistor (transistor T5) is coupled to the first voltage line (voltage line VGH); a gate electrode of the sixth transistor (transistor T5) is coupled to a second electrode of the eleventh transistor (transistor T12), a first electrode of the sixth transistor (transistor T6) is coupled to the first clock signal line (clock signal line CKB), and a second electrode of the sixth transistor (transistor T6) is coupled to a first electrode of the seventh transistor (transistor T7); a gate electrode of the seventh transistor (transistor T7) is coupled to the first clock signal line (clock signal line CKB), and a second electrode of the seventh transistor (transistor T7) is coupled to a gate electrode of the ninth transistor (transistor T9); a gate electrode of the eighth transistor (transistor T8) is coupled to a second electrode of the thirteenth transistor (transistor T13), a first electrode of the eighth transistor (transistor T8) is coupled to a gate electrode of the ninth transistor (transistor T9), and a second electrode of the eighth transistor (transistor T8) is coupled to the first voltage line (voltage line VGH); a first electrode of the ninth transistor (transistor T9) is coupled to the first voltage line (voltage line VGH), and a second electrode of the ninth transistor (transistor T9) is coupled to a driving signal output terminal (output terminal OUT); a first electrode of the tenth transistor (transistor T10) is coupled to the driving signal output terminal (output terminal OUT), and a second electrode of the tenth transistor (output terminal OUT) is coupled to the second voltage line (voltage line VGL); a gate electrode of the eleventh transistor (transistor T12) is coupled to the second voltage line (voltage line VGL), and a first electrode of the eleventh transistor (transistor T12) is coupled to the gate electrode of the fifth transistor (transistor T5); a gate electrode of the twelfth transistor (transistor T11) is coupled to the second voltage line (voltage line VGL), a first electrode of the twelfth transistor (transistor T11) is coupled to the second electrode of the first transistor (transistor T1), and a second electrode of the twelfth transistor (transistor T11) is electrically connected to the gate electrode of the tenth transistor (transistor T10); a gate electrode of the thirteenth transistor is coupled to the second clock signal line, a first electrode of the thirteenth transistor is coupled to the first voltage line, a second electrode of the thirteenth transistor is coupled to the gate electrode of the second transistor; a first electrode plate of the first capacitor (capacitor C2) is coupled to the gate electrode of the sixth transistor (transistor T6), and a second electrode plate of the first capacitor (capacitor C2) is coupled to the second electrode of the sixth transistor (transistor 6); a first electrode plate of the second capacitor (capacitor C3) is coupled to the gate electrode of the ninth transistor (transistor T9), and a second electrode plate of the second capacitor (capacitor C3) is coupled to the first voltage line (voltage line VGH); a first electrode plate of the third capacitor (capacitor C1) is coupled to the gate electrode of the fourth transistor (transistor T4), and a second electrode plate of the third capacitor (capacitor C1) is coupled to the second electrode of the fourth transistor (transistor T4). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from XU to the shift register of the display device of LEE in view of WANG. The combination/motivation would be to provide a shift register for a display device.
Response to Arguments
10. Regarding claim 1, applicant’s arguments have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. In view of amendments, the reference of LEE (US 20210288135 A1) has been used for new ground rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Yuzhen Shen whose telephone number is (571)272-1407. The examiner can normally be reached on Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
Prosecution Insights