DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-31 are pending in the instant application. Claims 1-23, 25-27 and 31 are elected and claims 24 and 28-30 are withdrawn from consideration as being directed to a non-elected species.
Election/Restrictions
Applicant’s election of Species A (claims 1-23, 25-27, and 31) in the reply filed on 06/17/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/05/2025 is being considered by the examiner.
Claim Objections
Claim 7 is objected to because of the following informalities:
Claim 7, line 2, recites “the same extension line”. Examiner suggests “a same extension line”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 14, 18, 21-22, 25, 27, and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 11910678 B1, hereinafter referenced as Zhang).
Regarding Claim 1, Zhang teaches a display apparatus (see abstract. Display panel) comprising:
a display area on which an image is displayed (see Figs. 2-3, col. 5 lines 15-46, the display panel 100 includes a display area AA. Note: Inherently the display panel display images in the display area);
a non-display area adjacent to the display area (see Figs. 2-3, col. 5 lines 15-46. A non-display area NA at least partially surrounding the display area AA);
a pixel in the display area (see Fig. 9, pixel circuit 60, first display area AA1, second display area AA2, Fig. 18, a light-emitting element D0, col. 10 lines 51-67, col. 11 lines 1-43. It should be noted that FIG. 9 only illustrates the pixel circuit 60 in the display panel in the form of a rectangular box, and for the layout and circuit structure of the pixel circuit 60 reference can be made to FIG. 10 and FIG. 18 respectively), the pixel including an anode electrode (see Fig. 18, anode of a light-emitting element D0, Fig. 6, col. 7 lines 49-54, col. 10 lines 31-50, col. 10 lines 63-67, col. 12 lines 6-10. The basic structure of the light-emitting layer of the OLED display panel generally include an anode RE In the embodiment shown in FIG. 9, reference can be made to FIG. 10 for the layout of the area where each pixel circuit 60 is located, and reference can be made to FIG. 18 for the specific composition of each pixel circuit 60. The electrodes of the seventh transistor T7 in the second reset module 95 may be respectively connected to the reset signal line Vref and a fourth node N4, and the fourth node N4 may be connected to the anode of a light-emitting element D0);
an anode reset line configured to reset the anode electrode (see Fig. 6, Fig. 18, col. 11 lines 8-13, col. 12 lines 5-10, col. 12 lines 22-31, col. 23 lines 65-67. The reset signal line Vref may be located on the capacitor metal layer MC. The electrodes of the seventh transistor T7 in the second reset module 95 may be respectively connected to the reset signal line Vref and a fourth node N4, and the fourth node N4 may be connected to the anode of a light-emitting element D0. The reset signal line Vref may be used to transmit reset signals. In the data writing stage t2, the second scan line Scan2 may be configured to provide a low-level signal to the second transistor T2, the fourth transistor T4, and the seventh transistor T7 to turn on the transistor T2, the fourth transistor T4, and the seventh transistor T7, the data signal may be written to the gate of the driving transistor T3 (or it can be referred to as the threshold grabbing of the driving transistor T3), and the reset signal may be sent to the fourth node N4 to reset the anode of the light-emitting element D0); and
a dummy line disposed in the display area, wherein the anode reset line is electrically connected to the dummy line (see Fig. 6, fourth metal layer M4, Fig. 31, L01, col. 11 lines 8-13, col. 12 lines 22-31, col. 21, lines 51-67, col. 22 lines 1-5, col. 23 lines 57-67, col. 24 lines 1-43. The connecting line L0 may be located on the fourth metal layer M4. FIG. 28 illustrates a technical solution in which the first connecting line segment L1, the second connecting line segment L2, the first virtual line segment L01, and the second virtual line segment L02 are arranged on the same layer. In this embodiment, these line segments are arranged on the fourth metal layer M4. The at least one first virtual line segment L01 and at least one second virtual line segment L02 may also be connected to a power signal line PVDD or a reset signal line Vref. FIG. 31 is a schematic connection diagram between a first virtual line segment and a second virtual line segment and a fixed voltage line. At least one first virtual line segment L01 may be electrically connected to a first fixed voltage line X1; and/or, at least one second virtual line segment may be electrically connected to a second fixed voltage line X2. The first fixed voltage line X1 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above, and the second fixed voltage line X2 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above).
Regarding Claim 2, Zhang teaches the display apparatus of claim 1.
Zhang further teaches wherein the pixel further includes a light-emitting element (see Fig. 9, pixel circuit 60, first display area AA1, second display area AA2, Fig. 18, a light-emitting element D0, col. 10 lines 51-67, col. 11 lines 1-43. It should be noted that FIG. 9 only illustrates the pixel circuit 60 in the display panel in the form of a rectangular box, and for the layout and circuit structure of the pixel circuit 60 reference can be made to FIG. 10 and FIG. 18 respectively) including the anode electrode (see Fig. 18, anode of a light-emitting element D0, Fig. 6, col. 7 lines 49-54, col. 10 lines 31-50, col. 10 lines 63-67, col. 12 lines 6-10. The basic structure of the light-emitting layer of the OLED display panel generally include an anode RE In the embodiment shown in FIG. 9, reference can be made to FIG. 10 for the layout of the area where each pixel circuit 60 is located, and reference can be made to FIG. 18 for the specific composition of each pixel circuit 60. The electrodes of the seventh transistor T7 in the second reset module 95 may be respectively connected to the reset signal line Vref and a fourth node N4, and the fourth node N4 may be connected to the anode of a light-emitting element D0), an organic layer (see Fig. 6, Fig. 18, col. 7 lines 42-62. A display panel using organic light-emitting diode display technology, that is, an OLED display panel. The array layer 10 may include a plurality of transistors TO, and the basic structure of the light-emitting layer of the OLED display panel generally include an anode RE, a light-emitting material layer 201, and a cathode 202), and a cathode electrode (see Fig. 18, cathode of a light-emitting element D0, Fig. 6, col. 7 lines 49-54. The basic structure of the light-emitting layer of the OLED display panel generally include an anode RE, a light-emitting material layer 201, and a cathode 202), and an initialization transistor configured to connect the anode electrode to the anode reset line (see Fig. 18, second reset module 95, col. 11 lines 44-67, col. 12 lines 1-31. The second reset module 95 may include a seventh transistor T7. The electrodes of the seventh transistor T7 in the second reset module 95 may be respectively connected to the reset signal line Vref and a fourth node N4, and the fourth node N4 may be connected to the anode of a light-emitting element D0. In the data writing stage t2, the second scan line Scan2 may be configured to provide a low-level signal to the second transistor T2, the fourth transistor T4, and the seventh transistor T7 to turn on the transistor T2, the fourth transistor T4, and the seventh transistor T7, the data signal may be written to the gate of the driving transistor T3 (or it can be referred to as the threshold grabbing of the driving transistor T3), and the reset signal may be sent to the fourth node N4 to reset the anode of the light-emitting element D0).
Regarding Claim 3, Zhang teaches the display apparatus of claim 2.
Zhang further teaches wherein the pixel further includes a driving transistor connected to the anode electrode (see Fig. 18, col. 11 lines 44-52. The pixel circuit may include a driving transistor T3), and a data supply transistor that is configured to supply a data voltage to the driving transistor (see Fig. 18. col. 11 lines 44-67. data writing module 91 may include a second transistor T2. The electrodes of the second transistor T2 in the data writing module 91 may be respectively connected to the data line Data and the second node N2).
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Regarding Claim 4, Zhang teaches the display apparatus of claim 1.
Zhang further teaches wherein the dummy line includes a first dummy line extending in a first direction, and a second dummy line extending in a second direction overlapping the first direction, and the anode reset line is electrically connected to the second dummy line (see Fig. 6, fourth metal layer M4, Fig. 31, the first virtual line segment L01, and the second virtual line segment L02, col. 11 lines 8-13, col. 12 lines 22-31, col. 21, lines 51-67, col. 22 lines 1-5, col. 23 lines 57-67, col. 24 lines 1-43. FIG. 28 illustrates a technical solution in which the first connecting line segment L1, the second connecting line segment L2, the first virtual line segment L01, and the second virtual line segment L02 are arranged on the same layer. In this embodiment, these line segments are arranged on the fourth metal layer M4. The at least one first virtual line segment L01 and at least one second virtual line segment L02 may also be connected to a power signal line PVDD or a reset signal line Vref. FIG. 31 is a schematic connection diagram between a first virtual line segment and a second virtual line segment and a fixed voltage line. At least one first virtual line segment L01 may be electrically connected to a first fixed voltage line X1; and/or, at least one second virtual line segment may be electrically connected to a second fixed voltage line X2. The first fixed voltage line X1 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above, and the second fixed voltage line X2 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above).
Regarding Claim 14, Zhang teaches a display apparatus (see abstract. Display panel) comprising:
a substrate (see Fig. 6, substrate 00, col. 6 lines 11-33, col. 7 lines 42-54. The display panel may include a substrate, and other film layer structures of the display panel may be formed on at least one side of the substrate) including a display area (see Figs. 2-3, col. 5 lines 15-46, the display panel 100 includes a display area AA) and an adjacent non-display area (see Figs. 2-3, col. 5 lines 15-46. A non-display area NA at least partially surrounding the display area AA), the display area having a pixel (see Fig. 9, pixel circuit 60, first display area AA1, second display area AA2, Fig. 18, col. 10 lines 51-67, col. 11 lines 1-43. It should be noted that FIG. 9 only illustrates the pixel circuit 60 in the display panel in the form of a rectangular box, and for the layout and circuit structure of the pixel circuit 60 reference can be made to FIG. 10 and FIG. 18 respectively) including an anode electrode (see Fig. 18, anode of a light-emitting element D0, col. 10 lines 31-50, col. 10 lines 63-67, col. 12 lines 6-10. In the embodiment shown in FIG. 9, reference can be made to FIG. 10 for the layout of the area where each pixel circuit 60 is located, and reference can be made to FIG. 18 for the specific composition of each pixel circuit 60. The electrodes of the seventh transistor T7 in the second reset module 95 may be respectively connected to the reset signal line Vref and a fourth node N4, and the fourth node N4 may be connected to the anode of a light-emitting element D0);
a first conductive layer including an anode reset line that is configured to reset the anode electrode (see Fig. 6, Fig. 18, col. 11 lines 8-13, col. 12 lines 5-10, col. 23 lines 65-67. The reset signal line Vref may be located on the capacitor metal layer MC. The electrodes of the seventh transistor T7 in the second reset module 95 may be respectively connected to the reset signal line Vref and a fourth node N4, and the fourth node N4 may be connected to the anode of a light-emitting element D0. The reset signal line Vref may be used to transmit reset signals); and
a second conductive layer on the first conductive layer and including a vertical dummy line electrically connected to the anode reset line (see Fig. 6, fourth metal layer M4, Fig. 31, L01, col. 11 lines 8-13, col. 21, lines 51-67, col. 22 lines 1-5, col. 23 lines 57-67, col. 24 lines 1-43. The connecting line L0 may be located on the fourth metal layer M4. FIG. 28 illustrates a technical solution in which the first connecting line segment L1, the second connecting line segment L2, the first virtual line segment L01, and the second virtual line segment L02 are arranged on the same layer. In this embodiment, these line segments are arranged on the fourth metal layer M4. The at least one first virtual line segment L01 and at least one second virtual line segment L02 may also be connected to a power signal line PVDD or a reset signal line Vref. FIG. 31 is a schematic connection diagram between a first virtual line segment and a second virtual line segment and a fixed voltage line. At least one first virtual line segment L01 may be electrically connected to a first fixed voltage line X1; and/or, at least one second virtual line segment may be electrically connected to a second fixed voltage line X2. The first fixed voltage line X1 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above, and the second fixed voltage line X2 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above).
Regarding Claim 18, Zhang teaches the display apparatus of claim 14.
Zhang further teaches wherein the pixel further includes a driving transistor connected to the anode electrode (see Fig. 18, col. 11 lines 44-52. The pixel circuit may include a driving transistor T3), a data supply transistor that supplies a data voltage to the driving transistor (see Fig. 18. col. 11 lines 44-67. data writing module 91 may include a second transistor T2. The electrodes of the second transistor T2 in the data writing module 91 may be respectively connected to the data line Data and the second node N2), and a connection electrode configured to connect the driving transistor to the anode electrode (see Fig. 18, col. 11 lines 11-67, col. 12 lines 1-14. the second electrode of the driving transistor T3 may be connected to a third node N3).
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Regarding Claim 21, Zhang teaches the display apparatus of claim 14.
Zhang further teaches wherein the electrical connection between the anode reset line and the vertical dummy line, in operation, reduces a ripple of an anode reset voltage applied to the anode electrode (see col. 12 lines 22-31, col. 24 lines 11-43. at least part of the first virtual line segment L01 extending along the first direction D1 and at least part of the second virtual line segment L02 extending along the second direction D2 may be electrically connected to the power signal line PVEE. In this way, it is equivalent to connecting the impedance of the power signal line PVEE in parallel, which is beneficial to reducing the overall impedance of the power signal line PVEE and improving the uniformity of the signal transmitted by the power signal line PVEE. It should be noted that FIG. 31 only illustrate the embodiment in which part of the first virtual line segment L01 and part of the second virtual line segment L02 are connected to the power signal line PVEE as an example for illustration. In some other embodiments of the present disclosure, the at least one first virtual line segment L01 and at least one second virtual line segment L02 may also be connected to a power signal line PVDD or a reset signal line Vref, which is not limited in the embodiments of the present disclosure. Note: Wherein when the at least one first virtual line segment L01 and at least one second virtual line segment L02 is connected to the reset signal line Vref, it reduces the overall impedance of the Vref line thus improving the uniformity of the signal transmitted by the Vref line as well as reducing ripple in the anode reset voltage during switching of the initialization transistor).
Regarding Claim 22, Zhang teaches a display apparatus (see abstract. Display panel) comprising:
a substrate (see Fig. 6, substrate 00, col. 6 lines 11-33, col. 7 lines 42-54. The display panel may include a substrate, and other film layer structures of the display panel may be formed on at least one side of the substrate) including a display area (see Figs. 2-3, col. 5 lines 15-46, the display panel 100 includes a display area AA) and a non-display area adjacent to the display area (see Figs. 2-3, col. 5 lines 15-46. A non-display area NA at least partially surrounding the display area AA);
a pixel including a light-emitting element (see Fig. 9, pixel circuit 60, first display area AA1, second display area AA2, Fig. 18, a light-emitting element D0, col. 10 lines 51-67, col. 11 lines 1-43. It should be noted that FIG. 9 only illustrates the pixel circuit 60 in the display panel in the form of a rectangular box, and for the layout and circuit structure of the pixel circuit 60 reference can be made to FIG. 10 and FIG. 18 respectively) including:
an anode electrode (see Fig. 18, anode of a light-emitting element D0, Fig. 6, col. 7 lines 49-54, col. 10 lines 31-50, col. 10 lines 63-67, col. 12 lines 6-10. The basic structure of the light-emitting layer of the OLED display panel generally include an anode RE In the embodiment shown in FIG. 9, reference can be made to FIG. 10 for the layout of the area where each pixel circuit 60 is located, and reference can be made to FIG. 18 for the specific composition of each pixel circuit 60. The electrodes of the seventh transistor T7 in the second reset module 95 may be respectively connected to the reset signal line Vref and a fourth node N4, and the fourth node N4 may be connected to the anode of a light-emitting element D0),
a cathode electrode (see Fig. 18, cathode of a light-emitting element D0, Fig. 6, col. 7 lines 49-54. The basic structure of the light-emitting layer of the OLED display panel generally include an anode RE, a light-emitting material layer 201, and a cathode 202), and
an organic layer between the anode electrode and the cathode electrode (see Fig. 6, Fig. 18, col. 7 lines 42-62. A display panel using organic light-emitting diode display technology, that is, an OLED display panel. The array layer 10 may include a plurality of transistors TO, and the basic structure of the light-emitting layer of the OLED display panel generally include an anode RE, a light-emitting material layer 201, and a cathode 202);
an anode reset line configured to reset the anode electrode (see Fig. 6, Fig. 18, col. 11 lines 8-13, col. 12 lines 5-10, col. 12 lines 22-31, col. 23 lines 65-67. The reset signal line Vref may be located on the capacitor metal layer MC. The electrodes of the seventh transistor T7 in the second reset module 95 may be respectively connected to the reset signal line Vref and a fourth node N4, and the fourth node N4 may be connected to the anode of a light-emitting element D0. The reset signal line Vref may be used to transmit reset signals. In the data writing stage t2, the second scan line Scan2 may be configured to provide a low-level signal to the second transistor T2, the fourth transistor T4, and the seventh transistor T7 to turn on the transistor T2, the fourth transistor T4, and the seventh transistor T7, the data signal may be written to the gate of the driving transistor T3 (or it can be referred to as the threshold grabbing of the driving transistor T3), and the reset signal may be sent to the fourth node N4 to reset the anode of the light-emitting element D0); and
a dummy line extending into the display area, the dummy line configured to connect to the anode reset line, wherein the anode electrode, in operation, receives an anode reset voltage via the dummy line (see Fig. 6, fourth metal layer M4, Fig. 31, L01, col. 11 lines 8-13, col. 12 lines 22-31, col. 21, lines 51-67, col. 22 lines 1-5, col. 23 lines 57-67, col. 24 lines 1-43. The connecting line L0 may be located on the fourth metal layer M4. FIG. 28 illustrates a technical solution in which the first connecting line segment L1, the second connecting line segment L2, the first virtual line segment L01, and the second virtual line segment L02 are arranged on the same layer. In this embodiment, these line segments are arranged on the fourth metal layer M4. The at least one first virtual line segment L01 and at least one second virtual line segment L02 may also be connected to a power signal line PVDD or a reset signal line Vref. FIG. 31 is a schematic connection diagram between a first virtual line segment and a second virtual line segment and a fixed voltage line. At least one first virtual line segment L01 may be electrically connected to a first fixed voltage line X1; and/or, at least one second virtual line segment may be electrically connected to a second fixed voltage line X2. The first fixed voltage line X1 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above, and the second fixed voltage line X2 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above).
Regarding Claim 25, Zhang teaches he display apparatus of claim 22.
Zhang further teaches wherein the anode reset line (see Fig. 6, Fig. 18, col. 11 lines 8-13, col. 12 lines 5-10, col. 23 lines 65-67. The reset signal line Vref may be located on the capacitor metal layer MC) is on a different layer than the dummy line (see Fig. 6, fourth metal layer M4, Fig. 31, L01, col. 11 lines 8-13, col. 21, lines 51-67, col. 22 lines 1-5, col. 23 lines 57-67, col. 24 lines 1-43. The connecting line L0 may be located on the fourth metal layer M4. FIG. 28 illustrates a technical solution in which the first connecting line segment L1, the second connecting line segment L2, the first virtual line segment L01, and the second virtual line segment L02 are arranged on the same layer. In this embodiment, these line segments are arranged on the fourth metal layer M4. The at least one first virtual line segment L01 and at least one second virtual line segment L02 may also be connected to a power signal line PVDD or a reset signal line Vref. FIG. 31 is a schematic connection diagram between a first virtual line segment and a second virtual line segment and a fixed voltage line. At least one first virtual line segment L01 may be electrically connected to a first fixed voltage line X1; and/or, at least one second virtual line segment may be electrically connected to a second fixed voltage line X2. The first fixed voltage line X1 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above, and the second fixed voltage line X2 may be at least one of the power signal line PVDD, the power signal line PVEE, and the reset signal line Vref described above).
Regarding Claim 27, Zhang teaches the display apparatus of claim 22.
Zhang further teaches further comprising an initialization transistor configured to connect the anode electrode to the anode reset line (see Fig. 18, second reset module 95, col. 11 lines 44-67, col. 12 lines 1-31. The second reset module 95 may include a seventh transistor T7. The electrodes of the seventh transistor T7 in the second reset module 95 may be respectively connected to the reset signal line Vref and a fourth node N4, and the fourth node N4 may be connected to the anode of a light-emitting element D0. In the data writing stage t2, the second scan line Scan2 may be configured to provide a low-level signal to the second transistor T2, the fourth transistor T4, and the seventh transistor T7 to turn on the transistor T2, the fourth transistor T4, and the seventh transistor T7, the data signal may be written to the gate of the driving transistor T3 (or it can be referred to as the threshold grabbing of the driving transistor T3), and the reset signal may be sent to the fourth node N4 to reset the anode of the light-emitting element D0), wherein an electrical connection between the anode reset line and the dummy line, in operation, reduces resistance of the anode reset line and reduces ripple in the anode reset voltage during switching of the initialization transistor (see col. 12 lines 22-31,col. 24 lines 11-43. At least part of the first virtual line segment L01 extending along the first direction D1 and at least part of the second virtual line segment L02 extending along the second direction D2 may be electrically connected to the power signal line PVEE. In this way, it is equivalent to connecting the impedance of the power signal line PVEE in parallel, which is beneficial to reducing the overall impedance of the power signal line PVEE and improving the uniformity of the signal transmitted by the power signal line PVEE. It should be noted that FIG. 31 only illustrate the embodiment in which part of the first virtual line segment L01 and part of the second virtual line segment L02 are connected to the power signal line PVEE as an example for illustration. In some other embodiments of the present disclosure, the at least one first virtual line segment L01 and at least one second virtual line segment L02 may also be connected to a power signal line PVDD or a reset signal line Vref, which is not limited in the embodiments of the present disclosure. Note: Wherein when the at least one first virtual line segment L01 and at least one second virtual line segment L02 is connected to the reset signal line Vref, it reduces the overall impedance of the Vref line thus improving the uniformity of the signal transmitted by the Vref line as well as reducing ripple in the anode reset voltage during switching of the initialization transistor).
Regarding Claim 31, Zhang teaches the display apparatus of claim 22.
Zhang further teaches a data line (see Fig. 6, Fig. 18, col. 25 lines 49-54, the data lines Data in the first display area AA1 and the data lines Data in the second display area AA2 may be located in the same layer, such as the third metal layer M3); and a connection line (see col. 21 lines 65-67, col. 22 lines 1-5, col. 26 lines 4-11. The first connecting line segment L1, the second connecting line segment L2, the first virtual line segment L01, and the second virtual line segment L02 are arranged on the same layer. The second connecting line segment L2 and the first connecting line segment L1 may both be arranged on the third metal layer M3); wherein the dummy line is on a same layer as either the data line or the connection line (see col. 21 lines 65-67, col. 22 lines 1-5, col. 25 lines 49-54, col. 26 lines 4-11. The data lines Data in the first display area AA1 and the data lines Data in the second display area AA2 may be located in the same layer, such as the third metal layer M3. The first connecting line segment L1, the second connecting line segment L2, the first virtual line segment L01, and the second virtual line segment L02 are arranged on the same layer. The second connecting line segment L2 and the first connecting line segment L1 may both be arranged on the third metal layer M3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 11910678 B1) in view of Heo et al. (US 20260011174 A1, hereinafter referenced as Heo).
Regarding Claim 10, Zhang teaches the display apparatus of claim 3.
Zhang does not explicitly disclose wherein one of the initialization transistor, the driving transistor, and the data supply transistor is a polycrystalline thin film transistor, and another one is an oxide thin film transistor.
However, Heo teaches wherein one of the initialization transistor, the driving transistor, and the data supply transistor is a polycrystalline thin film transistor, and another one is an oxide thin film transistor (see Fig. 5, para. [0101] The third and fourth transistors T3 and T4 among the first to seventh transistors T1 to T7 may be N-type transistors that use an oxide semiconductor as a semiconductor layer. Each of the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be P-type transistors that have a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present disclosure is not limited thereto. In an embodiment, all the first to seventh transistors T1 to T7 are P-type transistors. In an embodiment, all the first to seventh transistors T1 to T7 are N-type transistors. In an embodiment, at least one of the first to seventh transistors T1 to T7 is an N-type transistor and the others thereof are P-type transistors. A configuration of the pixel driving circuit PDC according to an embodiment of the present disclosure is not limited to an embodiment illustrated in FIG. 5. The pixel driving circuit PDC illustrated in FIG. 5 is only an example. For example, the configuration of the pixel driving circuit PDC may be variously modified and implemented).
Zhang and Heo are related to display devices and pixel circuits, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display apparatus disclosed by Zhang with Heo’s teachings of providing one of the initialization transistor, the driving transistor, and the data supply transistor is a polycrystalline thin film transistor, and another one is an oxide thin film transistor, since it would have been obvious to try from a finite number of transistors options known in the art that would have yield the same predictable result of providing a switching element in the pixel circuit. Moreover, the advantages of providing a pixel circuit with low temperature poly-silicon thin film transistor and an oxide thin film transistor is that low-frequency drive can be realized, power consumption can be reduced, and display quality can be improved.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 11910678 B1) in view of Yang et al. (US 20250081764 A1, hereinafter referenced as Yang).
Regarding Claim 11, Zhang teaches the display apparatus of claim 3.
Zhang does not explicitly disclose wherein all of the initialization transistor, the driving transistor, and the data supply transistor are oxide thin film transistors.
However, Yang teaches wherein all of the initialization transistor (see Fig. 4B, para. [0135]-[0136]. The pixel drive circuit provided in FIG. 4B further includes the seventh transistor T7 is turned on, the first electrode of the light emitting device L is reset, and the original charges in the first electrode of the light emitting device L are cleared. When the seventh transistor is electrically connected to the scan signal line, the first stage further includes that the seventh transistor T7 is turned on, the first electrode of the light emitting device L is reset, and the original charges in the first electrode of the light emitting device L are cleared), the driving transistor (see Fig. 4B, T3, para. [0121]. the third transistor T3 may be referred to as a drive transistor), and the data supply transistor (see Fig. 4B, para. [0116], para. [0119]-[0120]. a first electrode of the fourth transistor T4 is electrically connected to the data signal line Data) are oxide thin film transistors (see para. [0126] In an exemplary implementation, all the transistors in the pixel drive circuit may be low temperature poly silicon thin film transistors, or may be oxide thin film transistors, or may be low temperature poly silicon thin film transistors and oxide thin film transistors. The oxide thin film transistor has advantages such as low drain current)
Zhang and Yang are related to display devices and pixel circuits, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display apparatus disclosed by Zhang with Yang’s teachings of all of the initialization transistor, the driving transistor, and the data supply transistor are oxide thin film transistors, since having oxide thin film transistor has advantages such as low drain current (Yang para. [0126]). Moreover, oxide transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 11910678 B1, hereinafter referenced as Zhang) in view of Chen (US 20250087164 A1).
Regarding Claim 26, Zhang teaches the display apparatus of claim 22.
Zhang does not explicitly disclose wherein the anode reset line is configured to receive the anode reset voltage during a hold period of a Variable Refresh Rate (VRR) driving mode.
However, Chen teaches wherein the anode reset line is configured to receive the anode reset voltage during a hold period of a Variable Refresh Rate (VRR) driving mode (see FIG. 4A, and FIG. 5A, para. [0073] Optionally, the display device may display with a variable refresh rate. Correspondingly, when the display panel is displaying, it includes writing frames WF and holding frames HF. Herein, the writing frame WF may include the first phase t1 to the fourth phase t4. In the holding frame HF, the first scanning signal Scan1 output by the first gate driving circuit 101 has a high level state and a low level state, the second scanning signal Scan2 output by the second gate driving circuit 201 has a high level state and a low level state, and the scanning signal Pscan output by the sixth gate driving unit 60 has a low level state. A fifth phase t5 is included in the holding frame HF to reset the third node N3 of the subpixels Pi of the corresponding row and apply a bias voltage to the second node N2. For example, in the fifth phase t5, the X-th level first scanning signal Scan1(X) output by the first gate driving circuit 101 of the X-th cascade is at a high level, so that the light emission control transistors of the subpixels Pi located in the m-th row to the (m+3)th row are turned off; and the X-th level second scanning signal Scan2(X) output by the second gate driving circuit 201 of the X-th cascade is at a low level, the second reset transistors Ti2 and the third reset transistors Ti3 of the subpixels Pi located in the m-th row to the (m+3)th row are turned on, the second reset signal transmitted by the second reset line ViL2 resets the third node N3, and the third reset signal transmitted by the third reset line ViL3 applies a bias voltage to the second node N2, thereby relieving the hysteresis effect of the drive transistors Tdr and relieving the flicker).
Zhang and Chen are related to display devices, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display device with Chen’s teachings of receiving the anode reset voltage during a hold period of a Variable Refresh Rate (VRR) driving mode, since it would have relieved the hysteresis effect of the drive transistors and relieving the flicker (Chen, para. [0073])
Additional Rejection
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Gu et al. (US 20230178704 A1, herein after referenced as Gu).
Regarding Claim 1, Gu teaches a display apparatus (see abstract, para. [0006]. Display panel and display apparatus) comprising:
a display area on which an image is displayed (see Fig. 1, para. [0030]-[0032] . As shown in FIG. 1, the display panel includes a display region AA. Multiple pixels (such as light-emitting elements) are arranged in the display region AA. Inherently the display region will display images);
a non-display area adjacent to the display area (see Fig. 1, para. [0031]. The display region AA surrounds the through-hole non-display region NAK);
a pixel in the display area (see Fig. 3, para. [0032], para. [0043]-[0044], . Multiple pixels (such as light-emitting elements) are arranged in the display region AA), the pixel including an anode electrode (see Fig. 3, light-emitting element P (LED) inherently has an anode electrode (first electrode) and a cathode electrode (second electrode));
an anode reset line configured to reset the anode electrode (see Fig. 3, Ref line, para. [0044]. A first electrode of the electrode reset transistor T2 receives the reset signal Ref, a second electrode of the electrode reset transistor T2 is connected to the first electrode of the light-emitting element P).
In another embodiment, Gu teaches a dummy line disposed in the display area, wherein the anode reset line is electrically connected to the dummy line (see para. [0063]-[0066], Fig. 7. In some embodiments, as shown in FIG. 7, the display region AA includes dummy lines 60. The dummy lines 60 include a first dummy line 61 and a second dummy line 62. The first dummy line 61 has a same extending direction as the first connection segment 11a, and the second dummy line 62 has a same extending direction as the second connection segment 11b. The dummy line 60 is connected to the reset signal line, and the dummy line 60 transmits a reset signal).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display apparatus disclosed by Gu with Gu’s teachings, in another embodiment, of providing dummy lines, since the dummy line can balance the difference in the metal-line density at different positions in the display region AA, reduce the difference in reflectivity at different positions in the display region AA, thereby improving the display effect (Gu, para. [0063]).
Moreover, combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness.” Boston Scientific Scimed, Inc. v. Cordis Corp., 554 F.3d 982, 991 (Fed. Cir. 2009).
Regarding Claim 4, Gu teaches the display apparatus of claim 1.
Gu further teaches wherein the dummy line includes a first dummy line extending in a first direction (see Fig. 7, para. [0063]. The dummy lines 60 include a first dummy line 61. The first dummy line 61 has a same extending direction as the first connection segment 11a), and a second dummy line extending in a second direction overlapping the first direction (see Fig. 7, para. [0063]. The dummy lines 60 include a second dummy line 62. The second dummy line 62 has a same extending direction as the second connection segment 11b), and the anode reset line is electrically connected to the second dummy line (see Fig. 7, para. [0066]. The dummy line 60 is connected to the reset signal line, and the dummy line 60 transmits a reset signal).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display apparatus disclosed by Gu with Gu’s teachings, in another embodiment, of providing dummy lines, since the dummy line can balance the difference in the metal-line density at different positions in the display region AA, reduce the difference in reflectivity at different positions in the display region AA, thereby improving the display effect (Gu, para. [0063]).
Moreover, combining two embodiments disclosed adjacent to each other in a prior art patent does not require a leap of inventiveness.” Boston Scientific Scimed, Inc. v. Cordis Corp., 554 F.3d 982, 991 (Fed. Cir. 2009).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Gu (US 20230178704 A1) in view of Zhang (US 11910678 B1).
Regarding Claim 2, Gu teaches the display apparatus of claim 1.
Gu further teaches wherein the pixel further includes a light-emitting element including the anode electrode (see Fig. 3, para. [0044]. First electrode of a light-emitting element P) and a cathode electrode (see Fig. 3, para. [0044]. Asecond electrode of the light-emitting element P receive the negative power supply signal Pvee), and an initialization transistor configured to connect the anode electrode to the anode reset line (see Fig. 3, reset transistor T2, para. [0044]. A first electrode of the electrode reset transistor T2 receives the reset signal Ref, a second electrode of the electrode reset transistor T2 is connected to the first electrode of the light-emitting element P).
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Gu does not explicitly disclose the light-emitting element includes an organic layer.
However, Zhang teaches the light-emitting element includes an organic layer (see Fig. 6, Fig. 18, col. 7 lines 42-62. A display panel using organic light-emitting diode display technology, that is, an OLED display panel. The array layer 10 may include a plurality of transistors TO, and the basic structure of the light-emitting layer of the OLED display panel generally include an anode RE, a light-emitting material layer 201, and a cathode 202).
Gu and Zhang are related to display devices, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of substituting the light emitting element disclosed by Gu with Zhang’s organic light emitting diode, since is just a simple substitution of known element the would have yield the same predictable result of emitting display light.
Regarding Claim 3, Gu and Zhang teaches the display apparatus of claim 2.
Gu further teaches wherein the pixel further includes a driving transistor connected to the anode electrode (see Fig. 3, para. [0044]. As shown in FIG. 3, the pixel circuit includes a driving transistor Tm. The driving transistor Tm is connected in series between the first emission control transistor T5 and the second emission control transistor T6. A second electrode of the second emission control transistor T6 is connected to a first electrode of a light-emitting element P), and a data supply transistor that is configured to supply a data voltage to the driving transistor (see Fig. 3, para. [0044]. A first electrode of the data writing transistor T3 receives a data signal Vdata, and a second electrode of the data writing transistor T3 is connected to the first electrode of the driving transistor Tm).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gu (US 20230178704 A1) in view of Heo (US 20260011174 A1).
Regarding Claim 10, Gu teaches the display apparatus of claim 3.
Gu does not explicitly disclose wherein one of the initialization transistor, the driving transistor, and the data supply transistor is a polycrystalline thin film transistor, and another one is an oxide thin film transistor.
However, Heo teaches wherein one of the initialization transistor, the driving transistor, and the data supply transistor is a polycrystalline thin film transistor, and another one is an oxide thin film transistor (see Fig. 5, para. [0101] The third and fourth transistors T3 and T4 among the first to seventh transistors T1 to T7 may be N-type transistors that use an oxide semiconductor as a semiconductor layer. Each of the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be P-type transistors that have a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present disclosure is not limited thereto. In an embodiment, all the first to seventh transistors T1 to T7 are P-type transistors. In an embodiment, all the first to seventh transistors T1 to T7 are N-type transistors. In an embodiment, at least one of the first to seventh transistors T1 to T7 is an N-type transistor and the others thereof are P-type transistors. A configuration of the pixel driving circuit PDC according to an embodiment of the present disclosure is not limited to an embodiment illustrated in FIG. 5. The pixel driving circuit PDC illustrated in FIG. 5 is only an example. For example, the configuration of the pixel driving circuit PDC may be variously modified and implemented).
Gu and Heo are related to display devices and pixel circuits, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display apparatus disclosed by Gu with Heo’s teachings of providing one of the initialization transistor, the driving transistor, and the data supply transistor is a polycrystalline thin film transistor, and another one is an oxide thin film transistor, since it would have been obvious to try from a finite number of transistors options known in the art that would have yield the same predictable result of providing a switching element in the pixel circuit. Moreover, the advantages of providing a pixel circuit with low temperature poly-silicon thin film transistor and an oxide thin film transistor is that low-frequency drive can be realized, power consumption can be reduced, and display quality can be improved.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gu (US 20230178704 A1) in view of Yang (US 20250081764 A1).
Regarding Claim 11, Gu teaches the display apparatus of claim 3.
Gu does not explicitly disclose wherein all of the initialization transistor, the driving transistor, and the data supply transistor are oxide thin film transistors.
However, Yang teaches wherein all of the initialization transistor (see Fig. 4B, para. [0135]-[0136]. The pixel drive circuit provided in FIG. 4B further includes the seventh transistor T7 is turned on, the first electrode of the light emitting device L is reset, and the original charges in the first electrode of the light emitting device L are cleared. When the seventh transistor is electrically connected to the scan signal line, the first stage further includes that the seventh transistor T7 is turned on, the first electrode of the light emitting device L is reset, and the original charges in the first electrode of the light emitting device L are cleared), the driving transistor (see Fig. 4B, T3, para. [0121]. the third transistor T3 may be referred to as a drive transistor), and the data supply transistor (see Fig. 4B, para. [0116], para. [0119]-[0120]. a first electrode of the fourth transistor T4 is electrically connected to the data signal line Data) are oxide thin film transistors (see para. [0126] In an exemplary implementation, all the transistors in the pixel drive circuit may be low temperature poly silicon thin film transistors, or may be oxide thin film transistors, or may be low temperature poly silicon thin film transistors and oxide thin film transistors. The oxide thin film transistor has advantages such as low drain current)
Gu and Yang are related to display devices and pixel circuits, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display apparatus disclosed by Gu with Yang’s teachings of all of the initialization transistor, the driving transistor, and the data supply transistor are oxide thin film transistors, since having oxide thin film transistor has advantages such as low drain current (Yang para. [0126]). Moreover, oxide transistors can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.
Allowable Subject Matter
Claims 5-6, 8-9, 12-13, 15-17, 19-20, and 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 would be allowable if rewritten to overcome the objections set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/IM/Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 8/28/26
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