DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2-4, 8-18 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (USPN 7,936,196).
With respect to claim 1, Kim et al. discloses, in Figs. 4-5 and 7, a delay lock loop circuit (Fig. 4 further details disclosed in Figs. 5 and 7), comprising:
a variable delay component (210 with 220) configured to receive a first clock signal at an input terminal (EXCLK via 210) and generate a second clock signal comprising a first delay relative to the first clock signal (DCLK);
a delay component coupled with the variable delay component and configured to receive the second clock signal (280 receiving DCLK) and generate a third clock signal (output of 280) comprising the first delay relative to the first clock signal (EXCLK and delays of 210 with 220 and 280) and a second delay relative to the second clock signal (DCLK and delay of 280);
a control component coupled with the delay component (240) and configured to receive the third clock signal (output of 280 input to 240) and generate a feedback signal (output of 240, i.e., RCLK/RCLKB) by modifying the third clock signal (inverting adding delay of 241/bypassing the output of 280); and
a phase detector (230) coupled with the control component (output of 240) and configured to determine whether the feedback signal is aligned with the first clock signal and output an indication of the alignment (PS and/or output to 290), wherein the variable delay component is further configured to adjust the second clock signal based at least in part on receiving the indication of the alignment (delay of 220 under control of 230 and 290).
With respect to claim 2, the delay lock loop circuit of claim 1, wherein, to modify the third clock signal, the control component is further configured to:
restrict the first delay by preventing the third clock signal from satisfying a threshold associated with a misalignment between the feedback signal and the first clock signal (240 restricts the first delay by preventing the output of 240 from satisfying a threshold associated with the window, timing of the rising edge, of the feedback signal RCLK/RCLKB from being misaligned with the rising edge of the external clock, i.e. prevents the misaligned signal being input to 230, see Col. 12 lines 25-34).
With respect to claim 3, the delay lock loop circuit of claim2,wherein, to restrict the first delay, the control component is further configured to: restrict a magnitude of increasing the first delay from exceeding a second threshold (240 restricts the magnitude of increasing the first delay by removing the additional inverter 241, which has an additional delay associated with the inverter. Thus the removing the delay of 241 causes the delay magnitude of 220 to decrease to match the feedback signal, i.e., restricts an increase, according to the second threshold of the removed delay of 241. Furthermore, there is no explicit definition in the claims, or the in the instant specification as to what the “second threshold” refers to and how it differs from other thresholds).
With respect to claim 4, the delay lock loop circuit of claim 2, wherein, to restrict the first delay, the control component is further configured to: restrict a magnitude of decreasing the first delay from satisfying a second threshold (240 restricts the magnitude of decreasing the first delay by adding an additional inverter 241, which causes an additional delay associated with the inverter, and thus requires the delay magnitude of 220 to increase, i.e., restricts a decrease, according to the second threshold of the added delay. Furthermore, there is no explicit definition in the claims, or the in the instant specification as to what the “second threshold” refers to and how it differs from other thresholds).
With respect to claim 8, the delay lock loop circuit of The delay lock loop circuit of wherein modifying the third clock signal by the control component is based at least in part on the phase detector outputting the indication (260 which controls CONT,SW2 of 240 is directly controlled by PS and indirectly controlled by 230 via 290 and 220).
With respect to claim 9, Kim discloses, in Figs. 4-5 and 7, a method by a delay lock loop circuit (method of operating Fig. 4 further details disclosed in Figs. 5 and 7), comprising:
receiving a first clock signal at a variable delay component (delay of 210 with 220 receive EXCLK) and outputting a second clock signal comprising a first delay relative to the first clock signal (DCLK having the delay of 210 with 220);
receiving the second clock signal at a delay component coupled with the variable delay component (DCLK received by 280) and generating a third clock signal (output of 280) comprising the first delay relative to the first clock signal (delay of 210, 220 and 28) and a second delay relative to the second clock signal (delay of 280);
receiving the third clock signal at a control component coupled with the delay component (240 receiving the output of 280) and generating a feedback signal (output of 240, e.g., RCLK/RCKLB) by modifying the third clock signal (switching between the delay/inversion of 241 and bypassing the delay);
determining, by a phase detector coupled with the control component, whether the feedback signal is aligned with the first clock signal and outputting an indication of the alignment (230 generating the output to 290/220 and/or PS according the determination whether EXCLK and RCLK/RCLKB are aligned); and
adjusting, by the variable delay component, the second clock signal based at least in part on receiving the indication of the alignment (220 is controlled according to the output of 230).
With respect to claim 10, the method of claim 9, wherein modifying the third clock signal comprises: restricting the first delay by preventing the third clock signal from satisfying a threshold associated with a misalignment between the feedback signal and the first clock signal (240 restricts the first delay by preventing the output of 240 from satisfying a threshold associated with the window, timing of the rising edge, of the feedback signal RCLK/RCLKB from being misaligned with the rising edge of the external clock, i.e. prevents the misaligned signal being input to 230, see Col. 12 lines 25-34).
With respect to claim 11, the method of claim 10, wherein modifying the third clock signal comprises: increasing the first delay by a magnitude based at least in part on determining that the feedback signal is behind the first clock signal (when it is determined that RCLK is behind ECLK 240 changes to the RCLKB, see Col. 12 lines 25-34, and thus increases the first delay by at least the delay provided by the inversion of 241. Furthermore, when the feedback clock is behind ECLK 220 is controlled to increase its delay time)
With respect to claim 12, the method of claim 11, wherein modifying the third clock signal comprises: restricting the magnitude of increasing the first delay from the first delay exceeding a second threshold (240 restricts the magnitude of increasing the first delay by removing the additional inverter 241, which has an additional delay associated with the inverter. Thus the removing the delay of 241 causes the delay magnitude of 220 to decrease to match the feedback signal, i.e., restricts an increase, according to the second threshold of the removed delay of 241. Furthermore, there is no explicit definition in the claims, or the in the instant specification as to what the “second threshold” refers to and how it differs from other thresholds).
With respect to claim 13, the method of claim 10, wherein modifying the third clock signal comprises: decreasing the first delay by a magnitude based at least in part on determining that the feedback signal is ahead of the first clock signal (when RCLKB is ahead of EXCLK 240 will be changed to bypass 241 thus reducing the feedback by a delay associated with 241. When the feedback is reduced in delay time the delay line will be decreased to match the decreased delay. Furthermore, when EXCLK is behind the feedback clock the delay of 220 is reduced by 230 and 290).
With respect to claim 14, the method of claim 13, wherein modifying the third clock signal comprises: restricting the magnitude of decreasing the first delay from the first delay satisfying a second threshold (240 restricts the magnitude of decreasing the first delay by adding an additional inverter 241, which causes an additional delay associated with the inverter, and thus requires the delay magnitude of 220 to increase, i.e., restricts a decrease, according to the second threshold of the added delay. Furthermore, there is no explicit definition in the claims, or the in the instant specification as to what the “second threshold” refers to and how it differs from other thresholds).
With respect to claim 15, the method of claim 9, wherein modifying the third clock signal is based at least in part on the phase detector outputting the indication to the control component (260 which controls CONT,SW2 of 240 is directly controlled by PS and indirectly controlled by 230 via 290 and 220).
With respect to claim 16, the method of claim 15, wherein the indication comprises a command to increase the first delay or decrease the first delay (the output of 230 controls the increase/decrease of 220).
With respect to claim 17, the method of claim 9, further comprising: determining whether the feedback signal is aligned with the first clock signal based at least in part on modifying the third clock signal (the detection provided by 230 is determined by the adjusting of the feedback clock provided by 240, since PS and 290 with 220 control 260 which controls 240), wherein adjusting the second clock signal is based at least in part on determining that the feedback signal is aligned with the first clock signal (220 is controlled by the determining due to 230 controlling 290 which controls 220).
With respect to claim 18, the method of claim 9, further comprising: determining whether the feedback signal is aligned with the first clock signal based at least in part on modifying the third clock signal (the detection provided by 230 is determined by the adjusting of the feedback clock provided by 240, since PS and 290 with 220 control 260 which controls 240); and remodifying the third clock signal based at least in part on determining that the feedback signal is misaligned with the first clock signal, wherein adjusting the second clock signal is based at least in part on remodifying the third clock signal (when it is determined that the rising edge window of the feedback signal is not closest to the rising edge of the clock the feedback signal is remodified by 240 and the second clock is adjusted by 230, 290 and 220 is modified to cause the signals to become in alignment).
With respect to claim 22, the method of claim 9, wherein the second delay is generated to correspond to an expected delay of a memory device associated with the delay lock loop circuit (the circuit of Fig. 4 is used in a memory device, see Col. 2 lines 33-36. Furthermore the replica delay is set to an expected delay of the memory device until the output of the DLL reaches its final destination and thus replicates the expected delay of the memory device, see Col. 6 lines 35-38).
Claim(s) 1, 5, 9 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Im et al. (USPN 10,291,240).
With respect to claim 1, Im et al. discloses, in Figs. 1-3, a delay lock loop circuit (Fig. 1, details of operation disclosed in Figs. 2-3) circuit, comprising:
a variable delay component (200) configured to receive a first clock signal (REF_CK) at an input terminal (input of 200) and generate a second clock signal comprising a first delay relative to the first clock signal (output of 200 having a delay associated with 200);
a delay component coupled with the variable delay component (230) and configured to receive the second clock signal (output of 200) and generate a third clock signal (output of 240) comprising the first delay relative to the first clock signal (delay of 200 and 230) and a second delay relative to the second clock signal (delay of 230);
a control component coupled with the delay component (240, 250, 260 and 270) and configured to receive the third clock signal (output of 230) of and generate a feedback signal (FB) by modifying the third clock signal (delaying the third clock 240, by CAL of 250 and the delay associated with 270); and
a phase detector coupled with the control component (210) and configured to determine whether the feedback signal is aligned with the first clock signal and output an indication of the alignment (output of 210 generated as claimed), wherein the variable delay component is further configured to adjust the second clock signal based at least in part on receiving the indication of the alignment (under the control of 220 which is generated according, at least in part, to the output of 210).
With respect to claim 5, the delay lock loop circuit of claim 1, wherein the control component is further configured to: receive an indication to enable the control component to generate the feedback signal (SEL), wherein generating the feedback signal is based at least in part on receiving the indication (SEL controls 260 such that 270 generates FB based on 240 and 250, i.e., enables the generating of the feedback signal according to the control component, see operation of Fig. 2. Also see operation of Fig. 3 wherein 240 and 250 is disabled).
With respect to claim 8, the delay lock loop circuit of The delay lock loop circuit of wherein modifying the third clock signal by the control component is based at least in part on the phase detector outputting the indication (CAL to adjust the delay of 250 is generated by 100 which is operative responsive to LOCK generated by 220, wherein 220, and thus LOCK, is under the control of the output of 210).
Claims 9 and 21 are rejected for the same reasons as claims 1 and 5.
Claim(s) 1, 6-9, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma (USPN 7,825,711).
With respect to claim 1, a delay lock loop circuit (Fig. 5), comprising:
a variable delay component (108) configured to receive a first clock signal (CLKS) at an input terminal (input of 108) and generate a second clock signal (output of 108) comprising a first delay relative to the first clock signal (delay of 108);
a delay component coupled with the variable delay component (116 having an inherent delay associated with 116) and configured to receive the second clock signal (at input of 116) and generate a third clock signal (ICLK) comprising the first delay relative to the first clock signal (delay of 108 and 116) and a second delay relative to the second clock signal (delay of 116);
a control component coupled with the delay component and configured to receive the third clock signal (238 with 120) and generate a feedback signal (FBCLK) by modifying the third clock signal (delaying by the controlled delay of 238 and the delay of 120); and
a phase detector coupled with the control component (266) and configured to determine whether the feedback signal is aligned with the first clock signal and output an indication of the alignment (output of 266 operated as claimed), wherein the variable delay component is further configured to adjust the second clock signal based at least in part on receiving the indication of the alignment (via the output of 270 to 108 under the control of 266).
With respect to claim 6, the delay lock loop circuit of claim 1, further comprising: a filter component (270 providing filtering, see Col. 4 lines 17-19 and Col. 6 lines 64-65) coupled with the control component (270 controlling 238) and configured to use a plurality of shift registers (shift registers of the shift logic) to reduce noise in the feedback signal and adjust the second clock signal (the filtering providing by 270 will reduce noise and thus the control signal provided to by 108 and 238 will have a reduced noise and the adjusting of 108 and 238 will allow for a reduced noise associated with the delay of the feedback signal).
With respect to claim 7, the delay lock loop circuit of claim 6, wherein the plurality of shift registers are configured convert analog characteristics of the feedback signal to digital characteristics associated with the second clock signal (shift register converts the analog clock timing of the feedback signal to digital control bits output by 270 to 108 to adjust the delay characteristics of the second clock controlled by 108..
With respect to claim 8, the delay lock loop circuit of The delay lock loop circuit of wherein modifying the third clock signal by the control component is based at least in part on the phase detector outputting the indication (the output of 266 controls 270 which controls 238).
Claims 9, 19 and 20 are rejected for the same reasons as claims 1, 6 and 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2836
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