Prosecution Insights
Last updated: July 17, 2026
Application No. 19/230,255

READ OPERATIONS FOR MIXED DATA

Non-Final OA §112
Filed
Jun 06, 2025
Priority
Aug 29, 2022 — continuation of 12/346,584
Examiner
GIARDINO JR, MARK A
Art Unit
Tech Center
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
573 granted / 676 resolved
+24.8% vs TC avg
Minimal +2% lift
Without
With
+2.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
14 currently pending
Career history
694
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
78.0%
+38.0% vs TC avg
§102
6.7%
-33.3% vs TC avg
§112
8.2%
-31.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 676 resolved cases

Office Action

§112
DETAILED ACTION The instant application having Application No. 19/230,255 has a total of 20 claims pending in the application, there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner. INFORMATION CONCERNING DRAWINGS Drawings The applicant's drawings submitted 6/6/2025 are acceptable for examination purposes. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT Information Disclosure Statement As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 6/6/2025, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action. DOUBLE PATENTING The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over US 12,346,584. Although the conflicting claims are not identical, they are not patentably distinct from each other. Instant Application US 12,346,584 1. A memory device, comprising: a memory; a controller configured to: read, from the memory and based at least in part on a read command, data associated with a plurality of logical block addresses, wherein the plurality of logical block addresses are associated with a plurality of respective memory statuses; and provide, to a hardware component of the memory device, a single data transfer request indicating the plurality of logical block addresses and the plurality of respective memory statuses; and the hardware component configured to: provide, to a host device, a plurality of responses to the read command based at least in part on the single data transfer request. 1. A memory device, comprising: a memory; and one or more components configured to: obtain, from a host device, a read command for reading data associated with a plurality of logical blocks; read, from the memory, the data corresponding to the plurality of logical blocks; encode the data corresponding to the plurality of logical blocks with a plurality of respective status indicators, wherein the plurality of respective status indicators indicate memory statuses of the data stored in the plurality of logical blocks or of a plurality of physical addresses that are associated with the plurality of logical blocks; provide, by a controller of the memory device to a hardware component of the one or more components of the memory device, a single data transfer request indicating the plurality of logical blocks encoded with the plurality of respective status indicators; and provide, by the hardware component and to the host device, a plurality of responses to the read command based on the single data transfer request. This rejection has been made as all limitations of claim 1 of the instant application are present in the claims of US 12,346,584 as shown, and therefore claim 1 of the instant application is anticipated by US 12,346,584. See MPEP 804(II)(B)(2). The other independent claims correspond as follows: Instant Application US 12,346,584 Claim 11 Claim 11 Claim 20 Claim 20 Further, the dependent claims of both cases contain substantially similar limitations. CLAIM INTERPRETATION The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Claim 20 contains a means for reading and two means for providing. The examiner has interpreted the corresponding structure as elements of controller 130 of Fig. 2, based on Paragraphs 0038-0039 of the submitted specification. ALLOWABLE SUBJECT MATTER Regarding Claim 1, Hall (US 2018/0260159) teaches a memory device (shown on Fig. 1), comprising: a memory (storage disks 110 of Fig. 1); a controller (controller 133 of Fig. 1) configured to: read, from the memory and based at least in part on a read command, data associated with a plurality of logical block addresses (read commands are received at step 601 of Fig. 6, which “includes a range of LBAs,” Paragraph 0035). Though not explicitly taught by Hall, it is known in the art wherein a plurality of logical block addresses are associated with a plurality of respective memory statuses. See, for example, Weng et al (US 2004/0158669), Paragraph 0051, where status words such as “successful,” “error,” and “invalid address” are included in a “read” command status packet. However, when combined with the remaining limitations, the cited prior art does not teach or suggest: a controller configured to provide, to a hardware component of the memory device, a single data transfer request indicating the plurality of logical block addresses and the plurality of respective memory statuses; and the hardware component configured to: provide, to a host device, a plurality of responses to the read command based at least in part on the single data transfer request. Therefore, claim 1 contains allowable subject matter. Similarly, regarding Claim 11, when combined with the remaining limitations of the claim, the cited prior art does not teach or suggest: “providing, from a firmware component of the memory device to a hardware component of the memory device, a single data transfer request indicating the plurality of logical block addresses and the plurality of respective memory statuses; and providing, to a host device, a plurality of responses to the read command based at least in part on the single data transfer request” as recited in claim 11, and similarly in claim 20. RELEVANT ART CITED BY THE EXAMINER The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c). The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include: Carlson et al (US 2015/0127882) teaches READ OPERATION PRIOR TO RETRIEVAL OF SCATTER GATHER LIST. CLOSING COMMENTS Conclusion STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i): CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-20 have been rejected. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. /MARK A GIARDINO JR/Primary Examiner, Art Unit 2135
Read full office action

Prosecution Timeline

Jun 06, 2025
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
87%
With Interview (+2.5%)
2y 6m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 676 resolved cases by this examiner. Grant probability derived from career allowance rate.

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