DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because it should avoid using phrases which can be implied, such as “… are disclosed,” “this disclosure concerns,” “the disclosure describes,”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-10, 23-24, 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. (US 20230124193), in view of Panzarella et al. (US 5416776), further in view of Balasubramanian et al. (US 20140211657).
With regards to claim 1, Ito teaches
…, wherein the first card comprises: a first controller configured to receive a first instruction through a first communication network having a first communication protocol (When receiving the control instruction information from the control instructing unit 417 of the control node 413 via the control network 414 (i.e., first communication network having a first communication protocol), the control unit 311 (i.e., first controller) of each of the distributed processing nodes 402-1 to 402-4 secures resources based on the control instruction information; [0140], Ito)
a first processing device coupled to the first controller and configured to generate an operation result based on the first instruction (… The control unit 111 (i.e., first controller) includes a function of constructing a mathematical model in a software manner … allocating a learning job to the computing device 103 (i.e., first processing device), and a function of reading out learning data such as image data from the outside and passing the learning data to the computing device 103; [0049], Ito. Ito further teaches each of the computing devices 103 of the distributed node 102 receives image data of the imagenet via the control unit 111. Each of the computing devices 103 calculates a gradient of a loss function of a model for each of a plurality of weights of a learning target model (a neural network of Resnet50) in the own node and generates, for each of the weights, gradient data obtained by aggregating the gradients for each of image data (i.e., configured to generate an
operation result based on the first instruction); [0052], Ito.),
wherein the first card is configured to provide one or more data packets generated
based on the operation result to the second card through a second communication network
formed by the set of cards … (…the DMA controller 108 DMA-transfers the gradient data calculated by each of the computing devices 103 to a memory 1040 in the interconnect device 104 through the computing function unit 106 of the bus device 105 (i.e., second communication network formed by the set of cards) of the own node; [0054], Ito. Ito further teaches when gradient data is DMA-transferred by the DMA controller 108 of the own node (YES in step S300 in FIG. 4), the interconnect device 104 of the parent node DMA-transfers the gradient data to a child node having the next number (for example, a child node in a clockwise direction) via the transmission line 101A (step S301 in FIG. 4) (i.e., first card providing data to the second card); [0065], Ito. Ito further teaches …A distributed processing system 101 is configured from a plurality of distributed processing nodes 102 and a transmission line 101A connecting the plurality of distributed processing nodes 102 (i.e., second communication network formed by the set of cards); [0038], Ito)
wherein the second communication network has a ring topology (… The distributed processing nodes 102 are connected in a ring shape by the transmission line 101A including an optical fiber; [0042], Ito)
and the second card comprises a second processing device and a second controller configured to receive a second instruction through the first communication network (When receiving the control instruction information from the control instructing unit 417 of the control node 413 via the control network 414 (i.e., first communication network), the control unit 311 of each of the distributed processing nodes 402-1 to 402-4 (i.e., claimed second card) secures resources based on the control instruction information. That is, the control unit 311 allocates a learning job to the computing device 303 (i.e., claimed second processing device) of the own node instructed by the control instruction information; [0140] and Fig. 8, Ito).
Ito does not teach A board, comprising: a set of cards comprising a first card, a second card, and one or more additional cards.
However, in the same field of endeavor Panzarella teaches a board, comprising: a set of cards comprising a first card, a second card, and one or more additional cards (A backplane BP (FIG. 10) is the communications medium which all plug in cards (NACs and NICs) use for communications. The front of the backplane has slots that accept 16 front loading network application cards…; Column 3, line 34-36, Panzarella).
One of ordinary skill in the art would have been motivated to implement Ito’s distributed processing nodes using the multi-card backplane architecture taught by Panzarella to provide a modular hardware arrangement in which individual processing cards can be interconnected and managed separately.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to have combined the teachings of Ito and Panzarella to facilitate expansion, replacement, and centralized management of the individual processing.
Ito in view of Panzarella does not teach a set of cards having a second communication protocol different from the first communication protocol.
However, in the same field of endeavor Balasubramanian teaches a set of cards having a second communication protocol different from the first communication protocol (FIG. 10 illustrates switching system 1000, an exemplary, non-limiting embodiment referred to herein as switch mode 8. Switch mode 8 can be configured such that a frame received on a first network on port 1 (e.g., ENIP 1030) is not forwarded to a backplane connected on port 2 (e.g., NEO 1040), and vice-versa, a frame received on port 2 is not forwarded to port 1. The separation between ENIP 1030 (i.e., first communication network) and NEO 1040 (i.e., a different second communication network) is indicated by the broken line in FIG. 10… [0052], Balasubramanian).
One of ordinary skill in the art would have been motivated to implement teachings of Ito and Panzarella using different communication protocols taught by Balasubramanian for the separate communication networks.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to have combined the teachings of Ito and Panzarella with the teaching of Balasubramanian to enable separate control and data communications to be carried using protocols suited to their respective communication networks, thereby providing improved flexibility in configuring and routing communications between the processing nodes.
With regards to claim 2, Ito teaches through Panzarella and Balasubramanian the board of claim 1, further comprising a third card in addition to the set of cards, wherein
the set of cards form the second communication network without the third card. (A backplane BP (FIG. 10) is the communications medium which all plug in cards (NACs and NICs) use for communications. The front of the backplane has slots that accept 16 front loading network application cards (NACs) and 1 network management card (NMC) 162 (e.g., 105, 107, 123-134, 142 and 162 (FIG. 1))… (i.e., more than two card on the board. Any cards in addition to first and second card corresponds to claimed third card); Column 3, line 34-39, Panzarella).
The same rationale to combine for claim 1 applies.
With regards to claim 4, Ito teaches through Panzarella and Balasubramanian the board of claim 1, wherein the set of cards comprises a left neighbor card coupled to the
first card at one side and a right neighbor card coupled to the first card at another side along the ring topology of the second communication network (The interconnect device 104 of the child node DMA-transfers the gradient data subjected to the addition processing to a node having the next number (for example, a node in the clockwise direction) via the transmission line 101A (step S402 in FIG. 5) (i.e., cards next to each other). The processing in steps S400 to S402 in FIG. 5 is performed in order in the child nodes connected in a ring shape by the transmission line 101A, whereby a result obtained by adding up the gradient data of the distributed processing nodes 102 is obtained. The gradient data for which the addition processing in the distributed processing nodes 102 (figure 1 shows at least three nodes in a ring topology corresponding to the first card with a left neighbor card and a right neighbor card) ends is hereinafter referred to as aggregated data; [0067-0068], Ito).
With regards to claim 6, Ito teaches through Panzarella and Balasubramanian the board of claim 1, wherein the first card further comprises: an input/output (I/O) circuit of the first card coupled to the first processing device and configured to: receive the operation result from the first processing device; and provide the operation result to the second card through the second communication network having the ring topology (A distributed processing node of embodiments of the present invention includes: a plurality of computing devices configured to calculate gradient data of a loss function from an output result obtained by inputting learning data to a learning target model and update parameters of the model based on aggregation data of the gradient data; [0020], Ito. Ito further teaches …the DMA controller 108 DMA-transfers the gradient data calculated by each of the computing devices 103 to a memory 1040 in the interconnect device 104 through the computing function unit 106 of the bus device 105 (i.e., second communication network formed by the set of cards) of the own node; [0054], Ito. Ito further teaches when gradient data is DMA-transferred by the DMA controller 108 of the own node (YES in step S300 in FIG. 4), the interconnect device 104 of the parent node DMA-transfers the gradient data to a child node having the next number (for example, a child node in a clockwise direction) via the transmission line 101A (step S301 in FIG. 4) (i.e., first card providing data to the second card. The bus, DAM controller, and interconnect device together performs claimed I/O function); [0065], Ito. Ito further teaches … The distributed processing nodes 102 are connected in a ring shape by the transmission line 101A including an optical fiber; [0042], Ito).
With regards to claim 7, Ito teaches through Panzarella and Balasubramanian the board of claim 6, wherein the second card further comprises: an I/O circuit of the second card coupled to the second processing device and configured to: receive the operation result from the I/O circuit of the first card coupled to the first processing device, wherein the first processing device is a source of the operation result; and provide the operation result to the second processing device, wherein the second processing device is a destination of the operation result (Ito teaches that computing devices generate gradient data through DMA/bus/interconnect arrangement for communication with another distributed processing node [0054], Ito. The interconnect device of the receiving node receives the gradient data from an adjacent node; [0066], Ito. The DMA controller transfer the received aggregated data from the interconnect device, through the bus device, to the computing devices of the receiving node; [0074], Ito. Thus, Ito teaches the claimed source-to-I/O-to-I/O-to-destination process path).
With regards to claim 8, Ito teaches through Panzarella and Balasubramanian the board of claim 6, wherein the second card further comprises: an I/O circuit of the second card coupled to the second processing device and configured to: receive the operation result from the I/O circuit of the first card coupled to the first processing device, wherein the first processing device is a source of the operation result; and forward the operation result to a third card of the ring topology of the second communication network, wherein the second processing device is not a destination of the operation result (Ito teaches that computing devices generate gradient data through DMA/bus/interconnect arrangement for communication with another distributed processing node [0054]. The interconnect device of the receiving node receives the gradient data from an adjacent node; [0066], instead of providing the to a computing device of that node, processes and transfer the gradient data to the next node; [0067]. Because the nodes are connected in a ring shape, the next node corresponds to the claimed third node, while the computing device of the intermediate receiving node is not the destination; [0068], Ito).
With regards to claim 9, Ito teaches through Panzarella and Balasubramanian the board of claim 8, wherein the operation result is forwarded to the third card by the I/O circuit of the second card without being provided to the second processing device of the second card (Ito teaches that the interconnect device 104 of an intermediate distributed processing node receives gradient data to the next node through transmission line 101A; [0066-0067]. The forwarding is therefore performed by the interconnect device communication circuitry without providing the received gradient data to the computing devices of the intermediate node. Because the distributed processing nodes are connected in a ring shape, the next node corresponds to the claimed third card; [0068], Ito).
With regards to claim 10, Ito teaches through Panzarella and Balasubramanian the board of claim 6, wherein the first processing device and the I/O circuit of the first card
form a computing node of the first card, and wherein the computing node is a device physically separate from the first controller (Ito teaches a distributed processing node 102 including computing devices 103 and an interconnect device 104, with a bus/DMA arrangement transferring data between the computing devices and the interconnect device, thereby corresponding to the claimed computing node including the processing device and I/O circuitry; [0039-0040]. Ito further discloses the computing devices/interconnect device are mounted on a PCI-express daughter board associated with the server hardware (i.e., computing node is physically separate from the control unit); [0041-0042], Ito).
With regards to claims 23, 27, and 28, the claim limitations are identical and/or equivalent in scope to claim 1, therefore, claims 23, 27, and 28 are rejected under the same rationale as claim 1.
With regards to claim 24, Ito teaches through Panzarella and Balasubramanian the chassis of claim 23, further comprising a network device coupled to the first card,
wherein data traffic is routed from the first card to the network device, and wherein the network device is configured to route the data traffic to a computing device of another board of the chassis (Ito teaches that gradient data generated by computing devices 103 of a distributed processing node is transferred through the bus device 105 to interconnect device 104; [0054]. The interconnect device 104 communicates the data with other distributed processing nodes [0020], and the received data is subsequently transferred to computing devices 103 of the receiving node [0074], Ito. Thus, Ito teaches routing data from a first processing/card arrangement through an interconnect/network device to a computing device of another processing node).
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Ito, in view of Panzarella, further in view of Balasubramanian, and further in view of Chen et al. (CN 118827356).
With regards to claim 3, Ito, Panzarella, and Balasubramanian teach limitations of claim 3 as applied to claim 1, except for wherein the first card is configured to be addressed by a first media access control address (MAC) address and a first slot identifier that uniquely identifies the first card on the board, and wherein the second card is configured to be addressed by a second MAC address different from the first MAC address and a second slot identifier different from the first slot identifier.
However, in the same field of endeavor Chen teaches the first card is configured to be addressed by a first media access control address (MAC) address and a first slot identifier that uniquely identifies the first card on the board, and wherein the second card is configured to be addressed by a second MAC address different from the first MAC address and a second slot identifier different from the first slot identifier (…obtaining the media access control (MAC) address of each network card (i.e., claimed first card and second card) via the out-of-band management interface of the server; the first information represents the installation position of the network card in the server; … In the above solution, the first information includes a physical slot number and/or a physical slot number of the network card; [Page 2, paragraph starting with “based on the first information…” and paragraph starting with “In the above solution…”], Chen).
One of ordinary skill in the art would have been motivated to modify teachings of Ito, Panzarella, and Balasubramanian to employ Chen’s addressing scheme, including assigning different MAC addresses and slot identifier to respective cards, to uniquely identify and facilitate addressing and management of cards. Further assigning sequential slot identifiers to neighboring cards as taught by Chen, would provide an orderly identification scheme that facilitates determining the locations of the cards and routing communications.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to have combined the teachings of Ito, Panzarella, Balasubramanian, and Chen to uniquely identify and facilitate addressing and management of cards.
With regards to claim 5, Ito, Panzarella, and Balasubramanian teach limitations of claim 5 as applied to claim 4, except for wherein the first card has a slot identifier, the left neighbor card has a left slot identifier, the right neighbor card has a right slot identifier, and wherein a difference between the slot identifier for the first card and the left slot identifier is 1, and a difference between the slot identifier for the first card and the right slot identifier is 1.
However, in the same field of endeavor Chen teaches the first card has a slot identifier, the left neighbor card has a left slot identifier, the right neighbor card has a right slot identifier, and wherein a difference between the slot identifier for the first card and the left slot identifier is 1, and a difference between the slot identifier for the first card and the right slot identifier is 1 (the first information of the network card can be denoted as "slot 2-1". In practical application, the first information can also characterize the physical slot number and/or physical slot number corresponding to the network card in other set formats, for example, "slot 2-1" in the above can also be expressed as "slot 2.1", "slot 2/1", "slot b-a", "slotb.a" or "slot b/a", which are not limited here (i.e., this paragraph establishes that slot identifiers are sequential, incrementing numerical indices that remain functionally identical regardless of the syntactic delimiter or naming format used); [Page 4, paragraph starting with “Here, the first information …”], Chen).
The same rationale to combine for claim 3 applies.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ito, in view of Panzarella, further in view of Balasubramanian, and further in view of K N et al. (US 11394663), hereinafter Kiran.
With regards to claim 11, Ito, Panzarella, and Balasubramanian teach limitations of claim 11 as applied to claim 10, except for wherein the I/O circuit of the first card comprises a number of queues, and wherein a queue of the number of queues is configured to store the one or more data packets, wherein a data packet of the one more data packets comprises a source address and a destination address.
However, in the same field of endeavor Kiran teaches the I/O circuit of the first card comprises a number of queues, and wherein a queue of the number of queues is configured to store the one or more data packets, wherein a data packet of the one more data packets comprises a source address and a destination address (Physical network interface 202 may be a network interface card (NIC), line card (i.e., claimed I/O circuit of the first card), physical port etc. Physical network interface 202 can send and receive network packets to and from other network interfaces. Physical network interface 202 can be a wired network interface or a wireless network interface. Physical network interface 202 places received network packets on one of device queues 204A-204D (generically referred to as a “device queue 204”). Device queue 204 can be a First-Out (FIFO) queue (also referred to as a “ring buffer”). Physical network interface 202 may load balance network packets by distributing incoming network packets across device queues 204A-204D. In some aspects, physical network device 202 hashes packet header information of a network packet to determine a device queue 204 to receive the network packet. For example, physical network device 202 may perform receive side scaling (RSS) hashing on a 5-tuple comprising the source address, source port, destination address, destination port, and protocol identifier included in a header of a network packet. RSS hashing can perform load balancing by randomly distributing network packets to device queues 204A-204D according to the results of the hashing function; column 9, lines 52-67 and column 10, lines 1-6, Kiran).
One of ordinary skill in the art would have been motivated to modify the teachings of Ito, Panzarella, and Balasubramanian to incorporate the multiple packet queues taught by Kiran in order to buffer and manage packets based on packet-header information, including source and destination addresses.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to have combined the teachings of Ito, Panzarella, Balasubramanian, and Kiran to improve packet handling and distribution efficiency, including facilitating load balancing and orderly processing of packets communicated through the network interface.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Ito, in view of Panzarella, further in view of Balasubramanian, and further in view of Cambron (US 6539027).
With regards to claim 25, Ito, Panzarella, and Balasubramanian teach the limitations of claim 25 as applied to claim 23 except for wherein the board further comprises a multiplexer circuit coupled to a first port of the first card and a first port of the second card, wherein the multiplexer circuit is controlled by the instruction processing device of the chassis.
However, in the same field of endeavor Cambron teaches the board further comprises a multiplexer circuit coupled to a first port of the first card and a first port of the second card, wherein the multiplexer circuit is controlled by the instruction processing device of the chassis (Cambron teaches … The intelligent multiplexer also includes a plurality of circuit cards 31 having substantially identical conformations, the circuit cards 31 being configured to be placed in any of the slots 23 of the shelf 22 in interchangeable fashion. Each circuit card 31 includes one or more backplane connectors 32…; column 6, lines 39-44, Cambron. Cambron further teaches ...Data to/from the network is then routed through the card using a series of multiplexer (mux) devices and buffers to mapping circuitry, which distributes the digital signals in properly time format to the system bus interface...; column 8, lines 66-67 and column 9, lines 1-3, Cambron. Cambron further teaches … to establish a connection between two ports of two feature cards, the user selects… (i.e., first port of the first card and a first port of the second card); column 12, lines 32-32, Cambron. Cambron further teaches as illustrated conceptually in FIG. 4, the functions of a central controller card 31 A, managed by the processor 41, include providing an interface for an asynchronous terminal or a network management system. In addition, the central controller controls and monitors other common equipment and feature cards, and provides a real time clock. It also provides control of T1 clock selection, and controls alarm cutoff and bypass functions. The central controller manages all alarm functions, and also maintains a nonvolatile memory storage of the system configuration; column 8, lines 48-57, Cambron. Cambron further teaches … The Design Manager of the Software Shell (FIG. 6) assembles and translates all the detailed data regarding node configuration and span connections into a network map. The map is stored by the central controller and may be referenced via SNMP, and may also be transmitted to the nodes if they are preexisting, or to the planned nodes as they are constructed… (i.e., multiplexer circuit is controlled by the instruction processing device); column 12, lines 61-67, Cambron).
One of ordinary skill in the art would have been motivated to modify the teachings of Ito, Panzarella, and Balasubramanian to incorporate Cambron’s reconfigurable multiplexer and centralized routing techniques to provide configurable communications among the processing cards.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to have combined the teachings of Ito, Panzarella, Balasubramanian, and Cambron to provide increased routing and configuration flexibility using known techniques.
Claim 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Ito, in view of Panzarella, further in view of Balasubramanian, and further in view of Naouri (US 20150319231).
With regards to claim 29, Ito, Panzarella, and Balasubramanian teach limitations of claim 29 as applied to claim 28, except for wherein the second communication network comprises a star topology including computing nodes located at different chassis of the rack.
However, in the same field of endeavor Naouri teaches the second communication network comprises a star topology including computing nodes located at different chassis of the rack (FIG. 2b is a diagram illustrating a plurality of DSW servers linked together via connections to a ToR switch using a star configuration; [0015]. Naouri further teaches … a rack (or elsewhere) that includes multiple server chassis, each including one or more physical servers… [0032], Naouri. Thus, Naouri teaches claimed Star topology among computing resources associated with different server chassis).
One of ordinary skill in the art would have been motivated to apply Naouri’s star, mesh, or daisy-chain topologies to teachings of Ito, Panzarella, and Balasubramanian to provide alternative, known arrangements for interconnecting computing nodes across multiple chassis.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to have combined the teachings of Ito, Panzarella, Balasubramanian, and Naouri to provide increased flexibility, scalability, and routing options for the distributed processing system without changing the fundamental operation of the system.
With regards to claim 30, Ito, Panzarella, and Balasubramanian teach limitations of claim 30 as applied to claim 28, except for, wherein the second communication network comprises a mesh topology including computing nodes located at different chassis of the rack.
However, in the same field of endeavor Naouri teaches the second communication network comprises a mesh topology including computing nodes located at different chassis of the rack (Naouri teaches FIG. 2a is a diagram illustrating a plurality of DSW servers linked together via a fabric mesh of direct links; [0014]. Naouri further teaches … a rack (or elsewhere) that includes multiple server chassis, each including one or more physical servers… {0032], Naouri. Thus, Naouri teaches a mesh communication network connecting computing resources in a multi-chassis rack).
The same rationale to combine for claim 29 applies.
With regards to claim 31, Ito, Panzarella, and Balasubramanian teach limitations of claim 30 as applied to claim 28, except for, wherein the second communication network comprises a chain topology.
However, in the same field of endeavor Naouri teaches the second communication network comprises a chain topology (Naouri teaches FIG. 3 is a diagram of a DSW-enabled rack including a plurality of DSW server chassis linked in communication using a daisy chain configuration; [0016], Naouri).
The same rationale to combine for claim 29 applies.
Allowable Subject Matter
Claims 12-22, and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/S.K./Examiner, Art Unit 2455
/EMMANUEL L MOISE/Supervisory Patent Examiner, Art Unit 2455
Prosecution Insights