DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8 and 10-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neiger et al. 10713177 herein Neiger in view of Xu et al. 20170168953 herein Xu.
Per claim 1, Neiger discloses: obtaining a memory access request of a first computing unit, wherein the memory access request indicates to perform memory access on a shared memory space, (fig. 1, col. 4 line 49; During execution of a guest application 120, responsive to a request to access memory 104, memory management unit 108 may use the host physical addresses to access memory 104.) the memory access request comprises an .. identifier of the first computing unit, and the first computing unit is in a first computing device in a computing device cluster, wherein each computing device in the computing device cluster comprises at least one computing unit; (fig. 7, col. 4 line 49; The HPA space may be organized according memory frames that each has a fixed size. Each one of the memory frames may be associated with an identifier (e.g. memory frame number) that uniquely identifies the memory frame. Processing core 106 may execute VMM 114 to create a mapping from the GPA space 124 of VM 116 to the HPA space of the host. The mapping may be stored in an extended page table (EPT) 126 stored in memory 104.) querying a page table route based on the .. identifier of the first computing unit, the querying determining a target page table corresponding to the first computing unit, (col. 5 line 14; Guest OS 118 may translate the guest virtual addresses in GVA space 122 into guest physical addresses in GPA space 124. Memory management unit 108 may employ EPTEs 128 in EPT 126 specified by VMM 114 to map guest physical addresses into host physical addresses for accessing memory. In one embodiment, memory management unit 108 may load an EPTE 128 of EPT 126 into a register 110 associated with memory management unit 108 so that the memory management unit 108 may perform the memory address mapping on behalf of processing cores 106.) wherein the page table route stores correspondences between … identifiers of a plurality of computing units and a plurality of groups of page tables, (col. 4 line 49; In one embodiment, a policy data structure 140 stored in memory 104 may include rules that specify how to determine the access rights stored in EPTEs based on the corresponding page attributes (e.g., the user mode or the supervisor mode).) each group of page tables in the plurality of groups of page tables stores a computing unit access permission, and computing unit access permissions stored in the plurality of groups of page tables are different; and processing the memory access request based on a computing unit access permission stored in the target page table (col. 4 line 49; Thus, the VMM 114 may specify access rights in an EPTE different from the access rights assigned to the corresponding guest virtual address page by the guest OS 118. In this way, VMM 114 may provide a further layer of protection to a memory frame by modifying the access rights stored in the EPTE based on rules).
Neiger discloses identifying the does not specifically disclose an object identifier of the first computing unit: the memory access request comprises an object identifier of the first computing unit.
However, Xu discloses: the memory access request comprises an object identifier of the first computing unit (fig. 2, ¶0109; Receive a file access request from a process, where the file access request includes a file identifier, and the file identifier is used to indicate a to-be-accessed object file).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Neiger and Xu to reduce overhead during file access. Xu improves file access speed (¶0071; This can effectively reduce software running overheads during file access and improve a file access speed).
Per claim 2, Neiger discloses: wherein each group of page tables in the plurality of groups of page tables further stores a memory address mapping relationship; the memory address mapping relationship is used to determine, in response to the memory access request being processed, a target address to be accessed by the memory access request; and memory address mapping relationships stored in the plurality of groups of page tables are the same (col. 5 line 14; Guest OS 118 may translate the guest virtual addresses in GVA space 122 into guest physical addresses in GPA space 124. Memory management unit 108 may employ EPTEs 128 in EPT 126 specified by VMM 114 to map guest physical addresses into host physical addresses for accessing memory. In one embodiment, memory management unit 108 may load an EPTE 128 of EPT 126 into a register 110 associated with memory management unit 108 so that the memory management unit 108 may perform the memory address mapping on behalf of processing cores 106.).
Per claim 3, Neiger discloses: wherein each group of page tables in the plurality of groups of page tables comprises an access permission flag, the access permission flag represents the computing unit access permission, and the computing unit access permission the following permissions: a read-only permission, a read-write permission, or a write-only permission (col. 3, line 6; an expanded set of access right flags that the VMM may specify how access rights may be based on one or more paging attributes controlled by the guest OS (e.g., the user/supervisor mode). The VMM may specify the access rights according to rules stored in a policy data structure. For example, the existing access right flags stored in an EPTE may be expanded from (R, W, X) to (RU, WU, XU, RS, WS, XS), wherein (RU, WU, XU) are the access rights of “read”, “write”, and “execute” associated with the user mode assigned to a virtual address by the guest operating system, and (RS, WS, XS) are the access rights of “read”, “write”, and “execute” associated with the supervisor mode assigned to a virtual address by the guest operating system).
Per claim 4, Neiger discloses: wherein the plurality of groups of page tables comprise a first group of page tables and a second group of page tables, an access permission flag in the first group of page tables represents that a computing unit access permission is a read-only permission, and an access permission flag in the second group of page tables represents that a computing unit access permission is a read-write permission (col. 3, line 6; an expanded set of access right flags that the VMM may specify how access rights may be based on one or more paging attributes controlled by the guest OS (e.g., the user/supervisor mode). The VMM may specify the access rights according to rules stored in a policy data structure. For example, the existing access right flags stored in an EPTE may be expanded from (R, W, X) to (RU, WU, XU, RS, WS, XS), wherein (RU, WU, XU) are the access rights of “read”, “write”, and “execute” associated with the user mode assigned to a virtual address by the guest operating system, and (RS, WS, XS) are the access rights of “read”, “write”, and “execute” associated with the supervisor mode assigned to a virtual address by the guest operating system;).
Per claim 5, Neiger discloses: wherein the memory access request comprises a write operation instruction, and the processing the memory access request based on a computing unit access permission stored in the target page table comprises: if the computing unit access permission stored in the target page table is a read-write permission or a write-only permission, executing the write operation instruction in the memory access request; or if the computing unit access permission stored in the target page table is a read-only permission, ignoring the memory access request (col. 3, line 6; an expanded set of access right flags that the VMM may specify how access rights may be based on one or more paging attributes controlled by the guest OS (e.g., the user/supervisor mode). The VMM may specify the access rights according to rules stored in a policy data structure. For example, the existing access right flags stored in an EPTE may be expanded from (R, W, X) to (RU, WU, XU, RS, WS, XS), wherein (RU, WU, XU) are the access rights of “read”, “write”, and “execute” associated with the user mode assigned to a virtual address by the guest operating system, and (RS, WS, XS) are the access rights of “read”, “write”, and “execute” associated with the supervisor mode assigned to a virtual address by the guest operating system; the notes that the two if limitation are contingent and not required to teach the claim. Assuming arguendo, the cited portion teaches a combination of access permission based on the access request).).
Per claim 6, Neiger discloses: wherein the memory access request comprises a read operation instruction, and the processing the memory access request based on a computing unit access permission stored in the target page table comprises: if the computing unit access permission stored in the target page table is a read-write permission or a read-only permission, executing the read operation instruction in the memory access request; or if the computing unit access permission stored in the target page table is a write-only permission, ignoring the memory access request (col. 3, line 6; an expanded set of access right flags that the VMM may specify how access rights may be based on one or more paging attributes controlled by the guest OS (e.g., the user/supervisor mode). The VMM may specify the access rights according to rules stored in a policy data structure. For example, the existing access right flags stored in an EPTE may be expanded from (R, W, X) to (RU, WU, XU, RS, WS, XS), wherein (RU, WU, XU) are the access rights of “read”, “write”, and “execute” associated with the user mode assigned to a virtual address by the guest operating system, and (RS, WS, XS) are the access rights of “read”, “write”, and “execute” associated with the supervisor mode assigned to a virtual address by the guest operating system; the notes that the two if limitation are contingent and not required to teach the claim. Assuming arguendo, the cited portion teaches a combination of access permission based on the access request).
Per claim 7, Neiger discloses: wherein the page table route stores correspondences between the object identifiers of the plurality of computing units and page table base address information of the plurality of groups of page tables, and the page table route is generated in the following manner: (col. 4 line 49; In one embodiment, a policy data structure 140 stored in memory 104 may include rules that specify how to determine the access rights stored in EPTEs based on the corresponding page attributes (e.g., the user mode or the supervisor mode).)) in a process of applying for the shared memory space for a computing task, generating the plurality of groups of page tables for the applied shared memory space, wherein the memory address mapping relationship stored in the plurality of groups of page tables is a memory address mapping relationship for the shared memory space; (fig. 2; col. 5 line 14; Guest OS 118 may translate the guest virtual addresses in GVA space 122 into guest physical addresses in GPA space 124. Memory management unit 108 may employ EPTEs 128 in EPT 126 specified by VMM 114 to map guest physical addresses into host physical addresses for accessing memory. In one embodiment, memory management unit 108 may load an EPTE 128 of EPT 126 into a register 110 associated with memory management unit 108 so that the memory management unit 108 may perform the memory address mapping on behalf of processing cores 106.)) determining the plurality of computing units jointly processing the computing task in the computing device cluster, (fig. 7; the examiner notes the plurality of processor in the distributed system) and setting an access permission for each of the plurality of computing units; (col. 4 line 49; In one embodiment, a policy data structure 140 stored in memory 104 may include rules that specify how to determine the access rights stored in EPTEs based on the corresponding page attributes (e.g., the user mode or the supervisor mode).) separately determining, based on the access permission set for each computing unit and the computing unit access permissions in the plurality of groups of page tables, page tables corresponding to the plurality of computing units; (col. 4 line 49; Thus, the VMM 114 may specify access rights in an EPTE different from the access rights assigned to the corresponding guest virtual address page by the guest OS 118. In this way, VMM 114 may provide a further layer of protection to a memory frame by modifying the access rights stored in the EPTE based on rules). and generating the page table route based on the page tables corresponding to the plurality of computing units, the object identifiers of the plurality of computing units, and the page table base address information of the plurality of groups of page tables (fig. 2 col. 5 line 15; Guest OS 118 may translate the guest virtual addresses in GVA space 122 into guest physical addresses in GPA space 124. Memory management unit 108 may employ EPTEs 128 in EPT 126 specified by VMM 114 to map guest physical addresses into host physical addresses for accessing memory. In one embodiment, memory management unit 108 may load an EPTE 128 of EPT 126 into a register 110 associated with memory management unit 108 so that the memory management unit 108 may perform the memory address mapping on behalf of processing cores 106).
Per claim 8, Neiger discloses: wherein the querying a page table route based on the object identifier of the first computing unit, to determine a target page table corresponding to the first computing unit comprises: querying the page table route via a page table route control unit, to obtain target page table base address information corresponding to the object identifier of the first computing unit, (fig. 2 col. 5 line 15; Guest OS 118 may translate the guest virtual addresses in GVA space 122 into guest physical addresses in GPA space 124. Memory management unit 108 may employ EPTEs 128 in EPT 126 specified by VMM 114 to map guest physical addresses into host physical addresses for accessing memory.) and writing the target page table base address information into a directory base address register via the page table route control unit, wherein the target page table base address information is page table base address information of the target page table; and reading the target page table base address information from the directory base address register via a memory management unit (MMU), and determining the target page table via the memory management unit based on the target page table base address information (fig. 2 col. 5 line 15; In one embodiment, memory management unit 108 may load an EPTE 128 of EPT 126 into a register 110 associated with memory management unit 108 so that the memory management unit 108 may perform the memory address mapping on behalf of processing cores 106).
Claims 10-17 are the device claims corresponding to the method claims 1-8 and are rejected under the same reasons set forth in connection with the rejection of claims 1-8.
Claim 19 is the CRM device claim corresponding to the method claim 1 and is rejected under the same reasons set forth in connection with the rejection of claim 1.
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Neiger et al. 10713177 herein Neiger and Xu et al. 20170168953 herein Xu in view of Wallach 20200073822 herein Wallach.
Per claim 9, the combined teachings of Neiger and Xu do not specifically discloses: wherein the object identifier of the first computing unit comprises a device number of the first computing device and an object number of the first computing unit.
However, Wallach discloses: wherein the object identifier of the first computing unit comprises a device number of the first computing device and an object number of the first computing unit (¶0017; The memory management unit (MMU) can combine (e.g., via hashing, indexing, and/or multiplexing) the information related to the identifications of virtual memory spaces to locate a page table or page directory. Examples of such information include a virtual machine identifier, a domain identifier, a processor identifier, an object identifier provided in a virtual memory address, a portion of an offset within the object represented by the object identifier, etc. The page table or page directory can be used in converting the virtual memory address into a physical memory address).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Neiger, Xu and Wallach’s MMU’s privilege levels to protect data and functionality form faults and malicious behaviors. Wallack improves security (¶0018).
Claim 18 is the device claim corresponding to the method claim 9 and is rejected under the same reasons set forth in connection with the rejection of claim 9.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
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