NON-FINAL OFFICE ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 and 10-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Pub. No. 2022/0188033 to Cho et al. (hereinafter Cho).
Cho discloses:
1. An apparatus, comprising:
a plurality of memory devices (para. [0028] and Fig. 1, memory dies 221); and
a memory controller coupled to the plurality of memory devices via a plurality of memory channels (para. [0035], Fig. 1, storage controller 210 and memory interface 212);
wherein the plurality of memory channels are organized as a plurality of channel groups (para. [0061] and Fig. 3A); and
wherein the memory controller comprises a plurality of memory access request/response buffer sets (paras. [0038], [0041], [0043], Fig. 1, buffer memory 216, command queue 218), and wherein each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups (paras. [0061], [0121] and Figs. 3A, 10);
wherein the plurality of memory access request/response buffer sets are located within a front end portion of the memory controller (paras. [0036], [0041] and Fig. 1).
2. The apparatus of claim 1, wherein the front end portion of the memory controller comprises a compute express link (CXL) controller coupled to a host via a CXL link (para. [0131]).
3. The apparatus of claim 1, wherein each memory access request/response buffer set of the plurality of memory access request/response buffer sets comprises:
a read request buffer (para. [0032] and Fig. 1, command queue 218);
a write request buffer (paras. [0032], [0041] and Fig. 1, buffer memory 216, command queue 218);
a read response buffer (para. [0041] and Fig. 1, buffer memory 216); and
a write response buffer (paras. [0038], [0146]).
4. The apparatus of claim 3, wherein for each memory access request/response buffer set of the plurality of memory access request/response buffer sets:
the read request buffer is a master to subordinate (M2S) request buffer in accordance with a compute express link (CXL) protocol (paras. [0143]-[0147]);
the write request buffer is a M2S request buffer in accordance with the CXL protocol (paras. [0143]-[0147]);
the read response buffer is a subordinate to master (S2M) response buffer in accordance with the CXL protocol (paras. [0143]-[0147]); and
the write request buffer is a S2M response buffer in accordance with the CXL protocol (paras. [0143]-[0147]).
5. The apparatus of claim 1, wherein the plurality of channel groups comprises:
a first channel group comprising a first quantity of the plurality of memory channels (Figs. 3A and 10); and
a second channel group comprising a second quantity of the plurality of memory channels (Figs. 3A and 10);
wherein the first channel group includes first error correction circuitry that is operated, by the memory controller, in association with accessing memory devices corresponding to the first quantity of the plurality of memory channels (paras. [0045], [0161], [0174]); and
wherein the second channel group includes second error correction circuitry that is operated, by the memory controller and independently from the first error correction circuitry, in association with accessing memory devices corresponding to the second quantity of the plurality of memory channels (paras. [0045], [0161], [0174]).
6. The apparatus of claim 5, wherein the plurality of channel groups comprises:
a third channel group comprising a third quantity of the plurality of memory channels (Fig. 10); and
wherein the third channel group includes third error correction circuitry that is operated, by the memory controller and independently from the first error correction circuitry and the second error correction circuitry, in association with accessing memory devices corresponding to the third quantity of the plurality of memory channels (paras. [0045], [0161], [0174]).
7. The apparatus of claim 1, wherein the memory controller is configured to concurrently the plurality of memory access request/response buffer sets in association with performing memory access requests on memory devices corresponding to respective channel groups (para. [0046]).
8. The apparatus of claim 1, wherein a central portion of the memory controller includes a plurality of error manager components corresponding to respective ones of the plurality of channel groups (paras. [0045], [0161], [0174]).
10. A memory controller, comprising:
a front end portion configured to be coupled to a host via an interface (para [0038] and Fig. 1, host interface 211);
a back end portion configured to be coupled to a plurality of memory devices via a plurality of memory channels (para. [0035], Fig. 1, storage controller 210 and memory interface 212), wherein the plurality of memory channels are organized as a plurality of channel groups (para. [0061] and Fig. 3A); and
a central portion comprising a plurality of error manager components , wherein each error management component of the plurality of error management components corresponds to a different one the plurality of channel groups (paras. [0045], [0161], [0174]); and
wherein the front end portion comprises a plurality of memory access request/response buffer sets (paras. [0038], [0041], [0043], Fig. 1, buffer memory 216, command queue 218), wherein each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups (paras. [0061], [0121] and Figs. 3A, 10).
11. The memory controller of claim 10, wherein the central portion further comprises a plurality of independent caches, wherein each cache of the plurality of independent caches corresponds to a different one of the plurality of channel groups (paras. [0038], [0041], [0043], Fig. 1, buffer memory 216, command queue 218, and Fig. 10).
12. The memory controller of claim 10, wherein the plurality of memory access request/response buffer sets are configured to be operated in parallel in association with performing memory access requests in parallel on memory devices corresponding to the respective channel groups (paras. [0046], [0058] and Fig. 3A).
13. The memory controller of claim 10, wherein the interface operates in accordance with a compute express link (CXL) protocol (para. [0131]).
14. The memory controller of claim 10, wherein each memory access request/response buffer set of the plurality of memory access request/response buffer sets includes:
a master to subordinate (M2S) request buffer in accordance with a compute express link (CXL) protocol (paras. [0143]-[0147]);
a M2S request buffer in accordance with the CXL protocol (paras. [0143]-[0147]);
a subordinate to master (S2M) response buffer in accordance with the CXL protocol (paras. [0143]-[0147]); and
a S2M response buffer in accordance with the CXL protocol (paras. [0143]-[0147]).
15. The memory controller of claim 10, wherein the front end portion comprises a CXL controller configured to receive commands from a host (para. [0131]).
16. An apparatus, comprising:
a plurality of memory devices (para. [0028] and Fig. 1, memory dies 221); and
a memory controller coupled to the plurality of memory devices via a plurality of memory channels (para. [0035], Fig. 1, storage controller 210 and memory interface 212), wherein the plurality of memory channels are organized as a plurality of channel groups (para. [0061] and Fig. 3A);
wherein the memory controller comprises:
a front end portion comprising a plurality of memory access request/response buffers (paras. [0036], [0038], [0041], [0043], Fig. 1, buffer memory 216, command queue 218); and
a central portion comprising a plurality of memory access request/response buffer sets (paras. [0038], [0041], [0043], Fig. 1, buffer memory 216, command queue 218), wherein each memory access request/response buffer set of the plurality of memory access request/response buffer sets corresponds to a different one of the plurality of channel groups (paras. [0061], [0121] and Figs. 3A, 10).
17. The apparatus of claim 16, wherein the front end portion is configured to:
receive memory access requests from a host in accordance with a compute express link (CXL) protocol (paras. [0027], [0131]); and
provide memory access responses to the host in accordance with the CXL protocol (paras. [0027], [0131]).
18. The apparatus of claim 16, wherein the central portion further comprises a plurality of independent caches corresponding to the respective plurality of channel groups (paras. [0038], [0041], [0043], Fig. 1, buffer memory 216, command queue 218, and Fig. 10).
19. The apparatus of claim 16, wherein the memory controller is configured to operate the plurality of channel groups as independent respective reliability, availability, and serviceability (RAS) channels (paras. [0045], [0161], [0174]).
Allowable Subject Matter
Claims 9 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Philip Guyton whose telephone number is (571)272-3807. The examiner can normally be reached M-F 8:00-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHILIP GUYTON/Primary Examiner, Art Unit 2113
Prosecution Insights