DETAILED ACTION
This action is in response to the Applicant’s preliminary amendment filed on June 6, 2025. As set forth therein, claims 1-18 are canceled and claims 19-43 are newly added. Claims 19-43 are pending.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 6, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Reissue Applications
For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 7,911,844 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Reissue Declaration
The reissue oath/declaration filed with this application is defective (see 37 CFR 1.175 and MPEP § 1414) because of the following:
The Examiner notes that the error upon which reissue is based is set forth as:
Claim 1 of 7,911,844 recites a storage device with transfer transistors having diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Claim 19 recites a storage device having transfer transistors including a first transfer transistor comprising first and second active regions and a second transfer transistor comprising third and fourth active regions. Claim 19 does not recite that the first through fourth active regions function as source/drain layers1.
The Examiner first notes that the statement “Claim 19 recites a storage device having transfer transistors including a first transfer transistor comprising first and second active regions and a second transfer transistor comprising third and fourth active regions” is not set forth in claim 19. The Examiner finds that claim 19 currently recites drain/source regions and therefore, the error statement is not reflected in the current claim set. In addition, the claim does not recites “third and fourth” active regions, rather the claim recites second drain/source regions. The Examiner acknowledges that new claim 30 recites a first transfer transistor with a first and second active region and a second transfer transistor with a third and fourth active region, however, the Applicant’s error statement is directed to claim 19.
In addition, the stated error has already been corrected in a previous reissue. For example, if the error is directed to recited “active regions” as opposed to “source/drain layer”, RE50,512 recites a claim in which a transfer transistor comprises active region without the recitation of a source/drain layer. It is also noted that claim 19 of the instant reissue is similar to RE49274 since it recites source/drain layers for the transfer transistors.
Thus, the Applicant has not identified an error being corrected by this instant reissue continuation application.
Reissue Application – 35 U.S.C. 251
Claims 19-43 are rejected under 35 U.S.C. 251 as being in violation of the original patent requirement.
Section 251 requires that reissue is for “the invention disclosed in the original patent.” In order to satisfy the original patent requirement, “[i]t must appear from the face of the instrument that what is covered by the reissue was intended to have been covered and secured by the original.” U.S. Indus. Chems., Inc. v. Carbide & Carbon Chems. Corp., 315 U.S. 668, 676 (1942). Furthermore, “it is not enough that an invention might have been claimed in the original patent because it was suggested or indicated in the specification.” Id. In other words, the original patent “must clearly and unequivocally disclose the newly claimed invention as a separate invention.” Antares Pharma, Inc. v. Medac Pharma Inc., 771 F.3d 1354, 1362 (Fed. Cir. 2014).
In the present case, the original patent disclosed a non-volatile semiconductor storage device. This is set forth in the title of the patent, the abstract and each of the original claims (including claims as filed of the original application).
In addition, col. 1, lines 16-19 recites:
The present invention relates to a non-volatile semiconductor storage device, and, more particularly, a non-volatile semiconductor storage device including transfer transistors to transfer a high voltage.
Col. 2, lines 3-4 recites:
“One aspect of the present invention provides a non-volatile semiconductor storage device comprising: a memory cell array having memory cells arranged therein…”
Col. 6, lines 37-40 recites:
FIG. 9 is a plan view illustrating the wiring layout of the transfer transistors QNi provided in a non-volatile semiconductor storage device according to the second embodiment of the present invention.
Col. 7, lines 4-7 recites:
FIG. 10 is a plan view illustrating the wiring layout of the transfer transistors QNi provided in a non-volatile semiconductor storage device according to the third embodiment of the present invention.
The Examiner maintains that for reissue claims, “the specification of the original patent must do more than merely suggest or indicate the invention recited in reissue claims; ‘[i]t must appear from the face of the instrument that what is covered by the reissue was intended to have been covered and secured by the original.’” Forum US, Inc. v. Flow Valve, LLC, 926 F.3d 1346, 1351–52 (Fed. Cir. 2019) (quoting U.S. Indus. Chems. Inc. v. Carbide & Carbon Chems. Corp., 315 U.S. 668, 676 (1942)) .
As set forth in the current reissue claims, the claims are directed to a ‘semiconductor storage device’. The Examiner finds that it does not appear from the face of the original patent that applicant intended to cover and secure a ‘semiconductor storage device’ without it being a ‘non-volatile’ semiconductor storage device.
As set forth above, each of the original claims of the underlying patent2, as well as the specification only discloses a non-volatile semiconductor storage device.
Thus, the Examiner determines that the underlying patent does not clearly and unequivocally disclose any embodiment without a non-volatile semiconductor storage device, thus to broaden the claims to permit such an embodiment runs afoul of the original patent requirement.
Claims 30-43 are rejected under 35 U.S.C. 251 as being based upon new matter added to the patent for which reissue is sought. The added material which is not supported by the prior patent is discussed below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 30-43 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The Examiner notes that claim 30 recites, inter alia,
“the first portion having a first width in the second direction, a second portion extending in the first direction between the first portion and the common gate electrode in the second direction, the second portion at least partially overlapping with the first active region when viewed in the third direction, the second portion having a second width in the second direction smaller than the first width, and a third portion extending in the second direction to electrically connect the first and second portions, the third portion having a third width in the first direction.” (emphasis added)
The Examiner notes that the patent specification does not disclose any width associated with the wirings or that any portions of the wirings are smaller or bigger than other portions of wirings.
The Examiner notes that the Applicant, in their June 6, 2025 response provides support for the claims by referencing Figures 5, 8 and 11. It was noted that the wirings are shown as CG in Figures 5, 8 and 11.
The Examiner notes however, in consideration of the cited drawings and the specification, the Applicant’s disclosure does not disclose that the drawings are to scale and further it is silent as to any dimensions. It is also noted that dependent claim 31 also recites “the third width is smaller than the first width”. As explained above, there is insufficient support for whether the drawings are drawn to scale and more specifically that any width is smaller than any other width.
In addition, the Examiner finds that dependent claims 33, 36, 37 and 40 each recite “a distance”. It is noted that although, col. 5, lines 32-35 discloses “distance between the wirings” and “other wirings” to prevent an increase in parasitic capacitance, it is not clear whether the disclosure provides specific teachings directed to “distance”. It is acknowledged that the drawings do have ‘distances’ between the wiring and thus a person of ordinary skill in the art would understand that there would be a distance between the wirings, however, since the drawings are not drawn to scale, there does not appear to be sufficient support for “a distance between the substrate and the common gate electrode of the first transistor and the second transistor in the third direction is smaller than a distance between the substrate and the first wiring in the third direction” (Claim 33) or “the distance between the substrate and the common gate electrode of the first transistor and the second transistor in the third direction is smaller than a distance between the substrate and the third wiring in the third direction” (Claim 36) or “the distance between the substrate and the common gate electrode of the first transistor and the second transistor in the third direction is smaller than a distance between the substrate and the second wiring in the third direction and a distance between the substrate and the fourth wiring in the third direction” (Claim 37) or “a distance between the substrate and the fourth portion of the second wiring in the third direction is larger than a distance between the substrate and the fifth portion of the second wiring in the third direction.” (Claim 40).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 19-23 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 19, 22, 23, 26, 27 and 29 of U.S. Patent No. RE50512. Although the claims at issue are not identical, they are not patentably distinct from each other because as shown below, the instant reissue claims is substantially the same as the claims of RE50512.
19/230,931
RE50512
19. A semiconductor storage device comprising:
19. A non-volatile semiconductor storage device comprising:
a memory cell array including a plurality of memory cells;
a memory cell array including a plurality of memory cells;
a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including:
a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including:
a first transfer transistor, and a second transfer transistor, the first and second transfer transistors comprising a common gate electrode extending in a first direction,
a first transfer transistor, and a second transfer transistor, the first and second transfer transistors comprising a common gate electrode extending in a first direction,
the first transfer transistor comprising first drain/source regions arranged in a second direction with the common gate electrode as a center, the second direction crossing the first direction,
the first transfer transistor comprising a first active region and a second active region arranged in a second direction with the common gate electrode as a center, the second direction crossing the first direction,
the second transfer transistor comprising second drain/source regions arranged in the second direction with the common gate electrode as a center; and
the second transfer transistor comprising a third active region and a fourth active region arranged in the second direction with the common gate electrode as a center; and
wirings provided to at least partially overlap with the first drain/source regions and the second drain/source regions
when viewed in a third direction, the third direction crossing the first direction and the second direction,
a first wiring electrically connected to the first active region,
the wirings including a first wiring, the first wiring comprising a first portion extending in the first direction, the first portion at least partially overlapping with one of the first drain/source regions when viewed in the third direction,
the first wiring comprising a first portion extending in the first direction, the first portion at least partially overlapping with the first active region when viewed in a third direction, the third direction crossing the first direction and the second direction,
a second portion extending in the first direction between the first portion and the common gate electrode in the second direction, the second portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
a second portion extending in the first direction between the first portion and the common gate electrode in the second direction, the second portion at least partially overlapping with the first active region when viewed in the third direction, and
a third portion extending in the first direction between the second portion and the common gate electrode in the second direction, the third portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
a fourth portion extending in the second direction to electrically connect the first to third portions.
a third portion extending in the second direction to electrically connect the first and second portions.
The Examiner notes that as shown in the above claim table, the reissue claim are substantially the same as the claim in RE50512. The Examiner notes that the differences include recited “drain/source” region as opposed to “active region” and reciting an additional portion of the wire and its layout relative to the drain/source regions as well as its direction.
The Examiner notes that reciting “drain/source” is not a patentable distinction since both “drain/source” and “active region” relate to a part of the transfer transistor. Thus, they both reference the same parts of the transfer transistor and/or the “drain/source” region is not shown to be any different than the “active region” of RE50512.
In addition, both the instant reissue claim and the claim of RE5012 recite a wiring with a plurality of portions. Although the reissue claim recites an additional portion of the wiring, this is not a patentable distinction since claim 19 of RE5012 already shows that the wiring portions can extend in different directions and are configured to overlap the active (drain/source) regions of the transistors. Therefore, it would have been obvious to a person of ordinary skill in the art to have additional portions of the wire. Indeed, dependent claims 26-27 recites wiring with fourth and fifth portions which overlap and which extends in a second and third direction. Thus, in light of claims 26-27 of RE50512 reciting an additional portion of the wiring is not a patentable distinction.
Claims 19-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 19-29 of U.S. Patent No. RE49274. Although the claims at issue are not identical, they are not patentably distinct from each other because as set forth in the below table, the claims are substantially the same except reissue claim 19 of the instant application broadly recites a ‘semiconductor storage device’ as opposed to the narrower ‘non-volatile semiconductor storage device. Thus, a broader claim is not patentably distinct from the narrower claim.
19/230,931
RE49274
19. A semiconductor storage device comprising:
19. A non-volatile semiconductor storage device comprising:
a memory cell array including a plurality of memory cells;
a memory cell array including a plurality of memory cells;
a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including:
a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including:
a first transfer transistor, and a second transfer transistor, the first and second transfer transistors comprising a common gate electrode extending in a first direction,
a first transfer transistor, and a second transfer transistor, the first transfer and second transfer transistors comprising a common gate electrode extending in a first direction,
the first transfer transistor comprising first drain/source regions arranged in a second direction with the common gate electrode as a center, the second direction crossing the first direction,
the first transfer transistor comprising first drain/source regions arranged in a second direction with the common gate electrode as a center, the second direction crossing the first direction,
the second transfer transistor comprising second drain/source regions arranged in the second direction with the common gate electrode as a center; and
the second transfer transistor comprising second drain/source regions arranged in the second direction with the common gate electrode as a center; and
wirings provided to at least partially overlap with the first drain/source regions and the second drain/source regions when viewed in a third direction, the third direction crossing the first direction and the second direction,
wirings provided to at least partially overlap with the first drain/source regions and the second drain/source regions when viewed in a third direction, the third direction crossing the first direction and the second direction,
the wirings including a first wiring, the first wiring comprising a first portion extending in the first direction, the first portion at least partially overlapping with one of the first drain/source regions when viewed in the third direction,
the wirings including a first wiring, the first wiring comprising a first portion extending in the first direction, the first portion at least partially overlapping with one of the first drain/source regions when viewed in the third direction,
a second portion extending in the first direction between the first portion and the common gate electrode in the second direction, the second portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
a second portion extending in the first direction between the first portion and the common gate electrode in the second direction, the second portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
a third portion extending in the first direction between the second portion and the common gate electrode in the second direction, the third portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
a third portion extending in the first direction between the second portion and the common gate electrode in the second direction, the third portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
a fourth portion extending in the second direction to electrically connect the first to third portions.
a fourth portion extending in the second direction to electrically connect the first to third portions.
The Examiner notes that each of claims 20-29 directly correspond to claims 20-29 of RE49274.
Claims 19-27 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 19-28 of U.S. Patent No. RE47355. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant reissue are substantially the same as the claims of RE47355.
19/230,931
RE47355
19. A semiconductor storage device comprising:
19. A non-volatile semiconductor storage device comprising:
a memory cell array including a plurality of memory cells;
a memory cell array including a plurality of memory cells;
a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including:
a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including
a first transfer transistor, and a second transfer transistor, the first and second transfer transistors comprising a common gate electrode extending in a first direction,
a first transfer transistor and a second transfer transistor,
the first transfer transistor comprising first drain/source regions
arranged in a second direction with the common gate electrode as a center, the second direction crossing the first direction,
the first transfer transistor comprising first drain/source regions,
the second transfer transistor comprising second drain/source regions arranged in the second direction with the common gate electrode as a center; and
the second transfer transistor comprising second drain/source regions,
the first and second transfer transistors comprising a common gate electrode extending in a first direction; and
wirings provided to at least partially overlap with the first drain/source regions and the second drain/source regions
when viewed in a third direction, the third direction crossing the first direction and the second direction,
wirings provided above the first drain/source regions and the second drain/source regions,
the wirings including a first wiring, the first wiring comprising a first portion extending in the first direction,
the first portion at least partially overlapping with one of the first drain/source regions when viewed in the third direction,
the wirings including a first wiring, the first wiring comprising a first portion,
a second portion
extending in the first direction between the first portion and the common gate electrode in the second direction,
the second portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
a second portion, and
a third portion each provided above one of the first drain/source regions,
the first portion and the third portion extending in the first direction,
the second portion extending in a second direction crossing the first direction, the first portion being connected to the one of the first drain/source regions via a first contact,
a third portion extending in the first direction between the second portion and the common gate electrode in the second direction, the third portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
a fourth portion extending in the second direction to electrically connect the first to third portions.
The Examiner notes that as shown in the above claim table, the reissue claim is substantially the same as the claim in RE47355. The Examiner notes that the differences include the recitation of additional portions of the wire as well as its layout relative to the drain/source regions as well as its direction.
The Examiner finds that both the instant reissue claim and the claim of RE47355 recites a wiring with a plurality of portions. Although the reissue claim recites an additional portion of the wiring, this is not a patentable distinction since claim 19 of RE47355 already shows that the wiring portions can extend in different directions are configured to overlap the drain/source regions of the transistors. Therefore, it would have been obvious to a person of ordinary skill in the art to have additional portions of the wire. Indeed, dependent claims 22-24 of RE47355 recites wirings with fourth and fifth portions which extend in a direction as well as connected to a contact. Thus, in light of claims 22-24 of RE47355 reciting an additional portion of the wiring is not a patentable distinction.
The Examiner notes that claims 20-27 correspond to claims 20, 21, 23-28 of RE47355 respectively.
Claims 19, 21 and 22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 19, 21 and 23 of U.S. Patent No. RE46526. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant reissue are substantially the same as the claims of RE46526.
19/230,931
RE46526
19. A semiconductor storage device comprising:
19. A non-volatile semiconductor storage device comprising:
a memory cell array including a plurality of memory cells;
a memory cell array including a plurality of memory cells;
a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including:
a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including
a first transfer transistor, and a second transfer transistor, the first and second transfer transistors comprising a common gate electrode extending in a first direction,
a first transfer transistor and a second transfer transistor,
the first transfer transistor comprising first drain/source regions arranged in a second direction with the common gate electrode as a center,
one of the first and second transfer transistors including a gate electrode formed above a semiconductor substrate and drain/source regions; and
the second direction crossing the first direction, the second transfer transistor comprising second drain/source regions arranged in the second direction with the common gate electrode as a center; and
wirings provided to at least partially overlap with the first drain/source regions and the second drain/source regions when viewed in a third direction, the third direction crossing the first direction and the second direction,
wirings provided above the drain/source regions of the first and second transfer transistors,
the wirings including a first wiring, the first wiring comprising a first portion extending in the first direction, the first portion at least partially overlapping with one of the first drain/source regions when viewed in the third direction,
one of the wirings including a first portion, a second portion, and a third portion each provided above one of the drain/source regions, the first portion being connected to the one of the drain/source regions via a contact, and
a second portion extending in the first direction between the first portion and the common gate electrode in the second direction, the second portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
the second portion and the third portion being arranged between the first portion and the gate electrode, the second portion being connected to the first portion,
a third portion extending in the first direction between the second portion and the common gate electrode in the second direction, the third portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
the third portion being connected to the second portion, a direction in which the third portion extends being different from a direction in which the second portion extends, wherein the first and second transfer transistors share the gate electrode, and the wirings are separately disposed for one or two of the transfer transistors.
a fourth portion extending in the second direction to electrically connect the first to third portions.
The Examiner notes that as shown in the above claim table, the reissue claim is substantially the same as the claim in RE46526. The Examiner notes that the differences include the recitation of additional portions of the wire as well as its layout relative to the drain/source regions as well as its direction.
The Examiner finds that both the instant reissue claim and the claim of RE46526 recites a wiring with a plurality of portions. Although the reissue claim recites an additional portion of the wiring, this is not a patentable distinction since claim 19 of RE46526 already shows that the wiring portions can extend in different directions. Therefore, it would have been obvious to a person of ordinary skill in the art to have additional portions of the wire extend in different directions. Indeed, dependent claim 22 of RE46526 recites that the first and second portion extend in a first direction.
Thus, in light of claim 22 of RE46526 reciting limitations directed to direction, a person of ordinary skill in the art would have found it obvious to include additional portions of the wire as well as its direction relative to other portions of a wire over the drain/source regions of the transistor.
The Examiner notes that claims 21 and 22 correspond to claims 21 and 23 of RE46526 respectively.
Claims 19 and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 30 and 32 of U.S. Patent No. RE45307. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant reissue are substantially the same as the claims of RE45307.
19/230,931
RE45307
19. A semiconductor storage device comprising:
30. A non-volatile semiconductor storage device comprising:
a memory cell array including a plurality of memory cells;
a memory cell array including a plurality of memory cells, the memory cells storing data in a non-volatile manner;
a plurality of transfer transistors configured to transfer a voltage to the memory cells, the transfer transistors including:
a plurality of transfer transistors configured to transfer a voltage to the memory cells,
a first transfer transistor, and a second transfer transistor, the first and second transfer transistors comprising a common gate electrode extending in a first direction,
each of the plurality of transfer transistors including a gate electrode formed on a semiconductor substrate via a gate insulation film and drain/source regions formed to sandwich the gate electrode therebetween; and
the first transfer transistor comprising first drain/source regions arranged in a second direction with the common gate electrode as a center,
the second direction crossing the first direction, the second transfer transistor comprising second drain/source regions arranged in the second direction with the common gate electrode as a center; and
wirings provided to at least partially overlap with the first drain/source regions and the second drain/source regions when viewed in a third direction, the third direction crossing the first direction and the second direction,
wirings provided above the drain/source regions of the plurality of transfer transistors, each of the wirings including a first portion and a second portion both provided above one of the drain/source regions,
the wirings including a first wiring, the first wiring comprising a first portion extending in the first direction, the first portion at least partially overlapping with one of the first drain/source regions when viewed in the third direction,
the first portion being connected to the one of the drain/source regions via a contact and
a second portion extending in the first direction between the first portion and the common gate electrode in the second direction, the second portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
the second portion being arranged between the first portion and the gate electrode, wherein the plurality of transfer transistors share the gate electrode, and the wirings are separately disposed for one or two of the plurality of transfer transistors.
a third portion extending in the first direction between the second portion and the common gate electrode in the second direction, the third portion at least partially overlapping with the one of the first drain/source regions when viewed in the third direction, and
a fourth portion extending in the second direction to electrically connect the first to third portions.
The Examiner notes that as shown in the above claim table, the reissue claim is substantially the same as the claim in RE45307. The Examiner notes that the differences include the recitation of additional portions of the wire as well as its layout relative to the drain/source regions as well as its direction.
The Examiner finds that both the instant reissue claim and the claim of RE45307 recites a wiring with a plurality of portions. Although the reissue claim recites an additional portion of the wiring, this is not a patentable distinction since the claims RE47307 already shows that the wiring portions can extend in different directions. Therefore, it would have been obvious to a person of ordinary skill in the art to have additional portions of the wire extend in different directions. Specifically dependent claim 33 of RE47307 recites that the first and second portion extend in a first direction.
In addition, claim 21 of the reissue corresponds to claim 32 of RE45307.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ovidio Escalante whose telephone number is (571)272-7537. The examiner can normally be reached on Monday to Friday - 6:00 AM to 2:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Fuelling, can be reached at telephone number (571)272-7537. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Ovidio Escalante/
Primary Examiner, Art Unit 3992
Conferees:
/MATTHEW E HENEGHAN/Primary Examiner, Art Unit 3992 /M.F/Supervisory Patent Examiner, Art Unit 3992
1 The Examiner notes that the error statement further states that the claim does not recite that the “active regions” function as “source/drain layers”. It is noted that although “active region” is a broader phrase than “drain/source” region, the Applicant has not clearly shown support for active regions which do not function as a source/drain layers.
2 The Examiner also finds that each of the previous parent reissues (RE45307, RE46526,RE47355, RE49274, and RE50512) each recite a nonvolatile semiconductor storage device.