Prosecution Insights
Last updated: October 01, 2026
Application No. 19/230,931

NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE

Final Rejection §112§251
Filed
Jun 06, 2025
Priority
Dec 20, 2007 — JP 2007-328852 +6 more
Examiner
ESCALANTE, OVIDIO
Art Unit
3992
Tech Center
3900
Assignee
KIOXIA Corporation
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
12m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
177 granted / 232 resolved
+16.3% vs TC avg
Moderate +6% lift
Without
With
+5.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
262
Total Applications
across all art units

Statute-Specific Performance

§101
3.3%
-36.7% vs TC avg
§103
28.4%
-11.6% vs TC avg
§102
9.8%
-30.2% vs TC avg
§112
22.4%
-17.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 232 resolved cases

Office Action

§112 §251
DETAILED ACTION This action is in response to the Applicant’s response filed on June 30, 2026. As set forth therein, claims 1-18 are canceled and claims 19-43 are newly added. Claims 19-43 are pending. Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. Reissue Applications For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions. For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions. Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 7,911,844 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04. Response to Arguments Reissue Declaration The Examiner acknowledges the Applicant’s request for deferring the submission of a new Declaration. In view of the Request, the Examiner will continue to maintain the rejection until this issue is resolved. 35 U.S.C. § 251 In view of the original patent requirement, the Applicant states that the essential inquiry is “whether one skill in the art, reading the specification, would identify the subject matter of the new claims as invented and disclosed by the patentees. In short, the absence of an ‘intent,’ even if objectively evidenced form the earlier claims, the drawings, or the original object of the invention is simply not enough to establish that the new claims are not drawn to the invention disclosed in the original patent. The Applicant states that that is nothing in the original patent that shows an intent that only non-volatile memories are suitable for use with the claimed transfer transistors and wirings and that the example for non-volatile memory is “one aspect present invention”. The Examiner notes as set forth in the previous office action, the entirety of the underlying patent specification is directed to non-volatile semiconductor storage device. No other type of memory is disclosed. It is noted that the description of the related art discussed a memory directed to a NAND cell type flash memory and thus it is clear that the entire disclosure and discussion of related art is directed to a non-volatile semiconductor storage device. The specification does disclose whether its disclosed invention is applicable to the broader semiconductor memory that is not a non-volatile semiconductor storage device (e.g. volatile type memories). The Examiner acknowledges that the specification discloses that the non-volatile memory is “one aspect of the present invention” however, the specification does not state that the other aspects relate to a memory that is not a non-volatile memory device. The Examiner notes that as set forth in MPEP 1412.1: To satisfy the original patent requirement where a new invention is sought by reissue, "… the specification must clearly and unequivocally disclose the newly claimed invention as a separate invention." Antares Pharma, Inc., 771 F.3d at 1363, 112 USPQ2d at 1871. Accordingly, claims drawn to an invention comprising a newly claimed combination of features that were only disclosed in the original patent as suggested alternatives (and not as a single combination) or only as part of the original invention and not as an invention separate from the original invention would not satisfy the original patent requirement. See also Forum US, Inc. v. Flow Valve, LLC, 926 F.3d 1346, 1352, 2019 USPQ2d 221227 (Fed. Cir. 2019) ("nowhere do the written description or drawings disclose that arbors are an optional feature of the invention. Even if a person of ordinary skill in the art would understand that the newly claimed, arbor-less invention would be possible, that is insufficient to comply with the standard set forth in Industrial Chemicals [315 U.S. 668 (1942)] and Antares."). "The ‘original patent’ standard and the written description requirement are not the same. Where the written description requirement is based on what the skilled artisan would have understood was within the possession of the inventor, recent Federal Circuit case law indicates that the original patent requirement under § 251 requires something more." See Ex parte Sandwick, Appeal No. 2018-008369, op. at 22 (PTAB July 23, 2019) (Rejection under 35 U.S.C. 251 was affirmed because the patent did not describe any fabrication method other than casting. While one of ordinary skill in the art would have understood that other fabrication methods, such as injection molding or 3D printing, were possible or conventional, the reissue claims that did not include casting did not comply with the original patent requirement.) In addition, in comparison to Forum US, Inc. v. Flow Valve, the Examiner finds that nowhere does the written description or drawings disclose that non-volatile semiconductor storage devices are an optional feature of the invention. In this case, the specification must clearly and unequivocally disclose the newly claimed invention as a separate invention. That is, the specification must disclose the newly claimed invention (broader than non-volatile semiconductor storage device) as a separate invention. The Examiner notes that the Applicant has not pointed to any teaching within the specification that provides a memory device that is not a non-volatile semiconductor storage device. Therefore, the Applicant has not shown that the specification discloses the newly claimed invention as a separate invention. In addition, the Examiner notes that claim 19 is substantially the same as claim 19 of RE49274. The only difference is reciting “A semiconductor storage device” as opposed to “A non-volatile semiconductor storage device”. Thus, the Applicant intends to have a claim which covers a storage device that is broader than a non-volatile semiconductor storage device and which is broader than that disclosed in the underlying patent specification. As explained above and below, nothing in the original patent specification discloses any device other than a non-volatile semiconductor storage device. Therefore, the Examiner does not find the Applicant’s arguments persuasive. 35 U.S.C. § 112(a) The Applicant states that the drawings constitute part of the disclose of the patent and Figure 11 shows the dimension of the wiring. The Applicant states that the wiring are structures and, as such, inherently have a width in three dimensions. The Applicant states that Figure 11 clearly shows the widths in the horizontal and vertical directions of the portions of the wiring. The Applicant, in response to the Examiner statement that the disclosure “does not disclose that the drawings are to scale and further it is silent as to any dimensions” states that claim 30 recites relative dimensions and actual dimensions are not recited. The Examiner notes that with reference to Appeal 2021-005169, as relied upon by the Applicant, it is acknowledged that the claim was directed to relative dimensions. However, in Appeal 2021-005169, the Drawings were labels with “HW” and “Ww” and thus, provided a basis for showing a difference in dimensions—that is, an indication which contrasts the height and width. In contrast, there is no label or indication in Figure 11 of the underling application and as set forth below, the drawings are not disclosed as being drawn to scale nor does the specification disclose any relative dimension of the widths of the wiring. Therefore, the Examiner does not find that Applicant’s arguments persuasive as to this issue. With respect to ‘distance’, the Applicant referees to Figure 6B which shows the structure of a transfer transistor having a gate electronic 203 and wirings 301, CG(i) and 401. The Applicant states that Figure 6B has well-understood structure where wiring layers are provided above transistors for connection to the transistors and all of the wirings 301, CG(i) and 401 are above gate 203. The Applicant states that Figure 6B and 8 indicate that the wirings are metal layers in levels M0, M1, and M2 which are successively higher levels in the fabrication process. The Applicant states that the first-fourth wirings correspond to one of CGi, CGDi or 301a as each of these is connected to active regions 201a or 201b. The Applicant states that the distance between the substrate 11 and any part of the gate 203 is smaller than the distance between substrate 11 and CGi, CGDi or 301a. PNG media_image1.png 405 718 media_image1.png Greyscale PNG media_image2.png 498 689 media_image2.png Greyscale As shown in Figure 8, above, the Examiner notes that CGD is shown to be at level M2, and CG and 301a is shown on level M0. In addition, Figure 8 further illustrates that later M0 overlaps 203, thus, illustrating that level M0 is ‘above’ 203. As set forth in col. 5, lines 36-41, “[i]n FIG. 8, each wiring includes M0 wirings on the bottom layer, M1 wirings on the upper layer, and further M2 wirings on the top of the upper layer.” As set forth in claims 33, 36, and 37, the claims recite that the distance between the substrate and the common gate electrode of the first and second transistor is smaller than a distance between the substrate and the first, second, third and fourth wirings. As explained by the Applicant the first-fourth wirings correspond to one of CGi, CGDi or 301a and each of these are connected to active regions 201a or 201b. The Examiner notes that since the wiring layer (as shown above represented as layer M0) is above the gate electrode, then the Examiner finds persuasive the Applicant’s arguments that a distance between the substrate and the common gate electrode is smaller than a distance between the substrate and the first, second, third and fourth wirings. With respect to claim 40, the claim recites that a distance between the substrate and the fourth potion of the second wiring in the third direction is larger than a distance between the substrate and the firth portion of the second wiring in the third direction. The Examiner notes that since the second wiring, as explained above, is all in the same layer, it is not clear how the drawings support a difference in distance between a fourth and fifth portion of the second wiring since they are both on the same level/layer (M0). The Examiner notes that the ‘portion’ may correspond to vertical/horizontal however, the drawings are specific as to any height attributed to the wirings. Therefore, the Applicant’s arguments are persuasive as to claims 33, 36 and 37 but not persuasive to claim 40. The rejection to claim 40 will be maintained and the rejection to claims 33, 36, and 37 will be withdrawn (as it pertains to this specific issue). Terminal Disclaimer The terminal disclaimer filed on June 30, 2026, disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of RE50512, RE49274, RE47355, RE46526, RE45307 have been reviewed and is accepted. The terminal disclaimer has been recorded. Reissue Declaration The reissue oath/declaration filed with this application is defective (see 37 CFR 1.175 and MPEP § 1414) because of the following: The Examiner notes that the error upon which reissue is based is set forth as: Claim 1 of 7,911,844 recites a storage device with transfer transistors having diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Claim 19 recites a storage device having transfer transistors including a first transfer transistor comprising first and second active regions and a second transfer transistor comprising third and fourth active regions. Claim 19 does not recite that the first through fourth active regions function as source/drain layers1. The Examiner first notes that the statement “Claim 19 recites a storage device having transfer transistors including a first transfer transistor comprising first and second active regions and a second transfer transistor comprising third and fourth active regions” is not set forth in claim 19. The Examiner finds that claim 19 currently recites drain/source regions and therefore, the error statement is not reflected in the current claim set. In addition, the claim does not recite “third and fourth” active regions, rather the claim recites second drain/source regions. The Examiner acknowledges that new claim 30 recites a first transfer transistor with a first and second active region and a second transfer transistor with a third and fourth active region, however, the Applicant’s error statement is directed to claim 19. In addition, the stated error has already been corrected in a previous reissue. For example, if the error is directed to recited “active regions” as opposed to “source/drain layer”, RE50,512 recites a claim in which a transfer transistor comprises active region without the recitation of a source/drain layer. It is also noted that claim 19 of the instant reissue is similar to RE49274 since it recites source/drain layers for the transfer transistors. Thus, the Applicant has not identified an error being corrected by this instant reissue continuation application. Reissue Application – 35 U.S.C. 251 Claims 19-43 are rejected under 35 U.S.C. 251 as being in violation of the original patent requirement. Section 251 requires that reissue is for “the invention disclosed in the original patent.” In order to satisfy the original patent requirement, “[i]t must appear from the face of the instrument that what is covered by the reissue was intended to have been covered and secured by the original.” U.S. Indus. Chems., Inc. v. Carbide & Carbon Chems. Corp., 315 U.S. 668, 676 (1942). Furthermore, “it is not enough that an invention might have been claimed in the original patent because it was suggested or indicated in the specification.” Id. In other words, the original patent “must clearly and unequivocally disclose the newly claimed invention as a separate invention.” Antares Pharma, Inc. v. Medac Pharma Inc., 771 F.3d 1354, 1362 (Fed. Cir. 2014). In the present case, the original patent disclosed a non-volatile semiconductor storage device. This is set forth in the title of the patent, the abstract and each of the original claims (including claims as filed of the original application). In addition, col. 1, lines 16-19 recites: The present invention relates to a non-volatile semiconductor storage device, and, more particularly, a non-volatile semiconductor storage device including transfer transistors to transfer a high voltage. Col. 2, lines 3-4 recites: “One aspect of the present invention provides a non-volatile semiconductor storage device comprising: a memory cell array having memory cells arranged therein…” Col. 6, lines 37-40 recites: FIG. 9 is a plan view illustrating the wiring layout of the transfer transistors QNi provided in a non-volatile semiconductor storage device according to the second embodiment of the present invention. Col. 7, lines 4-7 recites: FIG. 10 is a plan view illustrating the wiring layout of the transfer transistors QNi provided in a non-volatile semiconductor storage device according to the third embodiment of the present invention. The Examiner maintains that for reissue claims, “the specification of the original patent must do more than merely suggest or indicate the invention recited in reissue claims; ‘[i]t must appear from the face of the instrument that what is covered by the reissue was intended to have been covered and secured by the original.’” Forum US, Inc. v. Flow Valve, LLC, 926 F.3d 1346, 1351–52 (Fed. Cir. 2019) (quoting U.S. Indus. Chems. Inc. v. Carbide & Carbon Chems. Corp., 315 U.S. 668, 676 (1942)) . As set forth in the current reissue claims, the claims are directed to a ‘semiconductor storage device’. The Examiner finds that it does not appear from the face of the original patent that applicant intended to cover and secure a ‘semiconductor storage device’ without it being a ‘non-volatile’ semiconductor storage device. As set forth above, each of the original claims of the underlying patent2, as well as the specification only discloses a non-volatile semiconductor storage device. Thus, the Examiner determines that the underlying patent does not clearly and unequivocally disclose any embodiment without a non-volatile semiconductor storage device, thus to broaden the claims to permit such an embodiment runs afoul of the original patent requirement. Claims 30-43 are rejected under 35 U.S.C. 251 as being based upon new matter added to the patent for which reissue is sought. The added material which is not supported by the prior patent is discussed below. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 30-43 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The Examiner notes that claim 30 recites, inter alia, “the first portion having a first width in the second direction, a second portion extending in the first direction between the first portion and the common gate electrode in the second direction, the second portion at least partially overlapping with the first active region when viewed in the third direction, the second portion having a second width in the second direction smaller than the first width, and a third portion extending in the second direction to electrically connect the first and second portions, the third portion having a third width in the first direction.” (emphasis added) The Examiner notes that the patent specification does not disclose any width associated with the wirings or that any portions of the wirings are smaller or bigger than other portions of wirings. The Examiner notes that the Applicant, in their June 6, 2025, response provides support for the claims by referencing Figures 5, 8 and 11. It was noted that the wirings are shown as CG in Figures 5, 8 and 11. The Examiner notes, however, in consideration of the cited drawings and the specification, the Applicant’s disclosure does not disclose that the drawings are to scale and further it is silent as to any dimensions. It is also noted that dependent claim 31 also recites “the third width is smaller than the first width”. As explained above, there is insufficient support for whether the drawings are drawn to scale and more specifically that any width is smaller than any other width. In addition, the Examiner finds that dependent claim 40 recites “a distance”. It is noted that although, col. 5, lines 32-35 discloses “distance between the wirings” and “other wirings” to prevent an increase in parasitic capacitance, it is not clear whether the disclosure provides specific teachings directed to “distance”. It is acknowledged that the drawings do have ‘distances’ between the wiring and thus a person of ordinary skill in the art would understand that there would be a distance between the wirings, however, since the drawings are not drawn to scale, there does not appear to be sufficient support for “a distance between the substrate and the fourth portion of the second wiring in the third direction is larger than a distance between the substrate and the fifth portion of the second wiring in the third direction.” (Claim 40). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ovidio Escalante whose telephone number is (571)272-7537. The examiner can normally be reached on Monday to Friday - 6:00 AM to 2:30 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Fuelling, can be reached at telephone number (571)272-7537. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /Ovidio Escalante/ Primary Examiner, Art Unit 3992 Conferees: /MATTHEW E HENEGHAN/Primary Examiner, Art Unit 3992 /M.F/Supervisory Patent Examiner, Art Unit 3992 1 The Examiner notes that the error statement further states that the claim does not recite that the “active regions” function as “source/drain layers”. It is noted that although “active region” is a broader phrase than “drain/source” region, the Applicant has not clearly shown support for active regions which do not function as a source/drain layers. 2 The Examiner also finds that each of the previous parent reissues (RE45307, RE46526, RE47355, RE49274, and RE50512) each recite a nonvolatile semiconductor storage device.
Read full office action

Prosecution Timeline

Jun 06, 2025
Application Filed
Jun 06, 2025
Response after Non-Final Action
Apr 09, 2026
Non-Final Rejection mailed — §112, §251
Jun 30, 2026
Response Filed
Aug 04, 2026
Final Rejection mailed — §112, §251 (current)

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
82%
With Interview (+5.8%)
2y 3m (~12m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 232 resolved cases by this examiner. Grant probability derived from career allowance rate.

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