Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2024-0088525, filed on 7/4/2024.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 4, and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2, 4, and 7 recites the limitation (or similar thereof) “output … to an outside of the memory device” in line 3, lines 5-6, and lines 2-3, respectively. The limitation, as drafted, renders the claim indefinite as it is unclear as to where the data is being output. Therefore, for the purposes of examination, the limitation is interpreted to mean “output to a circuit outside of the memory device”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention; or
Claims 11-12 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20240143182 A1).
Regarding claim 11, Lee teaches a memory controller configured to control a memory device including a plurality of planes (Paragraphs 62, 65; Fig. 1, rewritable nonvolatile memory module 43 includes a plurality of planes 701(0-P) and is controlled by memory management circuit 51), the memory controller comprising:
a command processor configured to generate an initial command-address for instructing a memory operation for the plurality of planes (Paragraphs 46, 50, 67; Fig. 7, memory management circuit 51 includes a microprocessor [command processor] which sends multiple read command sequences (containing an associated [initial-command] memory address) to the plurality of planes),
the command processor configured to generate an operation packet corresponding to each of the plurality of planes and the operation packet instructing data stored in a corresponding operation plane to be transmitted to the memory controller (Paragraphs 80, 82, 91; Fig. 7 and 9, memory management circuit 51 generates a direct memory access DMA command sequence [operation packet] which instructs the corresponding Planes(0-3) [including an operation plane] to send data to memory management circuit 51); and
a memory interface configured to, after the initial command-address is transmitted to the memory device, transmit the operation packet corresponding to each of the plurality of planes to the memory device according to a plane order in which data stored in each of the plurality of planes is output (Paragraphs 50, 80, 82, 91; Figs. 7 and 9, in response to a read command (including an associated [initial command] memory address) for rewritable non-volatile memory module 43, channel 71 [memory interface] transmits the direct memory access DMA command sequence [operation packet] to the corresponding Planes(0-3) which dictates the order in which data is send from the planes).
Regarding claim 12, Lee teaches the memory controller of claim 11, wherein the command processor is configured to add plane order information indicating the plane order to the operation packet (Paragraphs 82, 91; Figs. 7 and 9, memory management circuit 51 [command processor] generates a DMA command sequence [operation packet] which dictates the output order of planes Planes(0-3)).
Regarding claim 17, Lee teaches a memory system comprising: a memory controller configured to generate an initial command-address and operation packets respectively corresponding to a plurality of planes (Paragraphs 50, 80, 82, 91; Figs. 7 and 9, memory management circuit 51 generates read commands (including an associated [initial command] memory address) and a direct memory access DMA command sequence [operation packet(s)] which target a plurality of Planes(0-3)); and
a memory device configured to perform operations for the plurality of planes in response to the initial command-address and the operation packets (Paragraphs 50, 80, 82, 91; Figs. 7 and 9, rewritable non-volatile memory module 43 performs the read commands according to the [initial command] memory address and the DMA commands according to the DMA command sequence [operation packet(s)] on the plurality of Planes(0-3)),
wherein the memory device includes a memory cell array including the plurality of planes that include an initial plane, the initial plane including data (Paragraphs 42, 62, 91; Figs. 7 and 9, rewritable non-volatile memory module 43 consists of memory cells storing bits of data in multiple physical units, wherein the multiple physical units comprise planes, such as [initial] Plane(3)),
the memory device is configured to first output data of the initial plane (Paragraphs 82, 91; Figs. 7 and 9, rewritable non-volatile memory module 43 outputs plane data according to the DMA command sequence, the first of which is [initial] Plane(3)), and
a normal plane, the normal plane including data, the normal plane having a plane order after the initial plane (Paragraphs 82, 91; Fig. 9, the DMA command sequence includes [normal] Plane(2) after [initial] Plane(3)),
the memory device is configured to output data of the normal plane after outputting data of the initial plane (Paragraphs 82, 91; Figs. 7 and 9, rewritable non-volatile memory module 43 outputs plane data according to the DMA command sequence, the second of which is [normal] Plane(2)); and
an input/output circuit configured to temporarily receive and store data stored in the initial plane and the normal plane, based on the initial command-address (Paragraphs 50, 81, 91; Figs. 7 and 9, a buffer area [input/output circuit] of rewritable non-volatile memory module 43 temporarily stores data from read commands (including an associated [initial command] address) which target [initial] Plane(3) and [normal] Plane(2)), and
output data of an operation plane corresponding to the operation packet to the memory controller, based on the operation packet (Paragraphs 81-82, 91; Figs. 7 and 9, the buffer area sends stored data of [operation] Plane(2) to memory management circuit 51 [memory controller] based on the DMA command sequence [operation packet]).
Regarding claim 18, Lee teaches the memory system of claim 17, wherein the memory controller is configured to transmit the initial command-address to the memory device (Paragraphs 50, 91-92; Figs. 7 and 9, memory management circuit 51 sends a read command including an associated [initial command] memory address to rewritable non-volatile memory module 51), and
then transmit the operation packets respectively corresponding to the plurality of planes to the memory device according to the plane order (Paragraphs 91-92; Fig. 9, sending the DMA command sequences [operation packets] targeting Planes(0-3) according to the transmission order of the DMA commands).
Regarding claim 19, Lee teaches the memory system of claim 17, wherein the operation packet includes plane order information indicating the plane order for a subsequent plane,
the subsequent plane has a plane order in which the subsequent plane is after the operation plane (Paragraphs 91-92; Fig. 9, the DMA command sequence [operation packets including plane order] includes a DMA command DMA(3) for [subsequent] Plane(1), which is targeted after [operation] Plane(2)), and
the input/output circuit is configured to output data of the operation plane to the memory controller, based on the operation packets, during an operation period in which the data of the operation plane is output (Paragraphs 91-92; Figs. 7 and 9, the buffer area [input/output circuit] sends stored [operation] Plane(2) data to memory management circuit 51 based on the DMA command sequence [operation packets], during DMA(1-2) [operation period]), and
select data of the subsequent plane from among the data stored in the input/output circuit, based on the plane order information regarding the subsequent plane, in a subsequent operation period in which the data of the subsequent plane is output (Paragraphs 91-92; Figs. 7 and 9, sending [including selecting] stored [subsequent] Plane(1) data to memory management circuit 51 based on the DMA command sequence [including plane order information], during DMA(3) [subsequent operation period]).
Regarding claim 20, Lee teaches the memory system of claim 17, wherein the operation packet includes plane order information indicating the plane order for the operation plane (Paragraphs 91-92; Fig. 9, the DMA command sequence [operation packet] consists of an order of DMA commands, such as commands DMA(1-2) which target [operation] Plane(2)), and
the input/output circuit is configured to select data of the operation plane from among the data stored in the input/output circuit, based on the plane order information regarding the operation plane (Paragraphs 91-92; Fig. 9, the buffer area [input/output circuit] stores data read from [operation] Plane(2) and selects the read data in a subsequent DMA command, based on the DMA command sequence [including plane order information]), and
output the selected data to the memory controller during an operation period in which the data of the operation plane is output (Paragraphs 91-92; Figs. 7 and 9, sending Plane(2) data to memory management circuit 51 during DMA(1-2) [operation period]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-10 are rejected under 35 U.S.C 103 as being unpatentable over Sugahara (US 20210335398 A1) in view of Lee.
Regarding claim 1, Sugahara teaches a memory device comprising: a memory cell array including a plurality of planes (Paragraphs 38-39; Fig. 1, NAND flash memory 10 includes memory cell arrays 57A-B and planes PL0-1);
a plurality of first first-in first-out (FIFO) memories respectively corresponding to the plurality of planes and configured to store at least some pieces of data stored in the plurality of planes (Paragraphs 76, 82, 84; Fig. 4, FIFO circuits 14A-B are coupled to respective planes PL0-1 and store data from each respective plane),
a second FIFO memory (Paragraph 146; Fig. 9, FIFO circuit 14),
wherein the memory device is configured to store the data stored in each of the plurality of planes in a corresponding first FIFO memory of the plurality of first FIFO memories, respectively, based on an initial command-address provided from a memory controller (Paragraphs 78, 80, 82, 84; Figs. 1 and 4, FIFO circuits 14A-B store data from planes PL0-1 based on receiving a command CMD and address ADD from controller 90).
Sugahara does not explicitly teach a second memory configured to load at least some pieces of data stored in at least one of the plurality of first FIFO memories according to a plane order in which the data stored in the plurality of planes is output.
However, Lee teaches a second memory configured to load at least some pieces of data stored in at least one of the plurality of first FIFO memories according to a plane order in which the data stored in the plurality of planes is output (Paragraphs 80-82, 87; Fig. 4, buffer area [second memory] of rewritable non-volatile memory module 43 stores data read from a first and second plane (accessed by the first FIFO memories of Lee) reflecting the data transmission order of the plane read command sequence [plane order]).
Sugahara and Lee are analogous art because they are in the same field of endeavor, that being memory plane command management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Sugahara to further include the second memory and plane order information according to the teachings of Lee. The motivation for doing so would have been to improve the data reading performance of different planes (Lee, Paragraph 123).
Regarding claim 2, Sugahara teaches the memory device of claim 1, and the second FIFO memory (Paragraph 146; Fig. 9, FIFO circuit 14).
Sugahara does not explicitly teach wherein the memory device is configured to receive an operation packet for instructing that data loaded into the second memory is to be output to an outside of the memory device, and the memory device is configured to receive the operation packet after the initial command-address and includes plane order information indicating a plane order.
However, Lee teaches wherein the memory device is configured to receive an operation packet for instructing that data loaded into the second memory is to be output to an outside of the memory device (Paragraph 82; Fig. 4, in response to receiving a direct memory access DMA command sequence [operation packet], sending the data stored in the buffer area [second memory] to memory management circuit 51 (outside of rewritable non-volatile memory module 43)), and
the memory device is configured to receive the operation packet after the initial command-address and includes plane order information indicating a plane order (Paragraphs 50, 81; Fig. 9, the DMA command sequence [operation packet] is received after a read operation including an [initial command] address).
Sugahara and Lee are analogous art because they are in the same field of endeavor, that being memory plane command management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Sugahara to further include the second memory and plane order information according to the teachings of Lee. The motivation for doing so would have been to improve the data reading performance of different planes (Lee, Paragraph 123).
Regarding claim 3, Sugahara in view of Lee teaches the memory device of claim 2, wherein the operation packet includes the plane order information regarding an operation plane corresponding to the operation packet (Lee, Paragraphs 91-92; Fig. 9, the DMA command sequence [operation packet] includes an order of DMA commands DMA(0-5) [plane order] that includes commands DMA(1-2) that correspond to [operation] Plane(2))
Regarding claim 4, Sugahara teaches the memory device of claim 3, wherein the memory device is configured to load data of the plane from one of the plurality of first FIFO memories corresponding to the plane (Paragraphs 76, 82, 84; Fig. 4, FIFO circuits 14A-B store data from the respective planes PL0-1), and
the second FIFO memory (Paragraph 146; Fig. 9, FIFO circuit 14).
Sugahara does not explicitly teach wherein the memory device is configured to load data of the operation plane into the second memory, based on the plane order information, and the memory device is configured to output the data of the operation plane loaded in the second memory to outside of the memory device, based on the operation packet.
However, Lee teaches wherein the memory device is configured to load data of the operation plane into the second memory, based on the plane order information (Paragraphs 89, 91-92; Fig. 9, storing read data from second Plane(2) [operation plane] into the buffer area [second memory] based on the read command sequence), and
the memory device is configured to output the data of the operation plane loaded in the second memory to outside of the memory device, based on the operation packet (Paragraphs 89, 91-92; Figs. 7 and 9, sending [operation] Plane(2) data stored in buffer area [second memory] to memory management circuit 51 [outside of the memory device] based on the DMA command sequence [operation packet]).
Sugahara and Lee are analogous art because they are in the same field of endeavor, that being memory plane command management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Sugahara to further include the second memory and plane order information according to the teachings of Lee. The motivation for doing so would have been to improve the data reading performance of different planes (Lee, Paragraph 123).
Regarding claim 5, Sugahara in view of Lee teaches the memory device of claim 2, wherein the operation packet includes the plane order information regarding a subsequent plane, and the subsequent plane is a plane having a plane order following an operation plane corresponding to the operation packet (Lee, Paragraphs 91-92; Fig. 9, the DMA command sequence [operation packet] includes an order of DMA commands DMA(0-5) that includes command DMA(3), which corresponds to subsequent Plane(1) after [operation] Plane(2)).
Regarding claim 6, Sugahara teaches the memory device of claim 5, wherein the memory device is configured to load data of a plane from an initial first FIFO memory corresponding to the plane based on the initial command-address (Paragraphs 78, 80, 82, 84; Fig. 4, FIFO circuits 14A-B store data from the respective planes PL0-1 based on the received command CMD and address ADD), and
the second FIFO memory (Paragraph 146; Fig. 9, FIFO circuit 14).
Sugahara does not explicitly teach wherein the memory device is configured to load data of an initial plane to the second memory, and the initial plane is a plane of which the plane order is earliest among the plurality of planes.
However, Lee teaches wherein the memory device is configured to load data of an initial plane to the second memory (Paragraphs 89, 91-92; Fig. 9, storing read data from first Plane(3) [initial plane] into the buffer area [second memory]), and
the initial plane is a plane of which the plane order is earliest among the plurality of planes (Paragraphs 89, 91-92; Fig. 9, Plane(3) is the first in order of the command sequence).
Sugahara and Lee are analogous art because they are in the same field of endeavor, that being memory plane command management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Sugahara to further include the second memory and plane order information according to the teachings of Lee. The motivation for doing so would have been to improve the data reading performance of different planes (Lee, Paragraph 123).
Regarding claim 7, Sugahara teaches the memory device of claim 5, wherein the memory device is configured to load data of the plane from a subsequent first FIFO memory corresponding to the plane (Paragraphs 76, 82, 84; Fig. 4, FIFO circuits 14A-B store data from the respective planes PL0-1), and
the second FIFO memory (Paragraph 146; Fig. 9, FIFO circuit 14).
Sugahara does not explicitly teach wherein the memory device is configured to output data of the operation plane loaded in the second memory to outside of the memory device, based on the operation packet, and the memory device is configured to load data of the subsequent plane into the second memory, based on the plane order information.
However, Lee teaches wherein the memory device is configured to output data of the operation plane loaded in the second memory to outside of the memory device, based on the operation packet (Paragraphs 89, 91-92; Figs. 7 and 9, sending [operation] Plane(2) data stored in the buffer area [second memory] to memory management circuit 51 [outside of the memory device] based on the DMA command sequence [operation packet]), and
the memory device is configured to load data of the subsequent plane into the second memory, based on the plane order information (Paragraphs 89, 91-92; Fig. 9, storing data from [subsequent] Plane(1) into the buffer area based on the command sequence).
Sugahara and Lee are analogous art because they are in the same field of endeavor, that being memory plane command management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Sugahara to further include the second memory and plane order information according to the teachings of Lee. The motivation for doing so would have been to improve the data reading performance of different planes (Lee, Paragraph 123).
Regarding claim 9, Sugahara in view of Lee teaches the memory device of claim 2, wherein the memory device further includes a clock generator configured to control the first FIFO memories and the second FIFO memory (Sugahara, Paragraphs 85-86, 99, 101, 151; Figs. 4-5 and 9, write clock generator 35 and read clock generator 37 controls FIFO circuits 14A-B [first FIFO memories] and FIFO circuit 14 [second FIFO memory]), and
the clock generator is configured to generate a first clock signal for controlling the first FIFO memories, based on the initial command-address (Sugahara, Paragraphs 80, 82, 85-86, 99; Figs. 4-5, write clock generator 35 generates [first] write clock Wclk which controls the transmission of data RD0 in FIFO circuits 14A-B based on the command CMD and address ADD), and
generates a second clock signal for controlling the second FIFO memory (Sugahara, Paragraphs 101, 151; Figs. 5 and 9, read clock generator 37 generates a [second] read clock Rclk which controls FIFO circuit 14),
based on the operation packet (Lee, Paragraphs 91-92; Fig. 9, outputting data stored in the buffer area based on the DMA command sequence [operation packet]).
Regarding claim 10, Sugahara in view of Lee teaches the memory device of claim 2, wherein the memory device is configured to receive the initial command-address (Sugahara, Paragraphs 31-32, 35; Fig. 1, the command and address is sent by I/O signal DQ via a NAND [command-address] bus to NAND flash memory 10)
and the operation packet from the memory controller through a command-address bus (Lee, Paragraph 50; Fig. 4, command sequences [such as the operation packet] is sent through a [command-address] bus by memory management circuit 51 [controller]), and
transmit and receive the data to and from the memory controller through a data bus (Sugahara, Paragraphs 31-32, 35; Fig. 1, write/read data is transmitted to/from controller 90 via a NAND [also data] bus).
Claim 8 is rejected under 35 U.S.C 103 as being unpatentable over Sugahara in view of Lee as applied to claim 5 above, and further in view of Kim (US 20220129310 A1).
Regarding claim 8, Sugahara teaches the memory device of claim 5, and the second FIFO memory (Paragraph 146; Fig. 9, FIFO circuit 14).
Sugahara does not explicitly teach wherein the operation packet includes an operation execution packet for instructing to output the data loaded in the second memory and the operation packet includes an operation completion packet indicating an output completion of the data loaded in the second memory, and the operation completion packet includes the plane order information regarding the subsequent plane.
However, Lee teaches wherein the operation packet includes an operation execution packet for instructing to output the data loaded in the second memory (Paragraphs 91-92; Fig. 9, the DMA command sequence [operation packet] includes DMA commands DMA(0-3) [operation execution packets], which output the data stored in the buffer area [second memory]),
an output of the data loaded in the second memory (Paragraphs 91-92; Fig. 9, a DMA command outputs the data stored in the buffer area), and
the plane order information regarding the subsequent plane (Paragraphs 91-92; Fig. 9, DMA command sequence [plane order information] includes an order of DMA commands DMA(0-5) that includes command DMA(3), which corresponds to subsequent Plane(1) after [operation] Plane(2)).
Sugahara and Lee are analogous art because they are in the same field of endeavor, that being memory plane command management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Sugahara to further include the second memory and plane order information according to the teachings of Lee. The motivation for doing so would have been to improve the data reading performance of different planes (Lee, Paragraph 123).
Sugahara in view of Lee does not explicitly teach wherein the operation packet includes an operation completion packet indicating an output completion of the data, and the operation completion packet includes the plane order information regarding the subsequent plane.
However, Kim teaches wherein the operation packet includes an operation completion packet indicating an output completion of the data (Paragraphs 103-104; Fig. 11, steps S308-309, a command sequence includes transmitting completion information [packet] upon the complete transmission of Packet_C [data]), and
the operation completion packet includes the plane order information regarding the subsequent plane (Paragraphs 104, 109, the completion information [packet] includes plane status information for each plane (including a subsequent plane), which determines the output schedule [plane order] to planes).
Sugahara, Lee, and Kim are analogous art because they are in the same field of endeavor, that being memory plane command management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory device of Sugahara in view of Lee to further include the memory completion packet including plane order information according to the teachings of Kim. The motivation for doing so would have been to prevent resource starvation by amending an output schedule (plane order) based on received plane information (Kim, Paragraph 73).
Claims 13-16 are rejected under 35 U.S.C 103 as being unpatentable over Lee in view of Kim.
Regarding claim 13, Lee teaches the memory controller of claim 12, wherein the operation packet includes an operation execution packet for instructing to output data stored in an operation plane corresponding to the operation packet (Paragraphs 80, 91-92; Fig. 9, the DMA command sequence [operation packet] includes DMA commands [execution packet] DMA(1-2) which outputs data read from [operation] Plane(2)),
the output of data stored in the operation plane (Paragraphs 80, 91-92; Fig. 9, reading/outputting data from [operation] Plane(2)), and
the command processor (Paragraph 46; Fig. 7, memory management circuit 51 includes a microprocessor [command processor]).
Lee does not explicitly teach wherein the operation packet includes an operation completion packet indicating an output completion of the data, and the command processor is configured to add the plane order information to the operation completion packet.
However, Kim teaches the operation packet includes an operation completion packet indicating an output completion of data (Paragraphs 103-104; Fig. 11, steps S308-309, a command sequence includes transmitting completion information [packet] upon the complete transmission of Packet_C [data]), and
the command processor is configured to add the plane order information to the operation completion packet (Paragraphs 104, 109, the completion information [packet] includes plane status information for each plane, which determines the output schedule [plane order] to planes).
Lee and Kim are analogous art because they are in the same field of endeavor, that being memory plane command management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory controller of Lee to further include the memory completion packet including plane order information according to the teachings of Kim. The motivation for doing so would have been to prevent resource starvation by amending an output schedule (plane order) based on received plane information (Kim, Paragraphs 73, 104).
Regarding claim 14, Lee in view of Kim teaches wherein the command processor is configured to add the plane order information regarding a subsequent plane to the operation completion packet (Kim, Paragraphs 104, 109, the completion information [packet] includes plane status information for each plane (including a subsequent plane), which determines the output schedule [plane order] to planes), and
the subsequent plane has a plane order in which the subsequent plane is after the operation plane (Lee, Paragraphs 91-92; Fig. 9, [subsequent] Plane(1) is after [operation] Plane(2) in the command sequence).
Regarding claim 15, Lee teaches the memory controller of claim 12, wherein the operation packet includes an operation execution packet for instructing to output data stored in an operation plane corresponding to the operation packet (Paragraphs 80, 91-92; Fig. 9, the DMA command sequence [operation packet] includes DMA commands [execution packet] DMA(1-2) which outputs data read from [operation] Plane(2)),
the output of data stored in the operation plane (Paragraphs 80, 91-92; Fig. 9, reading/outputting data from [operation] Plane(2)), and
the command processor is configured to add the plane order information to the operation execution packet (Paragraphs 46, 82, 91-92; Fig. 9, memory management circuit 51 includes a microprocessor [command processor], which sends DMA commands [execution packet] DMA(1-5) that target Planes(0-2) according to a command sequence [plane order]).
Lee does not explicitly teach wherein the operation packet includes an operation completion packet indicating an output completion of the data.
However, Kim teaches the operation packet includes an operation completion packet indicating an output completion of data (Paragraphs 103-104; Fig. 11, steps S308-309, a command sequence includes transmitting completion information [packet] upon the complete transmission of Packet_C [data]).
Lee and Kim are analogous art because they are in the same field of endeavor, that being memory plane command management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory controller of Lee to further include the memory completion packet according to the teachings of Kim. The motivation for doing so would have been to prevent resource starvation by amending an output schedule (plane order) according to the completion information (Kim, Paragraphs 73, 104).
Regarding claim 16, Lee in view of Kim teaches the memory controller of claim 15, wherein the command processor is configured to add the plane order information regarding the operation plane to the operation execution packet (Lee, Paragraphs 46, 82, 91-92; Fig. 9, memory management circuit 51 includes a microprocessor [command processor], which sends DMA commands [execution packet] DMA(1-5) that target Planes(0-2) according to a command sequence [plane order]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
Park (US 20220027091 A1) teaches methods and devices for performing a multi-plane read operation using parallelized command sequences.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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