DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 25-44 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12050789; claims 1-24 of U.S. Patent No. 11520499; and claims 1-21 of U.S. Patent No. 12346579. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the issued patent make obvious the claims of the pending application in that the claims are directed to substantially the same subject matter as the parent case though not necessarily presented in the same sequential order or the same claim numbering as shown in the table below (for purposes of illustration rather than limitation).
Instant Application: 19,232,398
Patent: 12346579; 12050789; 11520499
Claim 25. A low-power system-on-chip comprising: an originating controller configured to initiate a memory transaction request, the memory transaction request including a source address; an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request; a fabric communicatively coupled to the originating controller and configured to perform a memory operation based on the memory transaction request; and a power controller communicatively coupled to the arbiter and at least one of the originating controller or the fabric, the power controller configured to: activate a path to the first memory device used to perform the memory operation, and deactivate the path to the first memory device; wherein the fabric is configured to perform the memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the path is activated and the memory transaction request includes a read request, and(b) sending data included in the memory transaction request to the memory storage locations when the path is activated and the memory transaction request includes a program request or a write request.
Claim 1. A low-power system-on-chip comprising: an originating controller configured to initiate a memory transaction request, the memory transaction request including a source address; an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request; a fabric communicatively coupled to the originating controller and configured to perform a memory operation based on the memory transaction request; and a power controller communicatively coupled to the arbiter and at least one of the originating controller or the fabric, the power controller configured to: selectively change a second memory bank from a first power mode to a second power mode in response to the fabric performing the memory operation on a first memory bank of the first memory device; wherein the fabric is configured to perform the memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program request or a write request.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Davis et al. (US 10,346,342) discloses a typical SoC including functionalities of a system integrated into a single chip including power management circuits, processors, memory interconnects, memory modules, memory controllers, memory mapping modules, arbiter, memory interface; AMBIQ, Datasheet, Apollo4 SoC; Ultra-Low Power Apollo SoC Family; DoC ID: DS-A4-1p4p0; Revision: 1.4.0, February 2025; discloses an ultra low-power, mixed-signal SoC designed for battery-powered devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARDOCHEE CHERY whose telephone number is (571)272-4246. The examiner can normally be reached 900-500.
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/MARDOCHEE CHERY/Primary Examiner, Art Unit 2133
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