DETAILED ACTION
The instant application having Application No. 19/232,467 has a total of 20 claims pending in the application, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application 19/232,467 filed 6/09/2025 is a Continuation of 18/496,699 filed 10/27/2023, now U.S. Patent #12353331.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/12/2026 is being considered by the examiner.
Claim Language
Claims 24 and 26 recite limitations which, as claimed, are conditionally executed without accounting for the possibility of the condition failing to trigger.
The limitations in the claims involving executing an action in response to a condition are not positively recited in the claims, as the limitations, as claimed, are conditionally executed without accounting for the possibility of the condition failing to occur. The method may never be required to execute the actions in the relevant limitations because the limitations include temporal conditional precedent(s) that may never be reached within the scope of the claim under the broadest reasonable interpretation. The examiner recommends amending the instances of limitations reliant on executing an action responsive to a condition to positively recite the occurrence(s) of the condition.
For example, for claim 24 reciting, “incrementing, by the kernel, the unique number in response to allocating an entry for a new element in the second data structure.”, the examiner suggests additionally including a limitation reciting that an entry for a new element is allocated in the second data structure.
Similarly, for claim 26 reciting, “determining whether the obtained element is set to an invalid status or a valid status; bypassing the registration process for the first address range responsive to determining that the obtained element is set to the valid status; and performing the registration process for the first address range responsive to determining that the obtained element is set to the invalid status.”, the examiner suggests additionally including limitations reciting that 1) the obtained element is determined to be set to the valid status, and 2) the obtained element is determined to be set to the invalid status
See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding “The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim”); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “processing resource” in claims 30 and 38.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim 30 contains one element which is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The element, “processing resource”, has been identified as “a processor” (specification: paragraphs 66, 87).
Claim 38 contains one element which is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The element, “processing resource”, has been identified as “a processor” (specification: paragraphs 66, 87).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6, 9-11 and 13 of U.S. Patent No. 12353331,Kuyel (US 20210255956 A1)
Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the co-pending applications disclose/obviate the claims on the instant application.
Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.
As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995.
Instant application 19/232,467
U.S. Patent #12353331 (corresponding to Application # 18/496,699)
21. (New) A method, comprising: receiving, from an application, a first command to register a first address range in a kernel, the first command including a cookie as an identifier for the first command; storing, in an entry in a first data structure, the first address range, the cookie, and an index of a corresponding element in a second data structure; creating, in the second data structure, an entry for the corresponding element, the entry comprising a unique number and a valid status; storing the index and the unique number in a cache entry in a user-space cache, the cache entry associated with the first address range; providing, by the kernel to the application, read-only access of the second data structure based on the cache entry; and bypassing a registration process for the first address range based on the index and the unique number stored in the cache entry.
24. (New) The method of claim 21, further comprising: generating, by the kernel, the unique number associated with the element; and incrementing, by the kernel, the unique number in response to allocating an entry for a new element in the second data structure.
28. (New) The method of claim 21, wherein the first data structure is associated with registration of address ranges; and wherein the second data structure is associated with at least one of a monitoring state window or an array indicating a monitoring state window.
29. (New) The method of claim 21, wherein the first command comprises a command to monitor the first address range in the kernel based on the kernel maintaining the second data structure with read-only access by the application and further based on the kernel maintaining first data structure.
1. A method, comprising:
performing a registration process for monitoring a respective address range, wherein the registration process comprises:
receiving, from an application, a first command to monitor a first address range in a kernel;
registering, in the kernel, the first address range;
creating a monitoring state window in the kernel, the monitoring state window indicating that the first address range is valid; and
providing, to the application, read-only access to the monitoring state window;
detecting, in the kernel based on a previous state of a mapping of virtual addresses to physical addresses, a change associated with a memory mapping of a second address range;
updating the monitoring state window by invalidating address ranges overlapping with the second address range; and
responsive to the first address range being valid, bypassing a subsequent registration process for the first address range;
wherein the registration process further comprises:
the first command including a cookie generated by the application as an identifier for the command;
storing, in an entry in a first data structure of the kernel, the first address range, an index of an element in a second data structure of the kernel, and the cookie;
allocating the element in the second data structure, the element comprising a unique number generated for the element and a status set to a valid state;
returning the index and the unique number to a cache in a user-space; and
storing the index and the unique number in a cache entry for the first address range.
3. The method of claim 1, further comprising:
determining, based on the index and the unique number in the cache entry, whether to bypass or perform the subsequent registration process for the first address range;
obtaining an element corresponding to the index by searching the second data structure based on the index and the unique number in the cache entry for the first address range;
performing a comparison of the unique number in the cache entry with a unique number in the obtained element;
determining, based on the comparison, that the unique number in the cache entry matches the unique number in the obtained element;
in response to a status of the obtained element being set to the valid state, determining that the first address range is valid and bypassing the subsequent registration process for the first address range; and
in response to the status of the obtained element being set to an invalid state, determining that the first address range is invalid and performing the registration process for the first address range.
22. (New) The method of claim 21, further comprising: detecting a mapping change associated with a second address range; searching, based on the second address range, the first data structure for address ranges overlapping with the second address range; setting elements in the second data structure corresponding to the overlapping address ranges to an invalid status; and deleting, from the first data structure, entries corresponding to the overlapping address ranges.
2. The method of claim 1,
wherein updating the monitoring state window comprises determining the address ranges overlapping with the second address range by searching the first data structure.
5. The method of claim 1, wherein responsive to detecting the change, the method further comprises:
identifying, in the first data structure, the address ranges overlapping with the second address range;
setting, in elements in the second data structure corresponding to the identified address ranges, a respective status to an invalid state; and
removing, from the first data structure, entries corresponding to the identified address ranges.
23. (New) The method of claim 22, wherein the mapping change is detected by a memory management system of an operating system associated with the kernel.
6. The method of claim 1, wherein detecting the change comprises:
receiving, from a memory management system of the kernel, a notification of the change associated with the memory mapping of the second address range.
25. (New) The method of claim 21, wherein bypassing the registration process for the first address range comprises determining whether the application is permitted to re-use the first address range by: identifying an element corresponding to the index by searching the second data structure based on the index and the unique number in the cache entry for the first address range; and determining whether the unique number in the cache entry matches the unique number in the identified element.
26. (New) The method of claim 25, further comprising: responsive to determining that the unique number in the cache entry matches the unique number in the identified element, determining whether the obtained element is set to an invalid status or a valid status; by passing the registration process for the first address range responsive to determining that the obtained element is set to the valid status; and performing the registration process for the first address range responsive to determining that the obtained element is set to the invalid status.
3. The method of claim 1, further comprising: determining, based on the index and the unique number in the cache entry, whether to bypass or perform the subsequent registration process for the first address range; obtaining an element corresponding to the index by searching the second data structure based on the index and the unique number in the cache entry for the first address range; performing a comparison of the unique number in the cache entry with a unique number in the obtained element; determining, based on the comparison, that the unique number in the cache entry matches the unique number in the obtained element; in response to a status of the obtained element being set to the valid state, determining that the first address range is valid and bypassing the subsequent registration process for the first address range; and in response to the status of the obtained element being set to an invalid state, determining that the first address range is invalid and performing the registration process for the first address range.
27. (New) The method of claim 21, further comprising: receiving, from the application, a second command to deregister the first address range in the kernel, the second command including a second cookie as an identifier for the second command; determining that the second cookie matches the cookie in the entry for the first address range in the first data structure; and deleting the entry for the first address range from the first data structure.
4. The method of claim 1, further comprising:
receiving a second command to perform a deregistration process, the second command including the first address range and a second cookie generated by the application as an identifier for the second command; and
removing, from the first data structure, the entry associated with the first address range responsive to the second cookie matching the cookie in the entry.
30. (New) A computer system, comprising: a processing resource; and a storage device storing instructions which when executed by the processing resource cause the processing resource to perform a method, the method comprising: receiving, from an application, a first command to register a first address range in a kernel, the first command including a cookie as an identifier for the first command; storing, in an entry in a first data structure, the first address range, the cookie, and an index of a corresponding element in a second data structure; creating, in the second data structure, an entry for the corresponding element, the entry comprising a unique number and a valid status; storing the index and the unique number in a cache entry in a user- space cache, the cache entry associated with the first address range; providing, by the kernel to the application, read-only access of the second data structure based on the cache entry; and bypassing a registration process for the first address range based on the index and the unique number stored in the cache entry.
33. (New) The computer system of claim 30, the method further comprising: generating, by the kernel, the unique number associated with the element; and incrementing, by the kernel, the unique number in response to allocating an entry for a new element in the second data structure.
36. (New) The computer system of claim 30, wherein the first data structure is associated with registration of address ranges; andwherein the second data structure is associated with at least one of a monitoring state window or an array indicating a monitoring state window.
37. (New) The computer system of claim 30, wherein the first command comprises a command to monitor the first address range in the kernel based on the kernel maintaining the second data structure with read-only access by the application and further based on the kernel maintaining first 6 data structure.
9. A computer system, comprising:
a processor; and
a storage device storing instructions to:
perform a registration process for monitoring a respective address range, wherein the registration process comprises:
registering, in a registration database of the kernel, the first address range in response to a request from an application; and
indicating that the first address range is valid in a monitoring state window which is a read-only data structure for the application;
determine, based on a command to re-use the first address range, whether to bypass a subsequent registration process for the first address range;
bypass the subsequent registration process for the first address range in response to the first address range being valid in the monitoring state window;
receive a notification of a change in a virtual-to-physical memory mapping associated with a second address range; and
invalidate, in the monitoring state window, address ranges overlapping with the second address range;
wherein the registration process further comprises:
receiving, from the application, a first command to monitor the first address range in a kernel, the first command including a cookie generated by the application as an identifier for the command;
storing, in an entry in a first data structure of the kernel, the first address range, an index of an element in a second data structure of the kernel, and the cookie;
allocating the element in the second data structure, the element comprising a unique number generated for the element and a status set to a valid state;
returning the index and the unique number to a cache in a user-space; and
storing the index and the unique number in a cache entry for the first address range.
11. The computer system of claim 9, determining whether to bypass the subsequent registration process for the first address range comprising:
determining, based on the index and the unique number in the cache entry, whether to bypass or perform the subsequent registration process for the first address range;
obtaining an element corresponding to the index by searching the second data structure based on the index and the unique number in the cache entry for the first address range;
determining that the unique number in the cache entry matches the unique number in the obtained element;
in response to a status of the obtained element being set to the valid state, determining that the first address range is valid and bypassing the subsequent registration process for the first address range; and
in response to the status of the obtained element being set to an invalid state, determining that the first address range is invalid and performing the subsequent registration process for the first address range.
31. (New) The computer system of claim 30, the method further comprising: detecting a mapping change associated with a second address range; searching, based on the second address range, the first data structure for address ranges overlapping with the second address range; setting elements in the second data structure corresponding to the overlapping address ranges to an invalid status; and deleting, from the first data structure, entries corresponding to the overlapping address ranges.
10. The computer system of claim 9, the instructions further to, prior to invalidating the address ranges overlapping with the second address range:
identify the address ranges overlapping with the second address range by searching the first data structure.
13. The computer system of claim 9, the instructions further to, responsive to receiving the notification of the change:
identify, in the first data structure, the address ranges overlapping with the second address range;
set, in elements in the second data structure corresponding to the identified address ranges, a respective status to an invalid state; and
remove, from the first data structure, entries corresponding to the identified address ranges.
32. (New) The computer system of claim 31, wherein the mapping change is detected by a memory management system of an operating system associated with the kernel.
1. A method, comprising:
performing a registration process for monitoring a respective address range, wherein the registration process comprises:
receiving, from an application, a first command to monitor a first address range in a kernel;
registering, in the kernel, the first address range;
creating a monitoring state window in the kernel, the monitoring state window indicating that the first address range is valid; and
providing, to the application, read-only access to the monitoring state window;
detecting, in the kernel based on a previous state of a mapping of virtual addresses to physical addresses, a change associated with a memory mapping of a second address range;
updating the monitoring state window by invalidating address ranges overlapping with the second address range; and
responsive to the first address range being valid, bypassing a subsequent registration process for the first address range;
wherein the registration process further comprises:
the first command including a cookie generated by the application as an identifier for the command;
storing, in an entry in a first data structure of the kernel, the first address range, an index of an element in a second data structure of the kernel, and the cookie;
allocating the element in the second data structure, the element comprising a unique number generated for the element and a status set to a valid state;
returning the index and the unique number to a cache in a user-space; and
storing the index and the unique number in a cache entry for the first address range.
6. The method of claim 1, wherein detecting the change comprises:
receiving, from a memory management system of the kernel, a notification of the change associated with the memory mapping of the second address range.
34. (New) The computer system of claim 30 wherein bypassing the registration process for the first address range comprises determining whether the application is permitted to re-use the first address range by: identifying an element corresponding to the index by searching the second data structure based on the index and the unique number in the cache entry for the first address range; and determining whether the unique number in the cache entry matches the unique number in the identified element.
35. (New) The computer system of claim 34, the method further comprising: responsive to determining that the unique number in the cache entry matches the unique number in the identified element, determining whether the obtained element is set to an invalid status or a valid status; bypassing the registration process for the first address range responsive to determining that the obtained element is set to the valid status; and performing the registration process for the first address range responsive to determining that the obtained element is set to the invalid status.
11. The computer system of claim 9, determining whether to bypass the subsequent registration process for the first address range comprising:
determining, based on the index and the unique number in the cache entry, whether to bypass or perform the subsequent registration process for the first address range;
obtaining an element corresponding to the index by searching the second data structure based on the index and the unique number in the cache entry for the first address range;
determining that the unique number in the cache entry matches the unique number in the obtained element;
in response to a status of the obtained element being set to the valid state, determining that the first address range is valid and bypassing the subsequent registration process for the first address range; and
in response to the status of the obtained element being set to an invalid state, determining that the first address range is invalid and performing the subsequent registration process for the first address range.
38. (New) A non-transitory computer-readable medium storing instructions which when executed by a processing resource cause the processing resource to perform a method, the method comprising: receiving, from an application, a first command to register a first address range in a kernel, the first command including a cookie as an identifier for the first command; storing, in an entry in a first data structure, the first address range, the cookie, and an index of a corresponding element in a second data structure; creating, in the second data structure, an entry for the corresponding element, the entry comprising a unique number and a valid status; storing the index and the unique number in a cache entry in a user-space cache, the cache entry associated with the first address range; providing, by the kernel to the application, read-only access of the second data structure based on the cache entry; and bypassing a registration process for the first address range based on the index and the unique number stored in the cache entry.
40. (New) The non-transitory computer-readable medium of claim 38, wherein the first data structure is associated with registration of address ranges; wherein the second data structure is associated with at least one of a monitoring state window or an array indicating a monitoring state window; and wherein the first command comprises a command to monitor the first address range in the kernel based on the kernel maintaining the second data structure with read-only access by the application and further based on the kernel maintaining first data structure.
9. A computer system, comprising:
a processor; and
a storage device storing instructions to:
perform a registration process for monitoring a respective address range, wherein the registration process comprises:
registering, in a registration database of the kernel, the first address range in response to a request from an application; and
indicating that the first address range is valid in a monitoring state window which is a read-only data structure for the application;
determine, based on a command to re-use the first address range, whether to bypass a subsequent registration process for the first address range;
bypass the subsequent registration process for the first address range in response to the first address range being valid in the monitoring state window;
receive a notification of a change in a virtual-to-physical memory mapping associated with a second address range; and
invalidate, in the monitoring state window, address ranges overlapping with the second address range;
wherein the registration process further comprises:
receiving, from the application, a first command to monitor the first address range in a kernel, the first command including a cookie generated by the application as an identifier for the command;
storing, in an entry in a first data structure of the kernel, the first address range, an index of an element in a second data structure of the kernel, and the cookie;
allocating the element in the second data structure, the element comprising a unique number generated for the element and a status set to a valid state;
returning the index and the unique number to a cache in a user-space; and
storing the index and the unique number in a cache entry for the first address range.
11. The computer system of claim 9, determining whether to bypass the subsequent registration process for the first address range comprising:
determining, based on the index and the unique number in the cache entry, whether to bypass or perform the subsequent registration process for the first address range;
obtaining an element corresponding to the index by searching the second data structure based on the index and the unique number in the cache entry for the first address range;
determining that the unique number in the cache entry matches the unique number in the obtained element;
in response to a status of the obtained element being set to the valid state, determining that the first address range is valid and bypassing the subsequent registration process for the first address range; and
in response to the status of the obtained element being set to an invalid state, determining that the first address range is invalid and performing the subsequent registration process for the first address range.
39. (New) The non-transitory computer-readable medium of claim 38, the method further comprising: detecting a mapping change associated with a second address range, wherein the mapping change is detected by a memory management system of an operating system associated with the kernel; searching, based on the second address range, the first data structure for address ranges overlapping with the second address range; setting elements in the second data structure corresponding to the overlapping address ranges to an invalid status; and deleting, from the first data structure, entries corresponding to the overlapping address ranges.
10. The computer system of claim 9, the instructions further to, prior to invalidating the address ranges overlapping with the second address range:
identify the address ranges overlapping with the second address range by searching the first data structure.
13. The computer system of claim 9, the instructions further to, responsive to receiving the notification of the change:
identify, in the first data structure, the address ranges overlapping with the second address range;
set, in elements in the second data structure corresponding to the identified address ranges, a respective status to an invalid state; and
remove, from the first data structure, entries corresponding to the identified address ranges.
Regarding claims 24 and 33, U.S. Patent #12353331 discloses all limitations except for incrementing the unique number in response to allocating an element in a data structure. However, Kuyel (US 20210255956 A1) teaches table entry comprising unique identifiers, wherein addition of a new table entry results in the identifier being assigned in an incremental manner (para. 79).
U.S. Patent #12353331 and Kuyel are analogous to the claimed invention because they are in the same field of endeavor involving data storage.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #12353331 and Kuyel, to modify the disclosures by U.S. Patent #12353331 to include disclosures by Kuyel since they both teach data storage and host mapping table, wherein Kuyel is directed towards improved access latency (para. 2-5). Therefore, it would be applying a known technique (addition of a new table entry resulting in a corresponding unique identifier being assigned in an incremental manner) to a known device (memory device having a data structure comprising entries with unique identifiers) ready for improvement to yield predictable results (memory device having a data structure comprising entries with unique identifiers that are incrementally assigned for each new table entry created; doing so would provide for means for more efficiently generating the unique identifiers for the entries). MPEP 2143
Regarding claims 25 and 34, U.S. Patent #12353331 discloses all limitations except for bypassing address registration in association with determining the address can be reused. However, Venkumahanti et al. (US 20090216993 A1) teaches, responsive to tag array data, comprising way information relating to physical memory address, being valid, reusing the tag array data in lieu of performing a tag array data lookup operation (para. 58, 39).
U.S. Patent #12353331 and Venkumahanti are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #12353331 and Venkumahanti, to modify the disclosures by U.S. Patent #12353331 to include disclosures by Venkumahanti since they both teach data storage and memory access, wherein Venkumahanti is directed towards reducing overall power consumption by reducing tag array and/or TLB lookup operations (para. 9-10). Therefore, it would be applying a known technique (responsive to tag array data, comprising way information relating to physical memory address, being valid, reusing the tag array data in lieu of performing a tag array data lookup operation) to a known device (system for bypassing address registration in association with the registered address being valid) ready for improvement to yield predictable results (system for bypassing address registration in association with the registered address being valid, where the valid registered address may be reused in lieu of performing a new registration in order to provide for improved access latency). MPEP 2143
The double patenting rejection above applies to claims 21-40.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Jiang et al. (US 20190057040 A1) teaches a control unit for translating a virtual address into physical addresses corresponding to a user space and a kernel space.
Archer et al. (US 8527734 B2) teaches an operating system maintaining a watch list of registered virtual address ranges, where a change in physical-to-virtual mapping for a virtual address range in the watch list results in operating system notifying a message passing module.
Blake et al. (US 10649684 B2) teaches monitoring memory address spaces for change in data stored therein.
Conclusion
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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