DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 11-15 and 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Ootomo (US 2023/0409202), Kim et al. (US 2015/0143033), Syu et al. (US 8,751,728).
Regarding claim 1, Ootomo discloses:
A memory system, comprising:
one or more memory devices (FIG. 1 Memory Chips); and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to (FIG. 1 Memory Controller):
receive an indication of a quantity of data to be written to the memory system as part of a first programming…(FIG. 5 S304 Is size information contained in command sequence of target? Yes; [0064] After that, the memory controller MC transfers the command sequence for the data-in operation including the size information to the bridge chip BC (S103));
store the indication to a first register of the memory system in response to receiving the indication (FIG. 5 S305 Store size information indicating page size in register; [0065] In the bridge chip BC, when the size information is received from the memory controller MC, the controller 103 stores the received size information in the register 113 (S104));
receive, in response to storing the indication to the first register, a portion of the data to be written to the memory system (FIG. 5 S310 Start data transfer; [0069] Then, the bridge chip BC transfers the write data as the data signal DQ[7:0] and toggles the data strobe signal DQS (S110));
write the portion of the data to the memory system using the first programming…in response to receiving the portion of the data (FIG. 5 S310 Start data transfer; [0070] The memory chip CP1 stores the data received from the bridge chip BC in the data cache 203); and
modify, in response to writing the portion of the data to the memory system, a value (FIG. 5 S311 Count amount of transfer data using counter)…
Ootomo does not appear to explicitly teach a programming “mode” and a value “stored to the first register.” However, Kim et al. disclose:
a programming mode ([0113] FIG. 12 is a diagram illustrating a method of selecting supportable write modes of a memory device)
Ootomo and Kim et al. are analogous art because Ootomo teach high efficiency data transfer and Kim et al. teach setting write operation speeds.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ootomo and Kim et al. before him/her, to modify Ootomo’s teachings of data transfer commands with the Kim et al. teachings of different write (i.e., programming) modes because a write mode would enable improvement in write performance while securing data reliability (Kim et al. [0079]).
Ootomo and Kim et al. do not appear to explicitly teach modifying a value “stored to the first register.” However, Syu et al. disclose:
[modify…a value] stored to the first register (FIG. 2A step 205 Decrement Register)
Ootomo, Kim et al., and Syu et al. are analogous art because Ootomo teach high efficiency data transfer; Kim et al. teach setting write operation speeds; and Syu et al. teach bus transfer optimization.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ootomo, Kim et al., and Syu et al. before him/her, to modify the combined teachings of Ootomo and Kim et al. with the Syu et al. teachings of decrementing the value stored in the register because doing so would trach the amount of data remaining to be transferred to the memory system.
Regarding claim 2, Syu et al. further disclose:
The memory system of claim 1, wherein modifying the value stored to the first register comprises the processing circuitry configured to cause the memory system to:
decrement the value stored to the first register in response to writing the portion of the data to the memory system (FIG. 2A step 205 Decrement Register).
Regarding claim 3, Kim et al. further disclose:
The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
disable the first programming mode ([0063] FIG. 4 is a flowchart illustrating a pre-SMT write step in the method of FIG. 1; FIG. 4 S280 Second register setting; [0067] In step S280, computing device 100 sets nonvolatile memory device 200 with information indicating an end of the pre-SMT write operation. Afterwards, the pre-SMT write operation may be ended)…
The combination of Ootomo and Kim et al. do not appear to teach “in accordance with the value satisfying a threshold value after decrementing the value.” However, Syu et al. further disclose:
in accordance with the value satisfying a threshold value after decrementing the value (FIG. 2A Register Zero?; Col 2, line 66-Col 3, line 2: If the value of the register is zero, this means that all blocks of data have been transferred for this command and the processing ends for the multiple block read or write command).
Regarding claim 4, Kim et al. further disclose:
The memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to:
write second data to the memory system using a second programming mode in response to disabling the first programming mode (FIG. 1 B300 Post-SMT writing; [0075] FIG. 6 is a flowchart illustrating a post-SMT write step in the method of FIG.).
Regarding claim 11, Ootomo further discloses:
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
transmit the value stored to the first register (FIG. 5 S305 Store size information indicating page size in register; [0065] In the bridge chip BC, when the size information is received from the memory controller MC, the controller 103 stores the received size information in the register 113 (S104)).
Claims 12-15 and 22-25 recite limitations substantially similar to the limitations of claims 1-4 and 11. Therefore, claims 12-15 and 22-25 are rejected under the same rationale as claims 1-4 and 11.
Claims 5-6 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ootomo, Kim et al., and Syu et al. as applied to claim 1 above, and further in view of Eguchi et al. (US 2016/0062896).
Regarding claim 5, the combination of Ootomo, Kim et al., and Syu et al. further disclose:
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
determine a maximum quantity of data capable of being written using the first programming mode indicated by a first value stored to a…register (Ootomo discloses: [0034] The register 113 is a memory that stores various information for controlling the operation of the bridge chip BC), wherein the quantity of data is less than or equal to the maximum quantity of data (Kim et al. disclose: [0077] a register setting operation about memory 1300 may be performed in step S320. As described above, memory 1300 supports a variety of write modes. Download speeds respectively corresponding to the write modes may be different from one another. Each write mode may be decided considering data reliability, write performance, size of data to be downloaded, etc.; FIG. 12; [0115]-[0116]).
Kim et al. do not disclose that the table of Fig. 12 is “a second register.” However, Eguchi et al. disclose:
a second register (FIG. 3, [0044], [0052])
Ootomo, Kim et al., and Syu et al. are analogous art because Ootomo teach high efficiency data transfer; Kim et al. teach setting write operation speeds; Syu et al. teach bus transfer optimization; and Eguchi et al. teach decreasing latency in a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ootomo, Kim et al., Syu et al., and Eguchi et al. before him/her, to modify the combined teachings of Ootomo, Kim et al., and Syu et al. with the Eguchi et al. teachings of a mode (i.e., second) register because implementing a second register would enable the storage of the parameter indicating the maximum quantity of data capable of being written using the first programming mode.
Regarding claim 6, Kim et al. further disclose:
The memory system of claim 5, wherein the processing circuitry is further configured to cause the memory system to:
modify the first value to indicate an updated maximum quantity of data capable of being written using the first programming mode ([0115] computing device 2000 may perform a register setting operation about a memory device 1300; It would be obvious to one skilled in the art before the effective filing date to use a register setting operation to update the maximum quantity of data capable of being written using the first programming mode. Such a modification would have amounted to little more than combining “familiar elements according to known methods” and would have been obvious because it would have done “no more than yield predictable results.” (MPEP 2143 I.A.) Updating values stored in a register is a common technique for reflecting changes to the stored value and would have yielded the predictable result of storing the updated maximum quantity of data capable of being written using the first programming mode.).
Claims 16 and 17 recite limitations substantially similar to the limitations of claims 5-6. Therefore, claims 16 and 17 are rejected under the same rationale as claims 5-6.
Claims 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ootomo, Kim et al., and Syu et al. as applied to claim 1 above, and further in view of Wu et al. (US 2025/0252042).
Regarding claim 10, Ootomo, Kim et al., and Syu et al. do not appear to explicitly teach while Wu et al. disclose:
The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
detect a power cycle at the memory system ([0044] resetting the volatile register at a beginning of a power cycle);
modify the value stored to the first register in response to detecting the power cycle ([0031] volatile register can be configured to reset at a beginning of a power cycle); and
disable the first programming mode in response to modifying the value (It would be obvious to one skilled in the art before the effective filing date that the first programming mode is disabled when the register is reset as a result of a power cycle because the register is a volatile memory device).
Ootomo, Kim et al., and Syu et al. are analogous art because Ootomo teach high efficiency data transfer; Kim et al. teach setting write operation speeds; Syu et al. teach bus transfer optimization; and Wu et al. teach memory device management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ootomo, Kim et al., Syu et al., and Wu et al. before him/her, to modify the combined teachings of Ootomo, Kim et al., and Syu et al. with the Wu et al. teachings of power cycles in order to implement a reset procedure at the volatile register when the system experiences a power cycle, which would cause the volatile memory to lose its stored data. The combination would reset the volatile register after a power cycle.
Claim 21 recites limitations substantially similar to the limitations of claim 10. Therefore, claim 21 is rejected under the same rationale as claim 10.
Allowable Subject Matter
Claims 7-9 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the examiner’s statement of reasons for allowance:
While one or more reasons are offered below citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Ootomo, Kim et al., and Syu et al., when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Regarding claim 7, the prior art, alone or in combination, does not disclose the following highlighted limitations, as claimed, in combination with the other claimed limitations:
“The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine whether the memory system is configured to operate using the first programming mode in accordance with a value stored to a third register of the memory system, wherein receiving the quantity of data is in accordance with the value stored to the third register.”
Claims 8 and 9 would be allowable based on their dependency from an allowed base claim. Claims 18-20 recite limitations substantially similar to the limitations of claims 7-9. Therefore, claims 18-20 would be allowable under the same rationale as claims 7-9.
Conclusion
The prior art made of record and not relied upon, Achtenberg et al. (US 2018/0025776), is considered pertinent to applicant's disclosure because it teaches programming modes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P. Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137
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