DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Application 19/232611 filed on June 9, 2025 in which Claims 1-20 are presented for examination.
Status of Claims
Claims 1-20 are pending, of which claims 1-20 are rejected under Double Patenting. Claims 18 and 19 are rejected under 101. Claims 1-20 do not have a prior art rejection.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
The claimed invention is directed to non-statutory subject matter.
As per claims 18 and 19, the claimed system has been read in view of applicant’s specification (see paragraph 104). The claimed apparatus appears to include elements which could be interpreted as including only software. Software is not one of the four categories of invention and therefore these claims are not statutory. Software is not a series of steps or acts and thus is not a process. Software is not a physical article or object and as such is not a machine or manufacture. Software is not a combination of substances and therefore not a composition of matter.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1- 20 of the instant application are rejected on the ground of obviousness-type nonstatutory double patenting as being unpatentable over Claims 1-20 of U.S. Patent No. US 12,326,778. Although the claims at issue are not identical, they are not patentably distinct from each other because the aforementioned claims of the instant application are rejected based on obviousness-type double patenting with regards to the aforementioned parent patent.
The following table summarizes claim mappings associated with the obviousness-type double patenting rejections:
12,326,778 (18/607880)
19/232611
1. A method of allocating memory to be accessed during the processing of a first task and a second task, the first task and the second task being duplicates, the method comprising: allocating a first block of memory configured to store read-write data to be accessed during the processing of the first task; allocating a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task; and allocating a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task.
1. A method of processing of a first task and a second task, the first task and the second task being duplicates, the method comprising: storing read-write data, wherein the stored read-write data is accessible during the processing of the first task; storing a copy of the read-write data, wherein the stored copy of the read-write data is accessible during the processing of the second task; and storing read-only data, wherein the stored read-only data is accessible during the processing of both the first task and the second task
2. The method of claim 1, comprising duplicating an input task so as to form the first task and the second task.
2. The method of claim 1, comprising duplicating an input task so as to form the first task and the second task.
3. The method of claim 2, wherein duplicating the input task comprises invoking the input task for processing twice without creating a copy of the input task.
3. The method of claim 2, wherein duplicating the input task comprises invoking the input task for processing twice without creating a copy of the input task.
4. The method of claim 1, wherein the second task is defined by a copy of each instruction or line of code defining the first task.
4. The method of claim 1, wherein the second task is defined by a copy of each instruction or line of code defining the first task.
5. The method of claim 1, further comprising, prior to processing the first and second task, storing read-write data at a memory address of the first block of memory and storing a copy of that read- write data at a corresponding memory address of the second block of memory.
5. The method of claim 1, wherein the read-write data is stored in a first block of memory, the copy of the read-write data is stored in a second block of memory, and the method further comprises, prior to processing the first and second task, storing read-write data at a memory address of the first block of memory and storing a copy of that read-write data at a corresponding memory address of the second block of memory.
6. The method of claim 1, wherein the first block of memory and the second block of memory are allocated in a heap of memory, each memory address of the second block of memory being offset from a corresponding memory address in the first block of memory by a fixed memory address stride.
6. The method of claim 1, wherein the read-write data is stored in a first block of memory, the copy of the read-write data is stored in a second block of memory, and the first block of memory and the second block of memory are allocated in a heap of memory, each memory address of the second block of memory being offset from a corresponding memory address in the first block of memory by a fixed memory address stride.
7. The method of claim 6, wherein the first task and second task are duplicates of an input task, and wherein a plurality of input tasks are processed at the processing system and the fixed memory address stride is the same for each pair of first and second tasks that are duplicates of the respective input tasks.
7. The method of claim 6, wherein the first task and second task are duplicates of an input task, and wherein a plurality of input tasks are processed at a processing system and the fixed memory address stride is the same for each pair of first and second tasks that are duplicates of the respective input tasks.
8. The method of claim 6, wherein the fixed memory address stride is half the size of the heap of memory.
8. The method of claim 6, wherein the fixed memory address stride is half the size of the heap of memory.
9. The method of claim 1, the method further comprising processing the first task and the second task at processing logic of a processing system so as to, respectively, generate first and second outputs.
9. The method of claim 1, the method further comprising processing the first task and the second task at processing logic of a processing system so as to, respectively, generate first and second outputs.
10. The method of claim 9, wherein the processing logic comprises a first processing element and a second processing element, wherein said processing the first task and the second task at processing logic of the processing system comprises processing the first task at the first processing element and processing the second task at the second processing element.
10. The method of claim 9, wherein the processing logic comprises a first processing element and a second processing element, wherein said processing the first task and the second task at processing logic of the processing system comprises processing the first task at the first processing element and processing the second task at the second processing element.
11. The method of claim 9, further comprising: receiving the second output; identifying, in the second output, a reference to a memory address in the first block of memory; updating that reference; and accessing, using the updated reference, the corresponding memory address in the second block of memory.
11. The method of claim 9, wherein the read-write data is stored in a first block of memory, the copy of the read-write data is stored in a second block of memory, and the method further comprises: receiving the second output; identifying, in the second output, a reference to a memory address in the first block of memory; updating that reference; and accessing, using the updated reference, a corresponding memory address in the second block of memory.
12. The method of claim 11, wherein the first block of memory and the second block of memory are allocated in a heap of memory, each memory address of the second block of memory being offset from a corresponding memory address in the first block of memory by a fixed memory address stride, the method further comprising using the fixed memory address stride to update the reference, in the second output, to a memory address in the first block of memory.
12. The method of claim 11, wherein the first block of memory and the second block of memory are allocated in a heap of memory, each memory address of the second block of memory being offset from a corresponding memory address in the first block of memory by a fixed memory address stride, the method further comprising using the fixed memory address stride to update the reference, in the second output, to a memory address in the first block of memory.
13. The method of claim 9, further comprising: submitting, concurrently, the first task and the second task to the processing logic.
13. The method of claim 9, the method further comprising: submitting, concurrently, the first task and the second task to the processing logic.
14. The method of claim 9, wherein the first and second outputs comprise intermediate outputs generated during the processing of, respectively, the first and second tasks, and optionally wherein an intermediate output is one or more of a load, store or atomic instruction generated during the processing of a task.
14. The method of claim 9, wherein the first and second outputs comprise intermediate outputs generated during the processing of, respectively, the first and second tasks, and optionally wherein an intermediate output is one or more of a load, store or atomic instruction generated during the processing of a task.
15. The method of claim 9, the method further comprising: forming first and second signatures which are characteristic of, respectively, the first and second outputs; comparing the first and second signatures; and raising a fault signal if the first and second signatures do not match.
15. The method of claim 9, the method further comprising: forming first and second signatures which are characteristic of, respectively, the first and second outputs; comparing the first and second signatures; and raising a fault signal if the first and second signatures do not match.
16. The method of claim 15, the method further comprising forming the first and second signatures prior to the first and second outputs accessing a memory hierarchy of the processing system.
16. The method of claim 15, the method further comprising forming the first and second signatures prior to the first and second outputs accessing a memory hierarchy of the processing system
17. The method of claim 1, further comprising: fetching data from the first, second and third blocks of memory into a cache configured to be accessed by processing logic during the processing of the first task and the second task.
17. The method of claim 1, wherein the read-write data is stored in a first block of memory, the copy of the read-write data is stored in a second block of memory, the read-only data is stored in a third block of memory, and the method further comprises: fetching data from the first, second and third blocks of memory into a cache configured to be accessed by processing logic during the processing of the first task and the second task.
18. A processing system configured to allocate memory to be accessed during the processing of a first task and a second task, the first task and the second task being duplicates, comprising: a memory; and a memory allocation unit configured to allocate memory in the memory, including a first block of memory in the memory configured to store read-write data to be accessed during the processing of the first task, a second block of memory in the memory configured to store a copy of the read- write data to be accessed during the processing of the second task, and a third block of memory in the memory configured to store read-only data to be accessed during the processing of both the first task and the second task.
18. A processing system configured to process a first task and a second task, the first task and the second task being duplicates, the processing system comprising a memory, the processing system being configured to: store read-write data in the memory, wherein the stored read-write data is accessible during the processing of the first task; store a copy of the read-write data in the memory, wherein the stored copy of the read-write data is accessible during the processing of the second task; and store read-only data in the memory, wherein the stored read-only data is accessible during the processing of both the first task and the second task.
19. The processing system of claim 18, wherein the processing system further comprises processing logic configured to process the first task so as to generate a first output, and to process the second task so as to generate a second output.
19. The processing system of claim 18, wherein the processing system further comprises processing logic configured to process the first task so as to generate a first output, and to process the second task so as to generate a second output.
20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processing system configured to allocate memory to be accessed during the processing of a first task and a second task, the first task and the second task being duplicates, wherein the processing system comprises: a memory allocation unit configured to allocate memory, including a first block of memory configured to store read-write data to be accessed during the processing of the first task, a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task, and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task.
20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processing system configured to process a first task and a second task, the first task and the second task being duplicates, the processing system comprising a memory, the processing system being configured to: store read-write data in the memory, wherein the stored read-write data is accessible during the processing of the first task; store a copy of the read-write data in the memory, wherein the stored copy of the read-write data is accessible during the processing of the second task, and store read-only data in the memory, wherein the stored read-only data is accessible during the processing of both the first task and the second task.
The claims of US Patent No. 12,326,778 do not explicitly teach allocating memory blocks.
However, Armangau et al. (US Patent Application 2005/0015663) teaches allocating memory blocks, in Paragraph 236.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine the claims of US Patent No. 12,326,778 with allocating memory blocks for the purpose of storing data.
Claims 1, 5-8 and 10-20 of the instant application are rejected on the ground of obviousness-type nonstatutory double patenting as being unpatentable over Claims 1-5, 7, 8, 10, 11, 13, 16-19 and 21 of U.S. Patent No. US 11,934,257. Although the claims at issue are not identical, they are not patentably distinct from each other because the aforementioned claims of the instant application are rejected based on obviousness-type double patenting with regards to the aforementioned parent patent.
The following table summarizes claim mappings associated with the obviousness-type double patenting rejections:
19/232611
11,934,257 (17/548043)
1. A method of processing of a first task and a second task, the first task and the second task being duplicates, the method comprising: storing read-write data, wherein the stored read-write data is accessible during the processing of the first task; storing a copy of the read-write data, wherein the stored copy of the read-write data is accessible during the processing of the second task; and storing read-only data, wherein the stored read-only data is accessible during the processing of both the first task and the second task.
1. A method of processing an input task in a processing system, the method comprising: duplicating the input task so as to form a first task and a second task; allocating memory comprising: a first block of memory configured to store read-write data to be accessed during the processing of the first task; a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task; and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task; and processing the first task and the second task at processing logic of the processing system so as to, respectively, generate first and second outputs.
5. The method of claim 1, wherein the read-write data is stored in a first block of memory, the copy of the read-write data is stored in a second block of memory, and the method further comprises, prior to processing the first and second task, storing read-write data at a memory address of the first block of memory and storing a copy of that read-write data at a corresponding memory address of the second block of memory.
2. The method of claim 1, the method further comprising, prior to processing the first and second task, storing read-write data at a memory address of the first block of memory and storing a copy of that read-write data at a corresponding memory address of the second block of memory.
6. The method of claim 1, wherein the read-write data is stored in a first block of memory, the copy of the read-write data is stored in a second block of memory, and the first block of memory and the second block of memory are allocated in a heap of memory, each memory address of the second block of memory being offset from a corresponding memory address in the first block of memory by a fixed memory address stride.
3. The method of claim 1, wherein the first block of memory and the second block of memory are allocated in a heap of memory, each memory address of the second block of memory being offset from a corresponding memory address in the first block of memory by a fixed memory address stride.
7. The method of claim 6, wherein the first task and second task are duplicates of an input task, and wherein a plurality of input tasks are processed at a processing system and the fixed memory address stride is the same for each pair of first and second tasks that are duplicates of the respective input tasks.
4. The method of claim 3, wherein a plurality of input tasks are processed at the processing system and the fixed memory address stride is the same for each pair of first and second tasks formed from the respective input tasks.
8. The method of claim 6, wherein the fixed memory address stride is half the size of the heap of memory.
5. The method of claim 3, wherein the fixed memory address stride is half the size of the heap of memory.
11. The method of claim 9, wherein the read-write data is stored in a first block of memory, the copy of the read-write data is stored in a second block of memory, and the method further comprises: receiving the second output; identifying, in the second output, a reference to a memory address in the first block of memory; updating that reference; and accessing, using the updated reference, a corresponding memory address in the second block of memory.
7. The method of claim 1, the method further comprising: receiving the second output; identifying, in the second output, a reference to a memory address in the first block of memory; updating that reference; and accessing, using the updated reference, the corresponding memory address in the second block of memory.
12. The method of claim 11, wherein the first block of memory and the second block of memory are allocated in a heap of memory, each memory address of the second block of memory being offset from a corresponding memory address in the first block of memory by a fixed memory address stride, the method further comprising using the fixed memory address stride to update the reference, in the second output, to a memory address in the first block of memory.
8. The method of claim 7, wherein the first block of memory and the second block of memory are allocated in a heap of memory, each memory address of the second block of memory being offset from a corresponding memory address in the first block of memory by a fixed memory address stride, the method further comprising using the fixed memory address stride to update the reference, in the second output, to a memory address in the first block of memory.
13. The method of claim 9, the method further comprising: submitting, concurrently, the first task and the second task to the processing logic.
10. The method of claim 1, the method further comprising: submitting, concurrently, the first task and the second task to the processing logic.
17. The method of claim 1, wherein the read-write data is stored in a first block of memory, the copy of the read-write data is stored in a second block of memory, the read-only data is stored in a third block of memory, and the method further comprises: fetching data from the first, second and third blocks of memory into a cache configured to be accessed by processing logic during the processing of the first task and the second task.
11. The method of claim 10, the method further comprising: fetching data from the first, second and third blocks of memory into a cache configured to be accessed by the processing logic during the processing of the first task and the second task.
10. The method of claim 9, wherein the processing logic comprises a first processing element and a second processing element, wherein said processing the first task and the second task at processing logic of the processing system comprises processing the first task at the first processing element and processing the second task at the second processing element.
13. The method of claim 1, wherein the processing logic comprises a first processing element and a second processing element, wherein said processing the first task and the second task at processing logic of the processing system comprises processing the first task at the first processing element and processing the second task at the second processing element.
14. The method of claim 9, wherein the first and second outputs comprise intermediate outputs generated during the processing of, respectively, the first and second tasks, and optionally wherein an intermediate output is one or more of a load, store or atomic instruction generated during the processing of a task.
16. The method of claim 1, wherein the first and second outputs comprise intermediate outputs generated during the processing of, respectively, the first and second tasks, and optionally wherein an intermediate output is one or more of a load, store or atomic instruction generated during the processing of a task.
15. The method of claim 9, the method further comprising: forming first and second signatures which are characteristic of, respectively, the first and second outputs; comparing the first and second signatures; and raising a fault signal if the first and second signatures do not match.
17. The method of claim 1, the method further comprising: forming first and second signatures which are characteristic of, respectively, the first and second outputs; comparing the first and second signatures; and raising a fault signal if the first and second signatures do not match.
16. The method of claim 15, the method further comprising forming the first and second signatures prior to the first and second outputs accessing a memory hierarchy of the processing system.
18. The method of claim 17, the method further comprising forming the first and second signatures prior to the first and second outputs accessing a memory hierarchy of the processing system.
18. A processing system configured to process a first task and a second task, the first task and the second task being duplicates, the processing system comprising a memory, the processing system being configured to: store read-write data in the memory, wherein the stored read-write data is accessible during the processing of the first task; store a copy of the read-write data in the memory, wherein the stored copy of the read-write data is accessible during the processing of the second task; and store read-only data in the memory, wherein the stored read-only data is accessible during the processing of both the first task and the second task.
19. The processing system of claim 18, wherein the processing system further comprises processing logic configured to process the first task so as to generate a first output, and to process the second task so as to generate a second output.
19. A processing system configured to process an input task, the processing system embodied in hardware on an integrated circuit comprising: a task duplication unit configured to duplicate the input task so as to form a first task and a second task; a memory; a memory allocation unit configured to allocate blocks of memory in the memory, including: a first block of memory in the memory configured to store read-write data to be accessed during the processing of the first task, a second block of memory in the memory configured to store a copy of the read-write data to be accessed during the processing of the second task, and a third block of memory in the memory configured to store read-only data to be accessed during the processing of both the first task and the second task; and processing logic configured to process the first task so as to generate a first output, and to process the second task so as to generate a second output.
20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processing system configured to process a first task and a second task, the first task and the second task being duplicates, the processing system comprising a memory, the processing system being configured to: store read-write data in the memory, wherein the stored read-write data is accessible during the processing of the first task; store a copy of the read-write data in the memory, wherein the stored copy of the read-write data is accessible during the processing of the second task, and store read-only data in the memory, wherein the stored read-only data is accessible during the processing of both the first task and the second task.
21. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a processing system configured to process an input task, the processing system comprising: a task duplication unit configured to duplicate the input task so as to form a first task and a second task; a memory allocation unit configured to allocate memory, including: a first block of memory configured to store read-write data to be accessed during the processing of the first task, a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task, and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task; processing logic configured to process the first task so as to generate a first output, and to process the second task so as to generate a second output.
The claims of US Patent No. 11,934,257 do not explicitly teach duplicating the input task so as to form a first task and a second task.
However, Spencer (US Patent Application 2013/0268807) teaches generating a duplicate request packet, in Paragraph 168.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine the claims of US Patent No. 11,934,257 with duplicating the input task so as to form a first task and a second task for the purpose of allocating memory blocks to store data.
Prior Art Made of Record
Resch et al. (U.S. Patent Application No. 2015/0039934), teaches replicating a task.
Varma et al. (US Patent Application 2015/0227414) teaches allocating a heap memory pool.
Gupta et al. (US Patent Application 2009/0094589) teaches reading heap memory size.
Hartono et al. (US Patent Application 2016/0092285) teaches a contiguous block of memory.
Coronado et al. (US Patent Application 2015/0234719) teaches updating a reference pointer.
Carlough et al. (US Patent Application 2016/0170828) teaches fetching instructions.
Flautner et al. (US Patent Application 2014/0181581) teaches a predefined safety level.
Ellis et al. (US Patent Application 2015/0269018) teaches inputting a test instruction.
Wade et al. (US Patent Application 2016/0154710) teaches executing a particular set of instructions.
Lev et al. (US Patent Application 2009/0031310) teaches an atomic source code.
Brewerton et al. (US Patent Application 2013/0198571) teaches comparing signatures.
Conclusion
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/SARAI E BUTLER/Primary Examiner, Art Unit 2114
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