DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petersen U.S. Patent Publication No. 2023/0045186 (hereinafter Petersen).
Consider claim 1, Petersen teaches a power supply device comprising: a switching block connected between an input node configured to receive an input power and a switching node configured to output a switching voltage (Figure 3, block 300, IN and OUT), the switching block being configured to convert the input power into the switching voltage by transistors being turned on/off based on a first control signal and a second control signal (Figures 4-9, S1-S5; [0095] suggest transistors used for switches); an inductor connected between the switching node and an output node configured to output an output power (Figure 3, L); and an output capacitor connected between the output node and a ground node configured to receive a ground power (Figure 3, Cout), wherein, during a first section in which an on duty ratio of each of the first control signal and the second control signal is greater than a reference value, a voltage level of the output power is greater than a voltage level of the input power (Figure 10, duty cycle greater than .5 and Vout/Vin greater than 1 corresponding to Figure 3), and during a second section in which the on duty ratio is less than or equal to the reference value, the voltage level of the output power is less than the voltage level of the input power (Figure 10, duty cycle less than .5 and Vout/Vin less than 1 corresponding to Figure 3), wherein a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section appears to be the same as a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section (Figure 10, rate around .3 duty cycle in comparison to rate around .9-1 duty cycle).
Peterson does not appear to specifically disclose wherein a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section is same as a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section.
However, Peterson disclose a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section is substantially similar to a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section (Figure 10, rate around .3 duty cycle in comparison to rate around .9-1 duty cycle).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular increasing rate as taught by Peterson in order to meet design choices. In addition, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Consider claim 2, Petersen teaches all the limitations of claim 1. In addition, Petersen teaches wherein based on the on duty ratio being greater than the reference value (e.g. duty cycle .8 in figure 10), the switching voltage has a voltage level between the voltage level of the input power and twice the voltage level of the input power (Figures 3 and figure 10, .8 and corresponding Vout/Vin)), and wherein based on the on duty ratio being less than or equal to the reference value (e.g. duty cycle .2 in figure 10), the switching voltage has the voltage level between a voltage level of the ground power and the voltage level of the input power (Figures 3 and figure 10, .2 and corresponding Vout/Vin)).
Consider claim 3, Petersen teaches all the limitations of claim 2. In addition, Petersen teaches wherein as the on duty ratio increases from zero to one (Figure 10, duty cycle 0 to 1), the voltage level of the output power continuously increases from the voltage level of the ground power to about twice the voltage level of the input power (Figure 10, Vout/Vin 0 to 2).
Petersen does not appear to specifically disclose twice.
However, Petersen suggests in [0114], states may be combined with other states in the driving sequence to achieve the desired conversion ratio.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide output power twice the voltage of the input power in order to achieve the desired conversion ration as suggested by Peterson. In addition, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Consider claim 4, Petersen teaches all the limitations of claim 3. In addition, Petersen teaches wherein a phase difference between the first control signal and the second control signal is 180 degrees (Figure 13, D1-D2 and Figures 4, 6, D1-D2).
Consider claim 5, Petersen teaches all the limitations of claim 4. In addition, Petersen teaches wherein the reference value is 0.5 (Figure 10, duty cycle .5).
Consider claim 6, Petersen teaches all the limitations of claim 4. In addition, Petersen teaches a first transistor coupled between the input node and a first node (Figure 3, S1), the first transistor including a gate electrode receiving the first control signal (Figure 3, [0104] and driver 320; [0095], FETs as transistors); a first capacitor connected between the first node and a second node (Figure 3, CF); a second transistor connected between the second node and the switching node (Figure 3, S2b), the second transistor including a gate electrode receiving the second control signal (Figure 3, [0104] and driver 320; [0095], FETs as transistors); a third transistor coupled between the second node and the input node (Figure 3, S2a), the third transistor including a gate electrode receiving a third control signal (Figure 3, [0104] and driver 320; [0095], FETs as transistors); a fourth transistor connected between the switching node and the first node (Figure 3, S3), the fourth transistor including a gate electrode receiving a fourth control signal (Figure 3, [0104] and driver 320; [0095], FETs as transistors); and a fifth transistor coupled between the first node and the ground node (Figure 3, S4), the fifth transistor including a gate electrode receiving a fifth control signal (Figure 3, [0104] and driver 320; [0095], FETs as transistors).
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petersen as applied to claim 6 above, and further in view of Tarroboiro et al. U.S. Patent Publication No. 2022/0302827 (hereinafter Tarroboiro).
Consider claim 7, Petersen teaches all the limitations of claim 6. In addition, Petersen teaches wherein based on the first control signal, the first transistor is configured to be turned on (Figure 8, S1) , and wherein based on the second control signal, the second transistor is configured to be turned on (Figure 8, S2b).
Petersen does not appear to specifically disclose having a logic high level.
However, in a related field of endeavor, Tarroboiro teaches a hybrid buck-boost power converter (figure 2 and [0026]) and further teaches having a logic high level (Figure 3 and [0028], NMOS M1).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to turn on based on high level as taught by Petersen with the benefit that NMOS switches on when a high voltage is applied to its gate, allowing current to flow from source to drain.
Consider claim 8, Petersen and Tarroboiro teach all the limitations of claim 7. In addition, Peterson teaches wherein the third control signal controls the third transistor to be turned on or off alternately with the first transistor (Figure 8, S2A and S1), wherein the fourth control signal controls the fourth transistor to be turned on or off alternately with the second transistor (Figure 8, S3 and S2b), and wherein the fifth control signal controls the fifth transistor to be turned on or off alternately with the first transistor (Figure 6, S4 and S1).
Consider claim 9, Petersen and Tarroboiro teach all the limitations of claim 7. In addition, Peterson teaches wherein based on the on duty ratio being greater than the reference value (Figure 11, duty cycle greater than .5), a switching cycle includes first to fourth consecutive intervals ([0121], D1-B2-D2-B2; [0123], in the second mode (step up) the switching state D1 may be partially or fully replaced with the switching state B1. For instance B1 may be used in combination with D2 and B2), and wherein during the first interval and the third interval, the first transistor and the second transistor are configured to be turned on (Figure 8, S1 and S2B), the third transistor, the fourth transistor, and the fifth transistor are configured to be turned off (Figure 8, S2A, S3 and S4), and the switching voltage is about twice the voltage level of the input power (Figure 10, D=1 and corresponding Vout/Vin).
Petersen does not appear to specifically disclose twice.
However, Petersen suggests in [0114], states may be combined with other states in the driving sequence to achieve the desired conversion ratio.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide output power twice the voltage of the input power in order to achieve the desired conversion ration as suggested by Peterson. In addition, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petersen in view of Park U.S. Patent Publication No. 2016/0125791 (hereinafter Park).
Consider claim 15, Petersen teaches a display device (Figure 25, 2510), wherein the power supply comprises: a switching block connected between an input node configured to receive the input power and a switching node configured to output a switching voltage (Figure 3, block 300, IN and OUT), the switching block being configured to convert the input power into the switching voltage by transistors being turned on/off based on a first control signal and a second control signal (Figures 4-9, S1-S5; [0095] suggest transistors used for switches); an inductor connected between the switching node and an output node outputting an output power (Figure 3, L); and an output capacitor connected between the output node and a ground node receiving a ground power (Figure 3, Cout), wherein, during a first section in which an on duty ratio of each of the first control signal and the second control signal being is greater than a reference value, a voltage level of the output power is greater than a voltage level of the input power (Figure 10, duty cycle greater than .5 and Vout/Vin greater than 1 corresponding to Figure 3), and during a second section in which the on duty ratio is less than or equal to the reference value, the voltage level of the output power is less than the voltage level of the input power (Figure 10, duty cycle less than .5 and Vout/Vin less than 1 corresponding to Figure 3), wherein a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section appears to be the same as a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section (Figure 10, rate around .3 duty cycle in comparison to rate around .9-1 duty cycle).
Peterson does not appear to specifically disclose wherein a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section is same as a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section.
However, Peterson disclose a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section is substantially similar to a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section (Figure 10, rate around .3 duty cycle in comparison to rate around .9-1 duty cycle).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular increasing rate as taught by Peterson in order to meet design choices. In addition, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Peterson does not appear to specifically disclose a display panel including scan lines, a first power supply line, a second power supply line, and pixels connected to the scan lines and the first and second power supply lines; a scan driver configured to sequentially provide scan signals to the scan lines; and a power supply configured to convert an input power into a first power supply voltage and a second power supply voltage, to supply the first power supply voltage to the first power supply line, and to supply the second power supply voltage to the second power supply line.
However, in a related field of endeavor, Park teaches a DC-DC converter (abstract) and further teaches a display panel including scan lines (Figure 12, Gp), a first power supply line, a second power supply line (Figure 12, ELVDD and ELVSS), and pixels connected to the scan lines and the first and second power supply lines (Figure 12, PX, Gp, ELVDD and ELVSS); a scan driver configured to sequentially provide scan signals to the scan lines [0178]; and a power supply configured to convert an input power into a first power supply voltage and a second power supply voltage, to supply the first power supply voltage to the first power supply line, and to supply the second power supply voltage to the second power supply line [0180-0181].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide scan driver and power supply for a display as taught by Park with the benefit that each of the plurality of pixels PX may operate in response to a first power voltage ELVDD, a second power voltage ELVSS, a gate signal, and a data signal as suggested in [0175].
Consider claim 16, it includes the limitations of claim 2 and thus it is rejected by the same reasoning.
Consider claim 17, it includes the limitations of claim 3 and thus it is rejected by the same reasoning.
Consider claim 18, it includes the limitations of claim 5 and thus it is rejected by the same reasoning.
Consider claim 19, Petersen teaches an electronic device (Figure 25, 2500), comprising: a display device (Figure 25, 2510), wherein the power supply comprises: a switching block connected between an input node configured to receive the input power and a switching node configured to output a switching voltage (Figure 3, block 300, IN and OUT), the switching block being configured to convert the input power into the switching voltage by transistors being turned on/off based on a first control signal and a second control signal (Figures 4-9, S1-S5; [0095] suggest transistors used for switches); an inductor connected between the switching node and an output node outputting an output power (Figure 3, L); and an output capacitor connected between the output node and a ground node receiving a ground power (Figure 3, Cout), wherein, during a first section in which an on duty ratio of each of the first control signal and the second control signal is greater than a reference value, a voltage level of the output power is greater than a voltage level of the input power (Figure 10, duty cycle greater than .5 and Vout/Vin greater than 1 corresponding to Figure 3), and during a second section in which the duty ratio being is less than or equal to the reference value, the voltage level of the output power is less than the voltage level of the input power (Figure 10, duty cycle less than .5 and Vout/Vin less than 1 corresponding to Figure 3), and wherein a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section appears to be the same as a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section (Figure 10, rate around .3 duty cycle in comparison to rate around .9-1 duty cycle).
Peterson does not appear to specifically disclose wherein a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section is same as a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section.
However, Peterson disclose a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section is substantially similar to a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section (Figure 10, rate around .3 duty cycle in comparison to rate around .9-1 duty cycle).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular increasing rate as taught by Peterson in order to meet design choices. In addition, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Peterson does not appear to specifically disclose an electronic device, comprising: a processor; and a display device including pixels, the display device configured to display an image on the pixels in response to control of the processor, wherein the display device comprises: a display panel including scan lines, a first power supply line, a second power supply line, and pixels connected to the scan lines and the first and second power supply lines; a scan driver configured to sequentially provide scan signals to the scan lines; and a power supply configured to convert an input power into a first power supply voltage and a second power supply voltage, to supply the first power supply voltage to the first power supply line, and to supply the second power supply voltage to the second power supply line.
However, in a related field of endeavor, Park teaches a DC-DC converter (abstract) and further teaches an electronic device (Figure 18, 6000), comprising: a processor (Figure 18, 2000); and a display device including pixels (Figure 12, Px), the display device configured to display an image on the pixels in response to control of the processor ([0223] and [0177]), wherein the display device comprises: a display panel including scan lines (Figure 12, Gp), a first power supply line, a second power supply line (Figure 12, ELVDD and ELVSS), and pixels connected to the scan lines and the first and second power supply lines (Figure 12, PX, Gp, ELVDD and ELVSS); a scan driver configured to sequentially provide scan signals to the scan lines [0178]; and a power supply configured to convert an input power into a first power supply voltage and a second power supply voltage, to supply the first power supply voltage to the first power supply line, and to supply the second power supply voltage to the second power supply line [0180-0181].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide processor, scan driver and power supply for a display as taught by Park with the benefit that each of the plurality of pixels PX may operate in response to a first power voltage ELVDD, a second power voltage ELVSS, a gate signal, and a data signal as suggested in [0175]. In addition, processor may control the storage device and the display device and perform specific functions and/or task.
Consider claim 20, it includes the limitations of claim 2 and thus it is rejected by the same reasoning.
Allowable Subject Matter
Claims 10-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior arts does not appear to disclose the second interval in combination to other limitations of base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 05/20/2026 have been fully considered but they are not persuasive.
On page 13, Applicant argues that “As shown in Petersen's FIG. 10, the voltage conversion ratio curve of the FIG. 3 topology (curve 1030) is visually non-linear and non-symmetric across the buck and boost sections. Specifically, curve 1030 exhibits a steep, varying slope in the buck section (D ≤ 0.5) and a comparatively different, more gradual slope in the boost section (D > 0.5). The two sections do not share the same rate of increase - the curve bends and changes character at the D = 0.5 boundary, confirming that the voltage conversion ratio does not increase at a uniform rate across both regions.” The Office respectfully disagrees for the following reasons.
Claim recites “wherein a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section is same as a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section.” Peterson disclose a first increasing rate of a voltage conversion ratio according to the on duty ratio during the first section is substantially similar to a second increasing rate of a voltage conversion ratio according to the on duty ratio during the second section (e.g. rate around .3 duty cycle in comparison to rate around .9-1 duty cycle in figure 10). Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular increasing rate as taught by Peterson in order to meet design choices. In addition, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. Consequently, these arguments have been considered but they are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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