DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 4 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, 11, and 16 of U.S. Patent No. 12,346,600. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent require all the limitations of the claims of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2020/0379922 (hereinafter Kumar) in view of US Patent No. 11,513,723 (hereinafter Muthiah), and further in view of US Patent No. 10,896,136 (hereinafter Bae).
As per claim 1, Kumar teaches a first memory module (Kumar; Figure 2 Item 250-0 “Memory”) communicating with a host (Kumar; Figure 2 Items 250-0 “CPUs”) through a first interface (Kumar; Paragraph [0030]); and a second memory module (Kumar; Figure 2 Item 260) communicating with the host through a second interface (Kumar; Paragraph [0016]), wherein the first memory module comprises: a memory device (Kumar; Figure 2 Item 250-0 “Memory”); and a memory controller (Kumar; Figure 2 Item 200) configured to prefetch data stored in the second memory module into the memory device based on access pattern information of the host for the memory device (Kumar; Paragraph [0030]).
Kumar does not explicitly teach the memory device including a plurality of zones allocated by the host and the first memory module comprises the memory controller.
However, Muthiah teaches a memory system in which a memory device includes a plurality of zones allocated by a host (Muthiah; Col 3 Lines 46 – 58).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Kumar to include the memory zones because doing so allows for avoiding memory conflicts.
Kumar in combination with Muthiah does not explicitly teach that the memory module comprises the memory controller.
However, Bae teaches a memory prefetching system in which the memory module (Bae; Figure 3 Item 200) includes the memory controller (Bar; Figure 3 Item 215).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Kumar in combination with Muthiah to include the memory controller within the memory device because doing so would be an ordinary design and system layout choice one would encounter when implementing such a system.
As per claim 3, Kumar teaches a first memory module (Kumar; Figure 2 Item 250-0 “Memory”) communicating with a host (Kumar; Figure 2 Items 250-0 “CPUs”) through a first interface (Kumar; Paragraph [0030]); and a second memory module (Kumar; Figure 2 Item 260) communicating with the host through a second interface (Kumar; Paragraph [0016]), wherein the second memory module comprises: a memory device (Kumar; Figure 2 Item 250-0 “Memory”); and a memory controller (Kumar; Figure 2 Item 200) configured to provide the first memory module with data stored in the plurality of zones based on access pattern information of the host for the memory device (Kumar; Paragraph [0030]).
Kumar does not explicitly teach the memory device including a plurality of zones allocated by the host and the second memory module comprises the memory controller.
However, Muthiah teaches a memory system in which a memory device includes a plurality of zones allocated by a host (Muthiah; Col 3 Lines 46 – 58).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Kumar to include the memory zones because doing so allows for avoiding memory conflicts.
Kumar in combination with Muthiah does not explicitly teach that the second memory module comprises the memory controller.
However, Bae teaches a memory prefetching system in which the memory module (Bae; Figure 3 Item 200) includes the memory controller (Bar; Figure 3 Item 215).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Kumar in combination with Muthiah to include the memory controller within the memory device because doing so would be an ordinary design and system layout choice one would encounter when implementing such a system.
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2020/0379922 (hereinafter Kumar) in view of US Patent No. 11,513,723 (hereinafter Muthiah).
As per claim 2, Kumar teaches a first memory module (Kumar; Figure 2 Item 250-0 “Memory”), which communicates with a host (Kumar; Figure 2 Items 250-0 “CPUs”) through a first interface (Kumar; Paragraph [0030]), and prefetching data stored in a second memory module (Kumar; Figure 2 Item 260), which communicates with the host through a second interface (Kumar; Paragraph [0016]), into each of the plurality of zones based on access pattern information of the host for each of the plurality of zones.
Kumar does not explicitly teach the allocating a storage area of a first memory module into a plurality of zones according to a core, a thread, or an application of the host.
However, Muthiah teaches a memory system in which a storage area of a first memory module into a plurality of zones according to a core, a thread, or an application of the host (Muthiah; Col 1 Lines 39 – 49).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Kumar to include the memory zones because doing so allows for avoiding memory conflicts.
As per claim 4, Kumar teaches a second memory module (Kumar; Figure 2 Item 260), which communicates with a host through a second interface (Kumar; Paragraph [0016]); and prefetching data (Kumar; Paragraph [0030]) stored in the second memory into a first memory module (Kumar; Figure 2 Item 250-0 “Memory”), which communicates with the host (Kumar; Figure 2 Items 250-0 “CPUs”) through a first interface (Kumar; Paragraph [0030]), based on access pattern information of the host for each of the plurality of zones.
Kumar does not explicitly teach the allocating a storage area of a second memory module into a plurality of zones according to a core, a thread, or an application of the host.
However, Muthiah teaches a memory system in which a storage area of a first memory module into a plurality of zones according to a core, a thread, or an application of the host (Muthiah; Col 1 Lines 39 – 49).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Kumar to include the memory zones because doing so allows for avoiding memory conflicts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
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