DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,2,12-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ZHAI (US 2022/0246088).
Regarding claim 1, ZHAI discloses a pixel circuit (abstract), comprising a first-type switch transistor and a second-type switch transistor (Figure 2; paragraph 47-50; PAM and PWM circuit comprises of n-type or p-type transistors); a gate of the first-type switch transistor is configured to receive a first-type control signal, and the first-type control signal comprises a first high level and a first low level (Figure 3, 4; paragraph 50-52; corresponding to any gate that receives control signaling); and a gate of the second-type switch transistor is configured to receive a second-type control signal, and the second-type control signal comprises a second high level and a second low level (Figure 3, 4; paragraph 50-52; corresponding to any gate that receives control signaling); wherein the pixel circuit further comprises a current driving circuit 110 and a pulse width modulation circuit 120, and the pulse width modulation circuit is configured to control a light emission duration of a light-emitting element based on pulse width data and a sweep signal (paragraph 30-32, 43-45, 50, 51); the current driving circuit comprises a first drive voltage end VDD_PAM, and the pulse width modulation circuit comprises a second drive voltage end VDD_PWM (Figure 2); and the second high level is greater than or equal to a second drive voltage supplied by the second drive voltage end (paragraph 43, 44, 58,59; based on voltage characteristics disclosed, drive voltages and high level voltages can be adjusted accordingly).
Regarding claim 2, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses wherein the first high level is greater than or equal to the second drive voltage supplied by the second drive voltage end (paragraph 43, 44, 58,59; based on voltage characteristics disclosed, drive voltages and high-level voltages can be adjusted accordingly).
Regarding claim 12, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses wherein the second drive voltage is greater than or equal to a first drive voltage supplied by the first drive voltage end (paragraph 43, 44, 58, 59; based on voltage characteristics disclosed, drive voltages and high/low-level voltages can be adjusted accordingly).
Regarding claim 13, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses wherein a first-type voltage difference is a voltage difference between the first high level and the first low level, a second-type voltage difference is a voltage difference between the second high level and the second low level, and the first-type voltage difference is less than or equal to the second-type voltage difference (paragraph 43, 44, 58, 59; based on voltage characteristics disclosed, drive voltages and high/low-level voltages can be adjusted accordingly).
Regarding claim 14, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses wherein at least one of following configurations is met: the first high level is not equal to the second high level, and the first low level is not equal to the second low level (paragraph 43, 44, 58, 59; based on voltage characteristics disclosed, drive voltages and high/low level voltages can be adjusted accordingly).
Regarding claim 15, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses wherein a material of an active layer of the first-type switch transistor is the same as a material of an active layer of the second-type switch transistor (paragraph 47-49, 90).
Regarding claim 16, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses wherein the current driving circuit comprises the first-type switch transistor, and the pulse width modulation circuit comprises the second-type switch transistor (Figure 2).
Regarding claim 17, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses wherein at least one of following configurations is met: the second high level is greater than the first high level, and the second low level is greater than the first low level (paragraph 43, 44, 58, 59; based on voltage characteristics disclosed, drive voltages and high/low level voltages can be adjusted accordingly).
Regarding claim 18, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses further comprising a reset circuit 111, wherein the current driving circuit is electrically connected to the pulse width modulation circuit at a connection node, and the reset circuit is electrically connected between a reset voltage end and the connection node (Figure 2); and the reset circuit comprises a third-type switch transistor, a gate of the third-type switch transistor receives a third-type control signal, the third-type control signal comprises a third high level and a third low level, and the third low level is less than the first low level (paragraph 43, 44, 58, 59; based on voltage characteristics disclosed, drive voltages and high/low level voltages can be adjusted accordingly).
Regarding claim 19, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses A display panel, comprising the pixel circuit according to claim 1 (abstract).
Regarding claim 20, see the rejections of the parent claim concerning the subject matter this claim is dependent upon. ZHAI further discloses A display apparatus, comprising the display panel according to claim 19 (abstract).
Allowable Subject Matter
Claims 3-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior Art fails to disclose:
The pixel circuit according to claim 1, wherein the current driving circuit comprises a first drive transistor, a first reset transistor, a drive data write circuit, and a first light emission control circuit; the first drive transistor and the first light emission control circuit are connected in series between the first drive voltage end and the light-emitting element; the first reset transistor is configured to transmit a first reset voltage supplied by a first reset voltage end to a gate of the first drive transistor; the drive data write circuit is configured to transmit drive data; and the first-type switch transistor comprises at least one of following transistors: the first reset transistor, at least one transistor in the drive data write circuit, and at least one transistor in the first light emission control circuit; and the pulse width modulation circuit comprises a second drive transistor, a second reset transistor, a pulse width data write circuit, and a second light emission control circuit; the second drive transistor and the second light emission control circuit are connected in series between the second drive voltage end and a connection node; the pulse width modulation circuit is electrically connected to the current driving circuit at the connection node; the second reset transistor is configured to transmit a second reset voltage supplied by a second reset voltage end to a gate of the second drive transistor; the pulse width data write circuit is configured to transmit the pulse width data; and the second-type switch transistor comprises at least one of following transistors: the second reset transistor, at least one transistor in the pulse width data write circuit, and at least one transistor in the second light emission control circuit.
Conclusion
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/ARIEL A BALAOING/ Primary Examiner, Art Unit 2624