Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 10 June 2025 for application number 19/233,328. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 23 December 2022 (PCT/US2022/053925).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10 June 2025 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Construction
The present application contains contingent limitations. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04(II). See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding "The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim"); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Note that the limitations “when the read command or the write command exists” (in claim 19) may never be reached within the scope of the claim under the broadest reasonable interpretation since it may occur that the read command or the write command does not exist and the “when” condition may never be met. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP211.04(II).
It is suggested method claim 1 be amended to first determine that the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof definitively by removing “when”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites in the second to last limitation “determining, by the DRAM controller, whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof”. Similar to item 11 above, the use of “whether” is indefinite language. It is unclear what happens when it is determined that a suspend storage condition is not satisfied, along with the remaining portion of the limitation. Examiner suggests removing “whether” to place the limitation in definitive language. Claims 2 – 10 depend from claim 1 and a rejected based upon their dependency. Claims 2, 11, and 12 recite similar language with the use of “whether” and is rejected with like reasoning. Claims 3, 4, and 13 – 20 depend from claims 2 and 11 and are rejected based upon their dependency.
Claim 1 recites in the last limitation: “storing, by the DRAM controller, the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied.” It is unclear how cache data is being stored into a ROM. If the data is to be written (stored), it is unclear how that is possible when the memory is read-only. Or if a write/storage of data is occurring then the memory cannot be a ROM. Claims 8, 11, and 18 and recites similar language and if rejected with like reasoning. Claims 2 – 10 and 12 – 20 depend from claims 1 and 11, and are rejected based upon their dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5, 9 – 15, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jones, JR. et al. [hereafter as Jones], US Pub. No. 2006/0005053 A1 in view of Cooper et al., [hereafter as Cooper], US Pub. No. 2009/0172439 A1 and further in view of Dev et al. [hereafter as Dev], US Pub. No. 2023/0236977 A1.
As per claim 1, Jones discloses a method for managing cache data stored by a control system [“wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered such that the cache, tag and much of the cache control logic can be powered-down during power-down standby mode.”] [Abstract], the method comprising:
storing, by a microcontroller [cache controller 116], the cache data of the microcontroller into a dynamic random-access memory (DRAM) in response to the microcontroller receiving a power-off command [“wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered”] [Abstract] [“the cache 106 is controlled by a cache controller 116”] [para. 0024];
operating, by a DRAM controller, the DRAM in a standby state in response to the microcontroller storing the cache data into the DRAM, wherein the DRAM is operable in the standby state, an on state, and an off state [“wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered such that the cache, tag and much of the cache control logic can be powered-down during power-down standby mode. If a DRAM cache is used, the refresh cycles can be inhibited to the DRAM cache, since it has been powered-down, so that additional power savings can be realized during self-refresh power-down standby.”] [Abstract] [“DRAM memory array 102 is controlled by a DRAM controller 112”] [para. 0024] [para. 0025];
determining, by the DRAM controller and when the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof [“The function of the DRAM memory array 102 is controlled by a DRAM controller 112 in response to signals input on a DRAM address/control (ADR/CTL) bus 114.”] [para. 0024] [“With reference additionally now to FIG. 2. a timing diagram is illustrated which shows the clock (CLK), Sleep Mode (ZZ), Clear Tag Flag (CTF) and Refresh Request (REFR) signals during a Sleep Mode entry with a refresh request in the inactive state. As indicated, on the positive-going transition of the CLK signal following assertion of the ZZ command with the REFR command inactive (e.g. "low"), a write-back operation from the cache 106 to the DRAM memory arrays 102 takes place.”] [para. 0025];
determining, by the DRAM controller, whether a storage condition is satisfied [“The function of the DRAM memory array 102 is controlled by a DRAM controller 112 in response to signals input on a DRAM address/control (ADR/CTL) bus 114.”] [para. 0024] [“With reference additionally now to FIG. 2. a timing diagram is illustrated which shows the clock (CLK), Sleep Mode (ZZ), Clear Tag Flag (CTF) and Refresh Request (REFR) signals during a Sleep Mode entry with a refresh request in the inactive state. As indicated, on the positive-going transition of the CLK signal following assertion of the ZZ command with the REFR command inactive (e.g. "low"), a write-back operation from the cache 106 to the DRAM memory arrays 102 takes place.”] [para. 0025];
storing, by the DRAM controller, the cache data [“wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered”] [Abstract] [“The function of the DRAM memory array 102 is controlled by a DRAM controller 112 in response to signals input on a DRAM address/control (ADR/CTL) bus 114.”] [para. 0024].
However, Jones does not explicitly disclose a vehicle control system:
determining whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof; and
storing the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied.
Cooper teaches determining whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof [“3. Setting of SLP_EN bit causes a hardware interrupt to EP 34. EP 34 evaluates the interrupt and determines that system wants to go into hibernate sleep state. EP 34 initiates a partial power-down of the platform by shutting down processor cores 22, and all user visible platform hardware; leaving only DRAM 20 powered. Note that this could be alternatively triggered after some amount of delay (e.g., 15 minutes) thus allowing the system to use conventional S3 for short duration sleep intervals, and only trigger the hibernate function after an extended S3 interval (e.g., 15 minutes).”] [para. 0032]; and
storing the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied [“3. Setting of SLP_EN bit causes a hardware interrupt to EP 34. EP 34 evaluates the interrupt and determines that system wants to go into hibernate sleep state. EP 34 initiates a partial power-down of the platform by shutting down processor cores 22, and all user visible platform hardware; leaving only DRAM 20 powered. Note that this could be alternatively triggered after some amount of delay (e.g., 15 minutes) thus allowing the system to use conventional S3 for short duration sleep intervals, and only trigger the hibernate function after an extended S3 interval (e.g., 15 minutes). 4. EP 34 copies OS hibernate data region from system DRAM 20 into Fast NVRAM memory 38 via its internal SRAM buffer 82 (shown in FIG. 2).”] [paras. 0032 – 0033].
Jones and Cooper are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Jones with Cooper in order to modify Jones for “determining whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof; and
storing the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied” as taught by Cooper. One of ordinary skill in the art would be motivated to combine Jones with Cooper before the effective filing date of the claimed invention to improve a system by providing for “faster hibernate and resume times …, and that consumes less ...” [Cooper, para. 0007].
However, Jones and Cooper do not explicitly disclose a vehicle control system.
Dev teaches a vehicle control system [“In at least one embodiment, vehicle 1100 may include one or more controller(s) 1136, such as those described herein with respect to FIG. 11A. In at least one embodiment, controller(s) 1136 may be used for a variety of functions. In at least one embodiment, controller(s) 1136 may be coupled to any of various other components and systems of vehicle 1100, and may be used for control of vehicle 1100, artificial intelligence of vehicle 1100, infotainment for vehicle 1100, and/or other functions.”] [para. 0172].
Jones, Cooper, and Dev are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Jones and Cooper with Dev in order to modify Jones and Cooper for “a vehicle control system” as taught by Dev. One of ordinary skill in the art would be motivated to combine Jones and Cooper with Dev before the effective filing date of the claimed invention to improve a system by providing for the ability where “a processor cache comprises circuitry to store data copied from another memory, in order to improve processor efficiency.” [Dev, para. 0058].
Claim 11 is rejected with like reasoning.
As per claim 2, Jones in view of Cooper and further in view of Dev discloses the method of Claim 1 Cooper teaches further comprising:
determining, by the microcontroller, whether a power-on command is received [“Upon the occurrence of a wake event (initiation of a resume command), EP 34 powers-on first and immediately initializes DRAM system memory 20 and starts restoring OS DRAM context from fast NVRAM device 38. In some embodiments, this restoring of DRAM occurs even before the processor starts to execute system BIOS code. While the BIOS follows its regular hibernate resume path, EP 34 continues to restore OS context in DRAM 20 and by the time BIOS 48 completes its initialization of processor, chipset, and other platform components, EP 34 has already completed restoring all OS hibernate recovery context in the DRAM. BIOS 48 finishes its execution and passes control to the OS hibernate wake-up vector that was originally embedded within the OS hibernate recovery context in the DRAM and has been restored by the EP along with the rest of the hibernate data. Once getting control, the OS wake-up code immediately starts executing from DRAM 20 and restores remaining OS components using hibernate recovery data in the DRAM. In other embodiments, the details are different.”] [para. 0037] [“In the figures, different instances of CPU cores 22, memory controller 28, controller 34, memory 20 and section 30, NVRAM 38, and hard drive 42 may be the same or different than each other.”] [para. 0051]; and
obtaining, by the microcontroller, the cache data from the ROM in response to the suspend to storage condition being satisfied [“Upon the occurrence of a wake event (initiation of a resume command), EP 34 powers-on first and immediately initializes DRAM system memory 20 and starts restoring OS DRAM context from fast NVRAM device 38. In some embodiments, this restoring of DRAM occurs even before the processor starts to execute system BIOS code. While the BIOS follows its regular hibernate resume path, EP 34 continues to restore OS context in DRAM 20 and by the time BIOS 48 completes its initialization of processor, chipset, and other platform components, EP 34 has already completed restoring all OS hibernate recovery context in the DRAM. BIOS 48 finishes its execution and passes control to the OS hibernate wake-up vector that was originally embedded within the OS hibernate recovery context in the DRAM and has been restored by the EP along with the rest of the hibernate data. Once getting control, the OS wake-up code immediately starts executing from DRAM 20 and restores remaining OS components using hibernate recovery data in the DRAM. In other embodiments, the details are different.”] [para. 0037] [“In the figures, different instances of CPU cores 22, memory controller 28, controller 34, memory 20 and section 30, NVRAM 38, and hard drive 42 may be the same or different than each other.”] [para. 0051].
Claim 12 is rejected with like reasoning.
As per claim 3, Jones in view of Cooper and further in view of Dev discloses the method of Claim 2 Cooper teaches further comprising obtaining, by the microcontroller, the cache data from the DRAM in response to the suspend to storage condition not being satisfied [“Upon the occurrence of a wake event (initiation of a resume command), EP 34 powers-on first and immediately initializes DRAM system memory 20 and starts restoring OS DRAM context from fast NVRAM device 38. In some embodiments, this restoring of DRAM occurs even before the processor starts to execute system BIOS code. While the BIOS follows its regular hibernate resume path, EP 34 continues to restore OS context in DRAM 20 and by the time BIOS 48 completes its initialization of processor, chipset, and other platform components, EP 34 has already completed restoring all OS hibernate recovery context in the DRAM. BIOS 48 finishes its execution and passes control to the OS hibernate wake-up vector that was originally embedded within the OS hibernate recovery context in the DRAM and has been restored by the EP along with the rest of the hibernate data. Once getting control, the OS wake-up code immediately starts executing from DRAM 20 and restores remaining OS components using hibernate recovery data in the DRAM. In other embodiments, the details are different.”] [para. 0037].
Claim 13 is rejected with like reasoning.
As per claim 4, Jones in view of Cooper and further in view of Dev discloses the method of Claim 3 Cooper teaches further comprising performing, by the microcontroller, one or more control routines in response to obtaining the cache data from one of the DRAM and the ROM [“BIOS 48 finishes its execution and passes control to the OS hibernate wake-up vector that was originally embedded within the OS hibernate recovery context in the DRAM and has been restored by the EP along with the rest of the hibernate data. Once getting control, the OS wake-up code immediately starts executing from DRAM 20 and restores remaining OS components using hibernate recovery data in the DRAM. In other embodiments, the details are different.”] [para. 0037].
Dev teaches infotainment [“In at least one embodiment, vehicle 1100 may include one or more controller(s) 1136, such as those described herein with respect to FIG. 11A. In at least one embodiment, controller(s) 1136 may be used for a variety of functions. In at least one embodiment, controller(s) 1136 may be coupled to any of various other components and systems of vehicle 1100, and may be used for control of vehicle 1100, artificial intelligence of vehicle 1100, infotainment for vehicle 1100, and/or other functions.”] [para. 0172].
Claim 14 is rejected with like reasoning.
As per claim 5, Jones in view of Cooper and further in view of Dev discloses the method of Claim 1, Cooper teaches wherein:
the time characteristic indicates an amount of time the DRAM operates in the standby state [“3. Setting of SLP_EN bit causes a hardware interrupt to EP 34. EP 34 evaluates the interrupt and determines that system wants to go into hibernate sleep state. EP 34 initiates a partial power-down of the platform by shutting down processor cores 22, and all user visible platform hardware; leaving only DRAM 20 powered. Note that this could be alternatively triggered after some amount of delay (e.g., 15 minutes) thus allowing the system to use conventional S3 for short duration sleep intervals, and only trigger the hibernate function after an extended S3 interval (e.g., 15 minutes).”] [para. 0032]; and
the suspend to storage condition is satisfied in response to the amount of time being greater than a threshold amount of time [“3. Setting of SLP_EN bit causes a hardware interrupt to EP 34. EP 34 evaluates the interrupt and determines that system wants to go into hibernate sleep state. EP 34 initiates a partial power-down of the platform by shutting down processor cores 22, and all user visible platform hardware; leaving only DRAM 20 powered. Note that this could be alternatively triggered after some amount of delay (e.g., 15 minutes) thus allowing the system to use conventional S3 for short duration sleep intervals, and only trigger the hibernate function after an extended S3 interval (e.g., 15 minutes).”] [para. 0032].
Claim 15 is rejected with like reasoning.
As per claim 9, Jones in view of Cooper and further in view of Dev discloses the method of Claim 1 Cooper teaches further comprising performing a bootloader routine in response to the microcontroller receiving a power-on command and the DRAM operating in the off state [“Upon the occurrence of a wake event (initiation of a resume command), EP 34 powers-on first and immediately initializes DRAM system memory 20 and starts restoring OS DRAM context from fast NVRAM device 38. In some embodiments, this restoring of DRAM occurs even before the processor starts to execute system BIOS code. While the BIOS follows its regular hibernate resume path, EP 34 continues to restore OS context in DRAM 20 and by the time BIOS 48 completes its initialization of processor, chipset, and other platform components, EP 34 has already completed restoring all OS hibernate recovery context in the DRAM. BIOS 48 finishes its execution and passes control to the OS hibernate wake-up vector that was originally embedded within the OS hibernate recovery context in the DRAM and has been restored by the EP along with the rest of the hibernate data. Once getting control, the OS wake-up code immediately starts executing from DRAM 20 and restores remaining OS components using hibernate recovery data in the DRAM. In other embodiments, the details are different. In some embodiments, in resuming from fast hibernate, the BIOS starts executing and initializing system components including DRAM 20, which is initialized because power was lost.”] [paras. 0037 – 0038].
Claim 19 is rejected with like reasoning.
As per claim 10, Jones in view of Cooper and further in view of Dev discloses the method of Claim 1 Cooper teaches further comprising performing a suspend to DRAM routine in response to the microcontroller receiving a power-on command and the DRAM operating in the standby state [“In some embodiments, in resuming from fast hibernate, the BIOS starts executing and initializing system components including DRAM 20, which is initialized because power was lost. NVRAM 34 is also initialized. Once memory is initialized, at least some of the contents of NVRAM 38 is copied to DRAM 20. A software switch in BIOS is done from hibernate (S4) flow to a suspend (S3) flow. The BIOS then jumps to an S3_wake_vector. At this point, the OS has what it needs to proceed with an OS S3_wake.”] [para. 0038].
Claim 20 is rejected with like reasoning.
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claims 1 – 5, 9 – 15, 19, and 20 are rejected under a 103 rejection. Claims 1 – 20 are rejected under a 112 rejection.
Allowable Subject Matter
Claims 6, 7, 8, 16, 17, and 18 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims in independent form.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 6 and 16 the prior art of record, neither anticipates, nor renders obvious a charging characteristic indicates an amount of electrical charge of the DRAM, where a suspend to storage condition is satisfied in response to the amount of electrical charge being less than a threshold amount of electrical charge of the DRAM.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 7 and 17 the prior art of record, neither anticipates, nor renders obvious where the ROM has a sequential read speed of at least 4.2 gigabytes per second.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claims 8 and 18 the prior art of record, neither anticipates, nor renders obvious where the ROM has a sequential write speed of at least 2.8 gigabytes per second.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ito, US Pub. No. 2020/0174876 A1 – teaches “In the MFP, when an instruction to turn off the power to the MFP is given in a state where data that has not been written into the platter is held in the cache memory (hereafter referred to as “the data holding state”), the control unit performs a predetermined shutdown sequence. Specifically, the control unit causes the MFP to enter a standby mode, and before the supply of power to the MFP is stopped, writes the data held in the cache memory into the platter. Thus, in the MFP, even when the supply of power to the MFP is stopped in response to an instruction to turn off the power, data stored in the cache memory can be held without being lost.” [para. 0003]
Biswas et al., US Pub. No. 2016/0116969 A1 – teaches “A method comprising: in a system including a plurality of components coupled to a memory controller having a memory cache capable of entering a cache power down state, the memory controller accessing a memory responsive to memory operations from the plurality of components; caching, in the memory cache, at least some memory data accessed from the memory responsive to the memory operations from the plurality of components; detecting an idle screen for a display device in a system; and disabling the cache power down state in the memory cache responsive to detecting the idle screen.” [claim 1]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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