DETAILED ACTION
Claims 1-20 filed June 10th 2025 are pending in the current action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okazaki et al. (US2011/0062992) in view of Van Acht et al. (US2008/0252338) in view of Itoh et al. (US2007/0008027)
Consider claim 1, where Okazaki teaches an inverter circuit, comprising: an inverted-signal output terminal; (See Okazaki Fig. 16A and ¶167 where the output at node 105 is VL when VH is applied to the input, thus an inverter) a first transistor comprising a control terminal, a first connection terminal, and a second connection terminal, wherein the first connection terminal of the first transistor is electrically connected to the inverted-signal output terminal, the second connection terminal of the first transistor is configured to receive a first low-level voltage, and the control terminal of the first transistor is configured to receive an input signal; (See Okazaki Figs. 16A, 16B and ¶167-169 where transistor 102 has a gate connected to an input, a first terminal connected to the output node 105 and a second terminal connected to VSS) and a second transistor comprising a first control terminal, a second control terminal, a first connection terminal, and a second connection terminal, wherein the first connection terminal and the first control terminal of the second transistor are both configured to receive the inverted -signal output terminal, and the second connection terminal of the second transistor is electrically connected to a high-level voltage; (See Okazaki Figs. 16A, 16B and ¶167-169 where transistor 101 has a gate and a first terminal connected to the output node 105, and a second terminal connected to VDD) wherein when the input signal is at a low level, the first transistor is turned off in response to the input signal, (See Okazaki Fig. 16A, 16B and ¶168 where in the case where V1=VL, the transistor 102 is turned off) wherein when the input signal is at a high level, the first transistor is turned on in response to the input signal, and the second transistor is configured to output a first on-current through the second connection terminal of the second transistor in response to a first control voltage received by the second control terminal, to cause the inverted-signal output terminal to output a low-level signal; (See Okazaki Fig. 16A, 16B and ¶168 where FIG. 16A illustrates the operation in the case where a potential (V1) of the first signal is high (i.e., V1=VH). As illustrated in FIG. 16A, in the case where V1=VH, the transistor 102 is turned on. On the other hand, because of the sufficiently low voltage applied to the back gate electrode, the transistor 101 behaves as an enhancement transistor.) and wherein an on-impedance of the second transistor when the second transistor outputs the first on-current is higher than an on-impedance of the first transistor when the first transistor is turned on, (See Okazaki Figs. 16A, 16B and ¶167-168 where because of the sufficiently low voltage applied to the back gate electrode, the transistor 101 behaves as an enhancement transistor. When the transistor 102 is on, the resistance (R102) of the transistor 102 is lower than the resistance (R101) of the transistor 101 (i.e., R102<R101))
Okazaki teaches a second transistor comprising a first control terminal, a second control terminal, a first connection terminal, and a second connection terminal, wherein the first connection terminal and the first control terminal of the second transistor are both configured to receive the inverted -signal output terminal, and the second connection terminal of the second transistor is electrically connected to a high-level voltage; (See Okazaki Figs. 16A, 16B and ¶167-169 where transistor 101 has a gate and a first terminal connected to the output node 105, and a second terminal connected to VDD) However, Okazaki does not explicitly teach a second transistor comprising a first control terminal, a second control terminal, a first connection terminal, and a second connection terminal, wherein the first connection terminal and the first control terminal of the second transistor are both configured to receive a high-level voltage, and the second connection terminal of the second transistor is electrically connected to the inverted-signal output terminal and the second transistor is turned on since both the first connection terminal and the first control terminal of the second transistor receive the high-level voltage, to cause the inverted-signal output terminal to receive the high-level voltage through the second transistor and output a high-level signal;. However, in an analogous field of endeavor Van Acht teaches a second transistor comprising a first control terminal, a second control terminal, a first connection terminal, and a second connection terminal, wherein the first connection terminal and the first control terminal of the second transistor are both configured to receive a high-level voltage, and the second connection terminal of the second transistor is electrically connected to the inverted-signal output terminal; and the second transistor is turned on since both the first connection terminal and the first control terminal of the second transistor receive the high-level voltage, to cause the inverted-signal output terminal to receive the high-level voltage through the second transistor and output a high-level signal; (See Van Acht Fig. 3 and ¶5, 6 where replacing a depletion/enhancement transistor by a conventional transistor connected in a diode mode, as shown in FIG. 3, may solve problems relating to depletion/enhancement manufacturing cost. The diode connected transistor is turned on and supplies a high voltage to the output node) Therefore, it would have been obvious for one of ordinary skill in the art to substitute the enhancement/depletion transistor 102 of Okazaki with the diode connected transistor shown in Van Acht Fig. 3. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of converting the different types to transistors to be the same type of transistor to save on manufacturing costs.
Okazaki teaches applying a voltage to the back gate, however Okazaki does not explicitly teach the first on-current output from the second transistor varies with the first control voltage. However, in an analogous field of endeavor Itoh teaches the first on-current output from the second transistor varies with the first control voltage (See Itoh Fig. 1 and ¶28-29 where the converter CNV converts a pulse, which is inputted into an input terminal IN and whose amplitude is equal to V.sub.DD, into a same-polarity pulse which is provided with a larger amplitude ranging from V.sub.BB to V.sub.DH. Then, the converter CNV applies this same-polarity and larger-amplitude pulse to the wells of M.sub.P1, and M.sub.N1.) Therefore, it would have been obvious for one of ordinary skill in the art that the back gate control signal Vbkg of Okazaki may take in a converted input as taught by Itoh. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using known methods to dynamically change the threshold voltages to switch between an enhancement mode and depletion mode. (See Itoh ¶29 where the dynamic-mode enhancement/depletion CMOS inverter where, depending on the input, the threshold voltages V.sub.T dynamically change between the enhancement mode and the depletion mode)
Consider claim 2, where Okazaki in view of Van Acht in view of Itoh teaches the inverter circuit of claim 1, further comprising an adjusting sub-circuit, wherein the adjusting sub-circuit comprises a control terminal and a control-voltage output terminal, the control terminal of the adjusting sub-circuit is configured to receive the input signal, and the control-voltage output terminal of the adjusting sub-circuit is electrically connected to the second control terminal of the second transistor; and the adjusting sub-circuit is configured to output the first control voltage to the second control terminal of the second transistor in response to the input signal at the high level. (See Itoh Fig. 1 and ¶28-29 where the converter CNV converts a pulse, which is inputted into an input terminal IN and whose amplitude is equal to V.sub.DD, into a same-polarity pulse which is provided with a larger amplitude ranging from V.sub.BB to V.sub.DH. Then, the converter CNV applies this same-polarity and larger-amplitude pulse to the wells of M.sub.P1, and M.sub.N1.)
Allowable Subject Matter
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 3 recites: “The inverter circuit of claim 2, wherein the adjusting sub-circuit comprises a third transistor, the third transistor comprises a control terminal, a first connection terminal, and a second connection terminal, the control terminal of the third transistor is the control terminal of the adjusting sub-circuit, the second connection terminal of the third transistor is configured to receive a second low-level voltage, and the first connection terminal of the third transistor is the control-voltage output terminal of the adjusting sub-circuit; the third transistor is turned off in response to the input signal at the low level, and is turned on in response to the input signal at the high level and is configured to output the first control voltage to the second control terminal of the second transistor through the first connection terminal of the third transistor; and the first control voltage is the second low-level voltage.” The Examiner finds it non-obvious to substitute to converter of Itoh with the proposed circuit presented in claim 3. Claims 4-8 are objected to as allowable based upon their dependence from claim 3.
Claims 9-20 are allowed.
The following is an examiner’s statement of reasons for allowance: Claims 9 and 17 recites components of a gate driver circuit in conjunction with the inverter circuit as presented in claim 1. While Lee et al. (US2020/0184896) teaches a gate driver of a display with a pull up and pull-down circuit that connects to an inverter, the Examiner finds it non-obvious to combine the circuit with the teachings of Okazaki, Van Acht and Itoh. Claims 10-16 and 18-20 are allowed based upon their dependence from claims 9 and 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM LU whose telephone number is (571)270-1809. The examiner can normally be reached 10am-6:30pm.
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WILLIAM LU
Primary Examiner
Art Unit 2624
/WILLIAM LU/Primary Examiner, Art Unit 2624
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