DETAILED ACTION
1. This Office Action is taken in response to Applicants’ Amendments and Remarks filed on 8/17/2026 regarding application 19/233,614 filed on 6/10/2025.
Claims 1-22 are pending for consideration.
2. Response to Amendments and Remarks
Applicants’ amendments and remarks have been fully and carefully considered, with the Examiner’s response set forth below.
(1) In response to the amendments and remarks, an updated claim analysis has been made with additional, new reference(s). Refer to the corresponding sections of the following Office Action for details.
3. Examiner’s Note
(1) In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
(2) Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-2, 11-13, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Patent Application Publication 2016/0034683, hereinafter Lee), and in view of Byun (US Patent Application Publication 2019/0187931)
As to claim 1, Lee teaches A memory system [memory system as shown in figures 2, 3, and 4; Byun also teaches this limitation – as shown in figure 1], comprising:
one or more memory devices [NVM, figure 2, 1210; flash memory, figure 3, 2210; Byun also teaches this limitation – as shown in figure 1, 150]; and processing circuitry coupled with the one or more memory devices [device controller, figure 2, 1230; Byun also teaches this limitation – as shown in figure 1, 130] and configured to cause the memory system to:
configure a region of a block of the memory system, the region comprising a starting logical block address of the block and a quantity of logical blocks from the starting logical block address of the block [as shown in figures 10-12, where a Write Protection (WP) area has a starting logical block address (starting LBA) and a length; FIG. 10 is a conceptual diagram showing an embodiment where a write protection area is defined in part by the logical block address LBA of a host. Referring to FIG. 10, a partition ID may be “1”. That is, write protection may be applied to a first partition. A start address of a WP Descriptor may be “100”, and a length may be “900”. Thus, the write protection area may start from LBA 100 and may end at LBA 1000. Namely, the start LBA and length define the memory area of the partition, which may be write protected. In FIG. 10, the first partition may be a boot partition where an authentication program is stored, and the write protection area may be an area of the boot partition where the authentication program is stored (¶ 0101); Byun also teaches configuring the memory into regions – A semiconductor memory system includes: a memory device including a first memory region and a second memory region; and a controller suitable for: merging a plurality of write commands, controlling the memory device to perform a write operation of storing a plurality of data corresponding to the merged write commands into the first memory region in a normal mode, and controlling the memory device to perform a write operation of storing data corresponding to each of the plurality of write commands into the second memory region in a boost mode (abstract)];
configure one or more parameters associated with the region, the one or more parameters comprising a mode of operation, a write threshold, or both, wherein the mode of operation is associated with a corresponding type of the write threshold, and wherein a value associated with the write threshold is in accordance with the mode of operation [the corresponding “parameter” is a “mode of operation” represented by the “writable” indicator – as shown in figure 12, where the WP descriptor includes a writable indicator (true or false); Referring to table 1, “writable” may indicate whether the write protection is applied. “Writable” may be set to “True” or “False”. When “writable” is set to “True”, a corresponding area may be writable, and, the write protection may not be applied. When “writable” is set to “False”, a corresponding area may not be writable. That is, the write protection may be applied. “Writable” may be always set to “True” after power-on. When “writable” is set to “False”, it may not be changed before power-off or HW reset. In case of the NV type, “writable” may be changed only by a request of a host 2100 or 3100. In case of the NV-P type, “writable” may be changed by a request of the host 2100 or 3100 ... FIG. 12 is a conceptual diagram showing an embodiment where a WP Descriptor is set to an NV-P type ... “writable” is set to “True”, and a type is set to NV-P. When a UFS system 2000 or 3000 is powered off or hardware reset, “writable” may be changed into “False” because the WP Descriptor is set to the NV-P type. That is, since write protection is applied, it is impossible to perform a write operation about a corresponding area from LBA 100 to LBA 1000 (¶ 0103-0106);
Byun more expressively teaches this limitation via a normal mode and a boost mode, where the type of write thresholds include “data size” and “performance/reliability” – mode selection criteria as shown in figure 6; A semiconductor memory system includes: a memory device including a first memory region and a second memory region; and a controller suitable for: merging a plurality of write commands, controlling the memory device to perform a write operation of storing a plurality of data corresponding to the merged write commands into the first memory region in a normal mode, and controlling the memory device to perform a write operation of storing data corresponding to each of the plurality of write commands into the second memory region in a boost mode (abstract); The write mode unit 500 may have a write mode parameter table 510. The write mode unit 500 may generate a write mode result 517 through write mode parameters included in the write mode parameter table 510 … The write mode parameter table 510 may include various parameters used for determining the boost mode and the normal mode … When the dummy data size 513 is great, high latency is required to merge a plurality of write commands and perform a write operation of storing data into the TLC blocks 551 in the normal mode of a conventional memory system. In accordance with an embodiment of the disclosure, when the dummy data size 513 is greater than a predetermined threshold of dummy data size, the write mode unit 500 may set the write mode to the boost mode … When the required write performance 515 is great, it is a problem that the low reliability of the TLC blocks 551 due to the characteristics of the TLC blocks 551 during a write operation to the TLC blocks 551 in the normal mode of a conventional memory system. The ‘required write performance’ indicates whether the reliability of the data to be written is high. In accordance with an embodiment of the disclosure, when the required write performance 515 is greater than a predetermined threshold of required write performance, the write mode unit 500 may set the write mode to the boost mode. In the boost mode, the controller 130 may control the memory device 150 to perform a write operation to the SLC blocks 553 having a high reliability without merging the plurality of write commands. Therefore, the low reliability in the normal mode as the problem of the prior art may be solved in accordance with an embodiment of the disclosure (¶ 0085-0089); Also, memory cells included in the respective memory blocks BLOCK0 to BLOCKN−1 may be one or more of a single level cell (SLC) memory block storing 1-bit data or a multi-level cell (MLC) memory block storing 2-bit data … The TCL memory blocks may include a plurality of pages which are embodied by plural memory cells, each capable of storing 3-bit data. In yet another embodiment, the memory device 150 may include a plurality of quadruple level cell (QLC) memory blocks. The QLC memory blocks may include a plurality of pages which are embodied by memory cells, each capable of storing 4-bit data … (¶ 0069)]; and
implement a secure write protection procedure for the region in accordance with configuring the one or more parameters [the corresponding “parameter” is a “mode of operation” represented by the “writable” indicator – as shown in figure 12, where the WP descriptor includes a writable indicator (true or false); Referring to table 1, “writable” may indicate whether the write protection is applied. “Writable” may be set to “True” or “False”. When “writable” is set to “True”, a corresponding area may be writable, and, the write protection may not be applied. When “writable” is set to “False”, a corresponding area may not be writable. That is, the write protection may be applied. “Writable” may be always set to “True” after power-on. When “writable” is set to “False”, it may not be changed before power-off or HW reset. In case of the NV type, “writable” may be changed only by a request of a host 2100 or 3100. In case of the NV-P type, “writable” may be changed by a request of the host 2100 or 3100 ... FIG. 12 is a conceptual diagram showing an embodiment where a WP Descriptor is set to an NV-P type ... “writable” is set to “True”, and a type is set to NV-P. When a UFS system 2000 or 3000 is powered off or hardware reset, “writable” may be changed into “False” because the WP Descriptor is set to the NV-P type. That is, since write protection is applied, it is impossible to perform a write operation about a corresponding area from LBA 100 to LBA 1000 (¶ 0103-0106)].
Regarding claim 1, Lee does not expressively teach the mode of operation is associated with a corresponding type of the write threshold, and wherein a value associated with the write threshold is in accordance with the mode of operation.
However, Byun specifically teaches a normal mode and a boost mode for writing data into memory cells, where the mode of operation is associated with a corresponding type of the write threshold, and wherein a value associated with the write threshold is in accordance with the mode of operation [Byun more expressively teaches this limitation via a normal mode and a boost mode, where the type of write thresholds include “data size” and “performance/reliability” – mode selection criteria as shown in figure 6; A semiconductor memory system includes: a memory device including a first memory region and a second memory region; and a controller suitable for: merging a plurality of write commands, controlling the memory device to perform a write operation of storing a plurality of data corresponding to the merged write commands into the first memory region in a normal mode, and controlling the memory device to perform a write operation of storing data corresponding to each of the plurality of write commands into the second memory region in a boost mode (abstract); The write mode unit 500 may have a write mode parameter table 510. The write mode unit 500 may generate a write mode result 517 through write mode parameters included in the write mode parameter table 510 … The write mode parameter table 510 may include various parameters used for determining the boost mode and the normal mode … When the dummy data size 513 is great, high latency is required to merge a plurality of write commands and perform a write operation of storing data into the TLC blocks 551 in the normal mode of a conventional memory system. In accordance with an embodiment of the disclosure, when the dummy data size 513 is greater than a predetermined threshold of dummy data size, the write mode unit 500 may set the write mode to the boost mode … When the required write performance 515 is great, it is a problem that the low reliability of the TLC blocks 551 due to the characteristics of the TLC blocks 551 during a write operation to the TLC blocks 551 in the normal mode of a conventional memory system. The ‘required write performance’ indicates whether the reliability of the data to be written is high. In accordance with an embodiment of the disclosure, when the required write performance 515 is greater than a predetermined threshold of required write performance, the write mode unit 500 may set the write mode to the boost mode. In the boost mode, the controller 130 may control the memory device 150 to perform a write operation to the SLC blocks 553 having a high reliability without merging the plurality of write commands. Therefore, the low reliability in the normal mode as the problem of the prior art may be solved in accordance with an embodiment of the disclosure (¶ 0085-0089); Also, memory cells included in the respective memory blocks BLOCK0 to BLOCKN−1 may be one or more of a single level cell (SLC) memory block storing 1-bit data or a multi-level cell (MLC) memory block storing 2-bit data … The TCL memory blocks may include a plurality of pages which are embodied by plural memory cells, each capable of storing 3-bit data. In yet another embodiment, the memory device 150 may include a plurality of quadruple level cell (QLC) memory blocks. The QLC memory blocks may include a plurality of pages which are embodied by memory cells, each capable of storing 4-bit data … (¶ 0069)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to associate the mode of operation with a corresponding type of the write threshold, and wherein a value associated with the write threshold is in accordance with the mode of operation, as specifically demonstrated by Byun and to incorporate it into the existing scheme disclosed by Lee in, because Byun teaches doing so allows tailoring the different requirements that may arise in different applications for the needs of data size and/or performance/reliability [When the dummy data size 513 is great, high latency is required to merge a plurality of write commands and perform a write operation of storing data into the TLC blocks 551 in the normal mode of a conventional memory system. In accordance with an embodiment of the disclosure, when the dummy data size 513 is greater than a predetermined threshold of dummy data size, the write mode unit 500 may set the write mode to the boost mode … When the required write performance 515 is great, it is a problem that the low reliability of the TLC blocks 551 due to the characteristics of the TLC blocks 551 during a write operation to the TLC blocks 551 in the normal mode of a conventional memory system. The ‘required write performance’ indicates whether the reliability of the data to be written is high. In accordance with an embodiment of the disclosure, when the required write performance 515 is greater than a predetermined threshold of required write performance, the write mode unit 500 may set the write mode to the boost mode. In the boost mode … (¶ 0088-0089); As described above, in accordance with an embodiment of the disclosure, the memory system may dynamically determine the write mode between the boost mode and the normal mode. Accordingly, overall performance of the memory system may be enhanced or improved by setting the write mode to the boost mode in the situation the advantages of the boost mode can be magnified while setting the write mode to the normal mode in the situation the advantages of the normal mode can be magnified (¶ 0115)].
As to claim 2, Lee in view of Byun teaches The memory system of claim 1, wherein the mode of operation indicates that the memory system is to implement the secure write protection procedure in response to configuring the region, and the processing circuitry is further configured to cause the memory system to: implement the secure write protection procedure in response to configuring the region of the block [Lee -- the corresponding “parameter” is a “mode of operation” represented by the “writable” indicator – as shown in figure 12, where the WP descriptor includes a writable indicator (true or false); Referring to table 1, “writable” may indicate whether the write protection is applied. “Writable” may be set to “True” or “False”. When “writable” is set to “True”, a corresponding area may be writable, and, the write protection may not be applied. When “writable” is set to “False”, a corresponding area may not be writable. That is, the write protection may be applied. “Writable” may be always set to “True” after power-on. When “writable” is set to “False”, it may not be changed before power-off or HW reset. In case of the NV type, “writable” may be changed only by a request of a host 2100 or 3100. In case of the NV-P type, “writable” may be changed by a request of the host 2100 or 3100 ... FIG. 12 is a conceptual diagram showing an embodiment where a WP Descriptor is set to an NV-P type ... “writable” is set to “True”, and a type is set to NV-P. When a UFS system 2000 or 3000 is powered off or hardware reset, “writable” may be changed into “False” because the WP Descriptor is set to the NV-P type. That is, since write protection is applied, it is impossible to perform a write operation about a corresponding area from LBA 100 to LBA 1000 (¶ 0103-0106)].
As to claim 11, Lee in view of Byun teaches The memory system of claim 1, wherein: the block comprises a replay-protected memory block (RPMB), and the region of the block comprises a RPMB region [Lee -- A security manager 2234 may manage various sorts of descriptors. The descriptors may include the following: device descriptor, configuration descriptor, geometry descriptor, unit descriptor, replay protected memory block (RPMB) unit descriptor, power parameters descriptor, and interconnect descriptor (¶ 0073)].
As to claim 12, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 13, it recites substantially the same limitations as in claim 2, and is rejected for the same reasons set forth in the analysis of claim 2. Refer to “As to claim 2” presented earlier in this Office Action for details.
As to claim 19, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 20, it recites substantially the same limitations as in claim 2, and is rejected for the same reasons set forth in the analysis of claim 2. Refer to “As to claim 2” presented earlier in this Office Action for details.
5. Claims 3-4, 7, 14, 17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Byun, and further in view of Kim (US Patent Application Publication 2013/0346676).
Regarding claim 3, Lee in view of Byun does not teach the mode of operation indicates that the write threshold is a threshold quantity of program erase cycles performed on the region, and the processing circuitry is further configured to cause the memory system to: monitor a quantity of program erase cycles performed on the region; and implement the secure write protection procedure for the region in response to the quantity of program erase cycles performed on the region satisfying the threshold quantity of program erase cycles.
However, Kim specifically teaches a threshold quantity of program erase cycles performed on the region, and the processing circuitry is further configured to cause the memory system to: monitor a quantity of program erase cycles performed on the region; and implement the secure write protection procedure for the region in response to the quantity of program erase cycles performed on the region satisfying the threshold quantity of program erase cycles [secure write protection procedure as shown in figures 7 and 8, where a memory block is written using SLC mode or MLC mode, depending on its Erase/Write cycles (E/W cycles); The ware-leveling module 135_3 manages the wear levels of blocks of the flash memory devices forming the data storage medium 140. The memory cells of the flash memory devices are aged by program and erase operations. Aged memory cells, that is, worn memory cells may develop a defect, for example, a physical defect. The wear-leveling module 135_3 levels off the erase-write counts of the respective blocks, in order to prevent a specific block of the flash memory devices from being worn more rapidly than the other blocks ... (¶ 0054-0055); FIG. 6 is a table showing a condition for applying the dynamic storage area allocating method according to an embodiment of the present invention. FIG. 6 shows a method for dynamically allocating the storage area based on an optimized lifetime ratio (OLR) ... The OLR is calculated according to the lifetime Ls of the SLC area, the lifetime Lm of the MLC area, an average erase-write count Ms of the SLC area, and an average erase-write count Mm of the MLC area. The lifetime used for calculating the OLR indicates a limit erase-write count of each area, that is the lifetime, or limit wear level, of an area may be defined based on a number of erase-writes that may occur in that area before the lifetime or limit wear level for that area is reached ... (¶ 0061-0062); That is, at step S130, whether or not the erase-write count of the target block is less than the average erase-write count Mm of the MLC area is determined. When the erase-write count of the target block is greater than the average erase-write count Mm of the MLC area, the procedure returns to step S120 to select another target block. That is, a block having a low erase-write count among the memory blocks belonging to the MLC may be selected by considering that the block is to be included in the SLC area and the erase-write count thereof is to increase. On the other hand, when the erase-write count of the target block is less than the average erase-write count Mm of the MLC area, the procedure proceeds to step S140 (¶ 0072); That is, at step S230, whether or not the erase-write count of the target block is less than the average erase-write count Mm of the MLC area is determined. When the erase-write count of the target block is greater than the average erase-write count Mm of the MLC area, the procedure returns to step S220 to select another target block. That is, since a memory block having a greater erase-write count than the average erase-write count Mm of the MLC area may increase the average erase-write number Mm of the MLC area, a block having a lower erase-write count than the average erase-write count Mm of the MLC area may be selected from the memory blocks belonging to the SLC area. On the other hand, when the erase-write number of the target block is less than the average erase-write number Mm of the MLC area, the procedure proceeds to step S240 (¶ 0082)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to monitor the program erase cycles performed on the region and to implement the secure write protection procedure for the region in response to the quantity of program erase cycles performed on the region satisfying the threshold quantity of program erase cycles, as specifically demonstrated by Kim and to incorporate it into the existing scheme disclosed by Lee in view of Byun, because Kim teaches doing so optimizes the lifetime of the memory device [FIG. 6 is a table showing a condition for applying the dynamic storage area allocating method according to an embodiment of the present invention. FIG. 6 shows a method for dynamically allocating the storage area based on an optimized lifetime ratio (OLR) ... The OLR is calculated according to the lifetime Ls of the SLC area, the lifetime Lm of the MLC area, an average erase-write count Ms of the SLC area, and an average erase-write count Mm of the MLC area. The lifetime used for calculating the OLR indicates a limit erase-write count of each area, that is the lifetime, or limit wear level, of an area may be defined based on a number of erase-writes that may occur in that area before the lifetime or limit wear level for that area is reached ... (¶ 0061-0062)].
As to claim 4, Lee in view of Byun & Kim teaches The memory system of claim 3, wherein: the threshold quantity of program erase cycles corresponds to a threshold percentage of predicted lifetime for the region, and the quantity of program erase cycles corresponds to a percentage of predicted lifetime for the region [Kim – FIG. 6 is a table showing a condition for applying the dynamic storage area allocating method according to an embodiment of the present invention. FIG. 6 shows a method for dynamically allocating the storage area based on an optimized lifetime ratio (OLR) ... The OLR is calculated according to the lifetime Ls of the SLC area, the lifetime Lm of the MLC area, an average erase-write count Ms of the SLC area, and an average erase-write count Mm of the MLC area. The lifetime used for calculating the OLR indicates a limit erase-write count of each area, that is the lifetime, or limit wear level, of an area may be defined based on a number of erase-writes that may occur in that area before the lifetime or limit wear level for that area is reached ... When the OLR is less than 1, it means that the average erase-write count Mm of the MLC area is high ... When the OLR is 1, it means that the average erase-write count Ms of the SLC area and the average erase-write count Mm of the MLC area are normal ... When the OLR is greater than 1, it means that the average erase-write count Ms of the SLC area is high ... (¶ 0061-0065)].
As to claim 7, Lee in view of Byun & Kim teaches The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: switch the mode of operation associated with the region from a first mode of operation to a second mode of operation, the first mode of operation being associated with a first type of the write threshold and the second mode of operation being associated with a second type of the write threshold, wherein implementing the secure write protection procedure is in accordance with switching the mode of operation associated with the region [Kim -- secure write protection procedure as shown in figures 7 and 8, where a memory block is written using SLC mode or MLC mode, depending on its Erase/Write cycles (E/W cycles); The ware-leveling module 135_3 manages the wear levels of blocks of the flash memory devices forming the data storage medium 140. The memory cells of the flash memory devices are aged by program and erase operations. Aged memory cells, that is, worn memory cells may develop a defect, for example, a physical defect. The wear-leveling module 135_3 levels off the erase-write counts of the respective blocks, in order to prevent a specific block of the flash memory devices from being worn more rapidly than the other blocks ... (¶ 0054-0055); FIG. 6 is a table showing a condition for applying the dynamic storage area allocating method according to an embodiment of the present invention. FIG. 6 shows a method for dynamically allocating the storage area based on an optimized lifetime ratio (OLR) ... The OLR is calculated according to the lifetime Ls of the SLC area, the lifetime Lm of the MLC area, an average erase-write count Ms of the SLC area, and an average erase-write count Mm of the MLC area. The lifetime used for calculating the OLR indicates a limit erase-write count of each area, that is the lifetime, or limit wear level, of an area may be defined based on a number of erase-writes that may occur in that area before the lifetime or limit wear level for that area is reached ... (¶ 0061-0062); That is, at step S130, whether or not the erase-write count of the target block is less than the average erase-write count Mm of the MLC area is determined. When the erase-write count of the target block is greater than the average erase-write count Mm of the MLC area, the procedure returns to step S120 to select another target block. That is, a block having a low erase-write count among the memory blocks belonging to the MLC may be selected by considering that the block is to be included in the SLC area and the erase-write count thereof is to increase. On the other hand, when the erase-write count of the target block is less than the average erase-write count Mm of the MLC area, the procedure proceeds to step S140 (¶ 0072); That is, at step S230, whether or not the erase-write count of the target block is less than the average erase-write count Mm of the MLC area is determined. When the erase-write count of the target block is greater than the average erase-write count Mm of the MLC area, the procedure returns to step S220 to select another target block. That is, since a memory block having a greater erase-write count than the average erase-write count Mm of the MLC area may increase the average erase-write number Mm of the MLC area, a block having a lower erase-write count than the average erase-write count Mm of the MLC area may be selected from the memory blocks belonging to the SLC area. On the other hand, when the erase-write number of the target block is less than the average erase-write number Mm of the MLC area, the procedure proceeds to step S240 (¶ 0082)].
As to claim 14, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
As to claim 17, it recites substantially the same limitations as in claim 7, and is rejected for the same reasons set forth in the analysis of claim 7. Refer to “As to claim 7” presented earlier in this Office Action for details.
As to claim 21, it recites substantially the same limitations as in claim 3, and is rejected for the same reasons set forth in the analysis of claim 3. Refer to “As to claim 3” presented earlier in this Office Action for details.
6. Claims 5-6, 8-11, 15-16, 18, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Byun, and in view of Kim (US Patent Application Publication 2019/0236031).
Regarding claim 5, Lee in view of Byun does not teach monitor a quantity of bytes of data written to the region; and implement the secure write protection procedure for the region in response to the quantity of bytes of data written to the region satisfying the threshold quantity of bytes.
However, Kim specifically teaches monitor a quantity of bytes of data written to the region; and implement the secure write protection procedure for the region in response to the quantity of bytes of data written to the region satisfying the threshold quantity of bytes [The write counter 162 may store a counter value indicating the number of authenticated data write requests and authenticated device configuration write requests. The write counter 162 may have a length of 4 bytes. An initial counter value may be 0x0000 0000. The counter value cannot be reset, and may not be increased further when the counter value reaches a maximum value of 0xFFFF FFFF. In an embodiment, when the value of the write counter 162 reaches the maximum value, a specific bit of a result register 203 may be permanently set (¶ 0056); In detail, when the MAC included in the write request from the host 300 matches the calculated MAC, the storage device 50 may compare a write counter value included in the write request with a write counter value stored in the write counter 162. When the write counter values are identical to each other, the write request from the host 300 may be determined to be authenticated (¶ 0093)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to monitor a quantity of bytes of data written to the region; and implement the secure write protection procedure for the region in response to the quantity of bytes of data written to the region satisfying the threshold quantity of bytes, as specifically demonstrated by Kim and to incorporate it into the existing scheme disclosed by Lee in view of Byun, because Kim teaches doing so allows confirmation that all write data is successfully received [In detail, when the MAC included in the write request from the host 300 matches the calculated MAC, the storage device 50 may compare a write counter value included in the write request with a write counter value stored in the write counter 162. When the write counter values are identical to each other, the write request from the host 300 may be determined to be authenticated (¶ 0093)].
As to claim 6, Lee in view of Byun & Kim teaches The memory system of claim 1, wherein the mode of operation indicates that the write threshold is a threshold quantity of bytes available to be written to the region, and the processing circuitry is further configured to cause the memory system to: implement the secure write protection procedure for the region in response to an available quantity of bytes in the region satisfying the threshold quantity of bytes available at the region [Kim -- The write counter 162 may store a counter value indicating the number of authenticated data write requests and authenticated device configuration write requests. The write counter 162 may have a length of 4 bytes. An initial counter value may be 0x0000 0000. The counter value cannot be reset, and may not be increased further when the counter value reaches a maximum value of 0xFFFF FFFF. In an embodiment, when the value of the write counter 162 reaches the maximum value, a specific bit of a result register 203 may be permanently set (¶ 0056); In detail, when the MAC included in the write request from the host 300 matches the calculated MAC, the storage device 50 may compare a write counter value included in the write request with a write counter value stored in the write counter 162. When the write counter values are identical to each other, the write request from the host 300 may be determined to be authenticated (¶ 0093)].
As to claim 8, Lee in view of Byun & Kim teaches The memory system of claim 1, wherein, to secure write protection procedure, the processing circuitry is further configured to cause the memory system to: determine whether to prohibit or allow an authenticated data write command to access the region in accordance with a first message authentication code (MAC) included in the authenticated data write command and a second MAC associated with the region [Lee -- Referring to table 5, the WP Descriptor Update Counter may mean a counter value requested up to now. “Nonce” may mean a random number for protecting replay attack. The WP Descriptor may mean a WP Descriptor to be applied or applied. “Result” may mean a result on a request and may provide whether a request is passed or failed and fail causes. The Hash-based Message Authentication Code (HMAC) may be used to authenticate a request. The host 3100 may calculate the HMAC for the WP Descriptor Update Request using a key and a message. FIG. 14 is a conceptual diagram for describing a method of calculating HMAC. HMAC may be calculated by a security manager 3234 shown in FIG. 9 of the HMAC 3250. Referring to FIG. 14, a security manager 3234 may calculate HMAC using a private key and a message. The message may include the following: Request Type, WP Descriptor Update Counter, Nonce, WP Descriptor, and Result. The security manager 3234 may calculate HMAC using MD5, SHA1, SHA256, etc. (¶ 0120-0121);
Kim more expressively teaches this limitation – The RPMB engine 210 may control a read operation and a write operation on the RPMB 160 using an authentication key. In an embodiment, the authentication key may allow a read operation and a write operation on the RPMB 160 using a message authentication code (MAC). The authentication key may be programmed in advance in a secure environment. The authentication key may be stored in the RPMB 160 ... The RPMB engine 210 may calculate the MAC using the hash algorithm from the provided data and the authentication key stored in the RPMB 160, and may compare the calculated MAC with the MAC received from the host 300. When the calculated MAC matches the MAC received from the host 300, the RPMB engine 210 may determine that the data received from the host 300 is not compromised (¶ 0049-0051); In detail, when the MAC included in the write request from the host 300 matches the calculated MAC, the storage device 50 may compare a write counter value included in the write request with a write counter value stored in the write counter 162. When the write counter values are identical to each other, the write request from the host 300 may be determined to be authenticated (¶ 0093)].
As to claim 9, Lee in view of Byun & Kim teaches The memory system of claim 8, wherein, to determine whether to prohibit or allow the authenticated data write command to access the region, the processing circuitry is further configured to cause the memory system to: determine to prohibit access to the region in response to the first MAC being different from the second MAC [Lee -- Referring to table 5, the WP Descriptor Update Counter may mean a counter value requested up to now. “Nonce” may mean a random number for protecting replay attack. The WP Descriptor may mean a WP Descriptor to be applied or applied. “Result” may mean a result on a request and may provide whether a request is passed or failed and fail causes. The Hash-based Message Authentication Code (HMAC) may be used to authenticate a request. The host 3100 may calculate the HMAC for the WP Descriptor Update Request using a key and a message. FIG. 14 is a conceptual diagram for describing a method of calculating HMAC. HMAC may be calculated by a security manager 3234 shown in FIG. 9 of the HMAC 3250. Referring to FIG. 14, a security manager 3234 may calculate HMAC using a private key and a message. The message may include the following: Request Type, WP Descriptor Update Counter, Nonce, WP Descriptor, and Result. The security manager 3234 may calculate HMAC using MD5, SHA1, SHA256, etc. (¶ 0120-0121);
Kim more expressively teaches this limitation – The RPMB engine 210 may control a read operation and a write operation on the RPMB 160 using an authentication key. In an embodiment, the authentication key may allow a read operation and a write operation on the RPMB 160 using a message authentication code (MAC). The authentication key may be programmed in advance in a secure environment. The authentication key may be stored in the RPMB 160 ... The RPMB engine 210 may calculate the MAC using the hash algorithm from the provided data and the authentication key stored in the RPMB 160, and may compare the calculated MAC with the MAC received from the host 300. When the calculated MAC matches the MAC received from the host 300, the RPMB engine 210 may determine that the data received from the host 300 is not compromised (¶ 0049-0051); In detail, when the MAC included in the write request from the host 300 matches the calculated MAC, the storage device 50 may compare a write counter value included in the write request with a write counter value stored in the write counter 162. When the write counter values are identical to each other, the write request from the host 300 may be determined to be authenticated (¶ 0093)].
As to claim 10, Lee in view of Byun & Kim teaches The memory system of claim 8, wherein, to determine whether to prohibit or allow the authenticated data write command to access the region, the processing circuitry is further configured to cause the memory system to: determine to allow access to the region in response to the first MAC being equal to the second MAC [Lee -- Referring to table 5, the WP Descriptor Update Counter may mean a counter value requested up to now. “Nonce” may mean a random number for protecting replay attack. The WP Descriptor may mean a WP Descriptor to be applied or applied. “Result” may mean a result on a request and may provide whether a request is passed or failed and fail causes. The Hash-based Message Authentication Code (HMAC) may be used to authenticate a request. The host 3100 may calculate the HMAC for the WP Descriptor Update Request using a key and a message. FIG. 14 is a conceptual diagram for describing a method of calculating HMAC. HMAC may be calculated by a security manager 3234 shown in FIG. 9 of the HMAC 3250. Referring to FIG. 14, a security manager 3234 may calculate HMAC using a private key and a message. The message may include the following: Request Type, WP Descriptor Update Counter, Nonce, WP Descriptor, and Result. The security manager 3234 may calculate HMAC using MD5, SHA1, SHA256, etc. (¶ 0120-0121);
Kim more expressively teaches this limitation – The RPMB engine 210 may control a read operation and a write operation on the RPMB 160 using an authentication key. In an embodiment, the authentication key may allow a read operation and a write operation on the RPMB 160 using a message authentication code (MAC). The authentication key may be programmed in advance in a secure environment. The authentication key may be stored in the RPMB 160 ... The RPMB engine 210 may calculate the MAC using the hash algorithm from the provided data and the authentication key stored in the RPMB 160, and may compare the calculated MAC with the MAC received from the host 300. When the calculated MAC matches the MAC received from the host 300, the RPMB engine 210 may determine that the data received from the host 300 is not compromised (¶ 0049-0051); In detail, when the MAC included in the write request from the host 300 matches the calculated MAC, the storage device 50 may compare a write counter value included in the write request with a write counter value stored in the write counter 162. When the write counter values are identical to each other, the write request from the host 300 may be determined to be authenticated (¶ 0093)].
As to claim 11, Lee in view of Byun & Kim teaches The memory system of claim 1, wherein: the block comprises a replay-protected memory block (RPMB), and the region of the block comprises a RPMB region [Lee -- A security manager 2234 may manage various sorts of descriptors. The descriptors may include the following: device descriptor, configuration descriptor, geometry descriptor, unit descriptor, replay protected memory block (RPMB) unit descriptor, power parameters descriptor, and interconnect descriptor (¶ 0073); Kim -- Provided herein may be a storage device and a method of operating the same. The method of operating a storage device including a replay protected memory block (RPMB) may include receiving a write request for the RPMB from an external host, selectively storing data in the RPMB based on an authentication operation, receiving a read request from the external host, and providing result data to the external host in response to the read request, wherein the read request includes a message indicating that a read command to be subsequently received from the external host is a command related to the result data (abstract)].
As to claim 15, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
As to claim 16, it recites substantially the same limitations as in claim 6, and is rejected for the same reasons set forth in the analysis of claim 6. Refer to “As to claim 6” presented earlier in this Office Action for details.
As to claim 18, it recites substantially the same limitations as in claim 8, and is rejected for the same reasons set forth in the analysis of claim 8. Refer to “As to claim 8” presented earlier in this Office Action for details.
As to claim 22, it recites substantially the same limitations as in claim 5, and is rejected for the same reasons set forth in the analysis of claim 5. Refer to “As to claim 5” presented earlier in this Office Action for details.
Conclusion
7. Claims 1-22 are rejected as explained above.
8. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE
MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG JEN TSAI whose telephone number is 571-272-4244. The examiner can normally be reached on Monday-Friday, 9-6.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on 571-272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG JEN TSAI/Primary Examiner, Art Unit 2139
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