Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 10 June 2025 for application number 19/233,617. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 09 May 2022 (KR10-2022-0056787).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10 June 2025 and 26 March 2025 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 5, 6, 9, 11 – 15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hinkle [hereafter as Hinkle], US Pub. No. 2023/0297236 A1 in view of Choi et al. [hereafter as Choi], US Pub. No. 2020/0142766 A1 and further in view of Maeda et al. [hereafter as Maeda], US Pub. No. 2014/0059224 A1.
As per claim 1, Hinkle storage device comprising:
a nonvolatile memory [“The far memory device 30 includes a far memory controller 32, one or more memory devices 34”] [para. 0036]; and
a storage controller [“The non-volatile data storage drive 50 includes a drive controller 52 …”] [para. 0037] configured to:
control the nonvolatile memory based on control of a host device [“The non-volatile data storage drive 50 includes a drive controller 52, persistent memory 54 coupled to the drive controller 52, a first port (Port 1) 56 coupled to the drive controller 52 for supporting the connection 22 to the host…”] [para. 0037];
connect to the host device through a first interface [“…a first port (Port 1) 56 coupled to the drive controller 52 for supporting the connection 22 to the host… and a second port (Port 2) 58 coupled to the drive controller 52 for supporting the connection 24 to the far memory ...”] [para. 0037];
connect to an external memory device through a second interface [Port 2 58, Fig. 1] that is physically separated from the first interface [Port 1 56, Fig. 1] [“…a first port (Port 1) 56 coupled to the drive controller 52 for supporting the connection 22 to the host… and a second port (Port 2) 58 coupled to the drive controller 52 for supporting the connection 24 to the far memory ...”] [para. 0037];
the external memory device through the second interface [“…a first port (Port 1) 56 coupled to the drive controller 52 for supporting the connection 22 to the host… and a second port (Port 2) 58 coupled to the drive controller 52 for supporting the connection 24 to the far memory ...”] [para. 0037]; and
the external memory device through the second interface [“…a first port (Port 1) 56 coupled to the drive controller 52 for supporting the connection 22 to the host… and a second port (Port 2) 58 coupled to the drive controller 52 for supporting the connection 24 to the far memory ...”] [para. 0037];
the external memory device [“…the far memory ...”] [para. 0037].
However, Hinkle does not explicitly disclose in an initialization operation, send a device information request to the memory device; and
in the initialization operation, receive a device information response corresponding to the device information request from the memory device;
wherein the device information response comprises information about a device type and a storage capacity of the memory device.
Choi teaches in an initialization operation, send a device information request [“further comprising performing an initialization operation for providing, by the storage device, the DTH information to the host, wherein the performing of the initialization operation includes: receiving device information request message from the host; and providing device information of the storage device in response to the device information request message.”] [claim 12]; and
in the initialization operation, receive a device information response corresponding to the device information request [“further comprising performing an initialization operation for providing, by the storage device, the DTH information to the host, wherein the performing of the initialization operation includes: receiving device information request message from the host; and providing device information of the storage device in response to the device information request message.”] [claim 12];
Hinkle and Choi are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Hinkle with Choi in order to modify Hinkle where “in an initialization operation, send a device information request; and
in the initialization operation, receive a device information response corresponding to the device information request” as taught by Choi. One of ordinary skill in the art would be motivated to combine Hinkle with Choi before the effective filing date of the claimed invention to improve a system by providing for the ability where a “memory controller … may control the memory devices according to an interleaving scheme so as to improve operational performance.” [Choi, para. 0064].
However, Hinkle and Choi do not explicitly disclose wherein the device information response comprises information about a device type and a storage capacity of the memory device.
Maeda teaches wherein the device information response comprises information about a device type and a storage capacity of the memory device [“the characteristic information includes at least one piece of capacity information indicating overall capacity of the additional device, memory state information indicating whether writing to the additional device is allowed, identifier information including an identifier identifying a type of the additional device,”] [para. 0016].
Hinkle, Choi, and Maeda are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Hinkle and Choi with Maeda in order to modify Hinkle and Choi “wherein the device information response comprises information about a device type and a storage capacity of the memory device” as taught by Maeda. One of ordinary skill in the art would be motivated to combine Hinkle and Choi with Maeda before the effective filing date of the claimed invention to improve a system by providing for the ability for “a reduction in the frequency of an initialization process of the nonvolatile memory … and an increase in the speed of a connection process are achieved.” [Maeda, para. 0049].
Claim 12 is rejected with like reasoning as claim 1 above and claim 3 below, except for the following remaining claim limitations:
a buffer memory configured to store a map data of the external storage device; and
the buffer memory.
Hinkle discloses a buffer memory configured to store a map data of the external storage device [“This volatile memory may include additional higher levels of volatile memory (not shown), including, but not limited to, cache memory, registers and buffers.”] [para. 0040] [“FIG. 2 is a table representing the memory map 44 according to some embodiments. Although the memory map 44 may have various data structures, the map 44 is illustrated as a table in which each row forms a record.”] [para. 0038]; and
the buffer memory [“This volatile memory may include additional higher levels of volatile memory (not shown), including, but not limited to, cache memory, registers and buffers.”] [para. 0040].
Claim 17 is rejected with like reasoning as claims 1, 5, 12.
As per claim 2, Hinkle in view of Choi and further in view of Maeda discloses the storage device of claim 1, Hinkle discloses wherein the storage controller is further configured to allocate at least a portion of the external memory device as a dedicated region for the storage device based on the storage capacity of the external memory device [“Any amount or region of the far memory may be used as regular memory, including … some percentage, … Accordingly, the far memory controller may identify those portions of far memory that are cleared and available for the host processor to use as regular memory.”] [para. 0024].
Choi teaches allocate [“size of an area that is to be allocated”] [para. 0066].
Claim 13 is rejected with like reasoning.
As per claim 3, Hinkle in view of Choi and further in view of Maeda discloses the storage device of claim 1, Hinkle discloses wherein the first interface and the second interface are based on a compute express link (CXL) protocol [“… the coherent protocol interface that connects the far memory to the host processor may implement the Compute Express Link (CXL) open standard for high-speed CPU-to-device and CPU-to-memory connections. CXL is built on the PCIe physical and electrical interface with additional protocols for input/output (I/O),...”] [para. 0031].
As per claim 5, Hinkle in view of Choi and further in view of Maeda discloses the storage device of claim 1, Hinkle discloses wherein the storage controller sends a map data that is stored in the nonvolatile memory to the external memory device through the second interface [“The one or more memory devices 34 may be either volatile or persistent memory devices. In addition, the one or more memory devices 34 may store data 42 being cached, a map 44 associating the location or address of data 42 on the memory device 34 with a corresponding location or address on the non-volatile data storage drive 50, which may be a dual-ported NVMe drive.”] [para. 0036].
Choi teaches in an initialization operation, sends data [“further comprising performing an initialization operation for providing, by the storage device, the DTH information to the host, wherein the performing of the initialization operation includes: receiving device information request message from the host; and providing device information of the storage device in response to the device information request message.”] [claim 12].
Claim 14 is rejected with like reasoning.
As per claim 6, Hinkle in view of Choi and further in view of Maeda discloses the storage device of claim 1, Maeda teaches wherein, in the initialization operation, the host device identifies the information about the device type and the storage capacity of the storage device. [“the characteristic information includes at least one piece of capacity information indicating overall capacity of the additional device, memory state information indicating whether writing to the additional device is allowed, identifier information including an identifier identifying a type of the additional device,”] [para. 0016] [“The idea of the present disclosure can be applied to a host apparatus and a functional device …”] [para. 0188].
As per claim 9, Hinkle in view of Choi and further in view of Maeda discloses the storage device of claim 1, Hinkle discloses wherein the storage controller communicates with the host device through the first interface using CXL.io [“… the coherent protocol interface that connects the far memory to the host processor may implement the Compute Express Link (CXL) open standard for high-speed CPU-to-device and CPU-to-memory connections. CXL is built on the PCIe physical and electrical interface with additional protocols for input/output (I/O),...”] [para. 0031], and
wherein the storage controller communicates with the external memory device through the second interface using at least one of the CXL.io and CXL.mcm [“…CXL is built on the PCIe physical and electrical interface with additional protocols for input/output (I/O), … far memory device may leverage the CXL.mem memory protocol ..”] [para. 0031].
As per claim 11, Hinkle in view of Choi and further in view of Maeda discloses the storage device of claim 1, Hinkle discloses wherein the first interface includes a switch configured to mediate communication between the storage controller and the host device [“Embodiments of the computing system provide for a direct connection between a far memory device and a non-volatile data storage drive to support direct communication there between. A direct connection between the far memory device and the non-volatile data storage drive may be established through a backplane, a direct cable connection or through a PCIe/CXL switch. In addition to the direct connection between the far memory device and the non-volatile data storage drive, the far memory device and the non-volatile data storage drive may each have their own direct connection with the host processor, such as a PCIe connection, to support direct communication there between.”] [para. 0030].
As per claim 15, Hinkle in view of Choi and further in view of Maeda discloses the memory device of claim 12, Hinkle discloses wherein the memory controller communicates with the external storage device through the first interface using at least one of the CXL. io and CXL.mem [“In some embodiments of the computing system, the coherent protocol interface that connects the far memory to the host processor may implement the Compute Express Link (CXL) open standard for high-speed CPU-to-device and CPU-to-memory connections. CXL is built on the PCIe physical and electrical interface with additional protocols for input/output (I/O), memory and cache coherence. With a CXL connection, the far memory device may leverage the CXL.mem memory protocol and/or CXL.cache cache protocol to present byte-addressable memory to the CPU”] [para. 0031].
As per claim 20, Hinkle in view of Choi and further in view of Maeda discloses the operating method of claim 17, Hinkle discloses wherein the first interface and the second interface are based on a compute express link (CXL) protocol and the second interface is based on at least one of CXL.i io and CXL.mem [“In some embodiments of the computing system, the coherent protocol interface that connects the far memory to the host processor may implement the Compute Express Link (CXL) open standard for high-speed CPU-to-device and CPU-to-memory connections. CXL is built on the PCIe physical and electrical interface with additional protocols for input/output (I/O), memory and cache coherence. With a CXL connection, the far memory device may leverage the CXL.mem memory protocol and/or CXL.cache cache protocol to present byte-addressable memory to the CPU”] [para. 0031].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hinkle [hereafter as Hinkle], US Pub. No. 2023/0297236 A1 in view of Choi et al. [hereafter as Choi], US Pub. No. 2020/0142766 A1 and further in view of Maeda et al. [hereafter as Maeda], US Pub. No. 2014/0059224 A1 as applied to claim 1 above, and further in view of Shan et al. [hereafter as Shan], US Patent No. 11,132,313 B2.
As per claim 4, Hinkle in view of Choi and further in view of Maeda discloses the storage device of claim 1, however Hinkle, Choi, and Maeda wherein the external memory device is accessible only by the storage device.
Shan teaches wherein the memory [Memory 104, Fig. 1] is accessible only by the storage device [102, Fig. 1] [Examiner is interpreting item 102 as a storage device because it contains storage space].
Hinkle, Choi, Maeda, and Shan are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Hinkle, Choi, and Maeda with Shan in order to modify Hinkle, Choi, and Maeda “wherein the memory is accessible only by the storage device” as taught by Shan. One of ordinary skill in the art would be motivated to combine Hinkle, Choi, and Maeda with Shan before the effective filing date of the claimed invention to improve a system by providing for the ability where “data can be transmitted in respective formats between the at least one first interface and the at least one second interface.” [Shan, Abstract].
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hinkle [hereafter as Hinkle], US Pub. No. 2023/0297236 A1 in view of Choi et al. [hereafter as Choi], US Pub. No. 2020/0142766 A1 and further in view of Maeda et al. [hereafter as Maeda], US Pub. No. 2014/0059224 A1 as applied to claim 5 above, and further in view of Kim [hereafter as Kim1], US Pub. No. 2022/0121517 A1.
As per claim 10, Hinkle in view of Choi and further in view of Maeda discloses the storage device of claim 5, Hinkle discloses wherein the storage controller further comprises a direct memory access (DMA) configured to transfer the map data to the external memory device independently of control by the host device [“Embodiments of the computing system provide for a direct connection between a far memory device and a non-volatile data storage drive to support direct communication there between. A direct connection between the far memory device and the non-volatile data storage drive may be established through a backplane, a direct cable connection or through a PCIe/CXL switch. In addition to the direct connection between the far memory device and the non-volatile data storage drive, the far memory device and the non-volatile data storage drive may each have their own direct connection with the host processor, such as a PCIe connection, to support direct communication there between.”] [para. 0030] [“The one or more memory devices 34 may be either volatile or persistent memory devices. In addition, the one or more memory devices 34 may store data 42 being cached, a map 44 associating the location or address of data 42 on the memory device 34 with a corresponding location or address on the non-volatile data storage drive 50, which may be a dual-ported NVMe drive.”] [para. 0036].
However, Hinkle, Choi, and Maeda do not explicitly disclose a (DMA) engine.
Kim1 teaches a (DMA) engine [“and a direct memory access (DMA) component configured to provide the first map data”] [para. 0008].
Hinkle, Choi, Maeda, and Kim1 are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Hinkle, Choi, and Maeda with Kim1 in order to modify Hinkle, Choi, and Maeda for “a (DMA) engine” as taught by Kim1. One of ordinary skill in the art would be motivated to combine Hinkle, Choi, and Maeda with Kim1 before the effective filing date of the claimed invention to improve a system by providing for the ability where the system “controls the NVM … in response to a request from the host.” [Kim1, para. 0051].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hinkle [hereafter as Hinkle], US Pub. No. 2023/0297236 A1 in view of Choi et al. [hereafter as Choi], US Pub. No. 2020/0142766 A1 and further in view of Maeda et al. [hereafter as Maeda], US Pub. No. 2014/0059224 A1 as applied to claim 12 above, and further in view of Kim [hereafter as Kim2], US Pub. No. 2019/0324664 A1.
As per claim 16, Hinkle in view of Choi and further in view of Maeda discloses the memory device of claim 12, however Hinkle, Choi, and Maeda do not explicitly disclose wherein the memory device supports a hot-plug function.
Kim2 teaches wherein the memory device supports a hot-plug function [“input/output interface may be a serial interface that can support Hot-plug to connect and disconnect the memory devices easily.”] [para. 0059].
Hinkle, Choi, Maeda, and Kim2 are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Hinkle, Choi, and Maeda with Kim2 in order to modify Hinkle, Choi, and Maeda for “a (DMA) engine” as taught by Kim2. One of ordinary skill in the art would be motivated to combine Hinkle, Choi, and Maeda with Kim2 before the effective filing date of the claimed invention to improve a system by providing for the ability to “support Hot-plug to connect and disconnect the memory device easily.” [Kim2, para. 0048].
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claims 1 – 6, 9 – 17, and 20 are rejected under a 103 rejection.
Allowable Subject Matter
Claims 7, 8, and 18 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten in independent form to include all of the limitations of the base claim and any intervening claims. Claim 19 depends upon claim 18 and is objected as considered as containing allowable subject matter based upon its dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 7 the prior art of record, neither anticipates, nor renders obvious receiving a first write request from a host device through a first interface and writing data corresponding to the first write request in a nonvolatile memory, then sending a first write response that corresponds to the first write request to the host device through the first interface, and sending a second write request for partial map data that has been updated based on the first write request to an external memory device through the second interface.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 8 the prior art of record, neither anticipates, nor renders obvious receiving power-off information from a host device through a first interface and sending a read request to an external memory device through a second interface, storing map data included in a read response that is received from the external memory device in the nonvolatile memory based on the power-off information, and sending a response of the power-off information to the host device through the first interface.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 18 the prior art of record, neither anticipates, nor renders obvious determining a buffer capacity based on the storage capacity of an external memory device. Claim 19 depends on claim 18 and would be allowable.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hasbun et al., US Pub. No. 2019/0347035 A1 – teaches “Buffer 240 may in some cases be configured to operate as a logical augmentation of cache memory 255 within SoC/processor 250. In some examples, the capacity of buffer 240 may be on the order of 256 M bytes. In some examples, the capacity of buffer 240 may be based on the size of cache memory 255 in SoC/processor 250.” [para. 0040]
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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