DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 10 June 2025.
Claims 1-20 are pending and have been presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 8 and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over WON (U.S. Patent Application Publication #2024/0257844) in view of TRAININ (U.S. Patent Application Publication #2023/0214389).
1. WON discloses A bank-level dynamic random access memory (DRAM) (see [0024]: DRAM) process-in- memory (DRAM-PIM) filtering (see [0024]: memory device may be a processing-in-memory device) architecture to accelerate database online analytical processing (OLAP) queries, comprising: a DRAM chip comprising multiple memory banks (see [0024]: memory circuits composed of memory banks), each memory bank comprising: multiple sub-arrays in which data is stored in horizontal layouts, with each byte present in a same row of the corresponding one of the multiple sub-arrays (see TRAININ below); a per-bank global data bus, by which the data of one sub-array at a time flows relative to the memory bank (see [0028]: the GIO line allows access to the plurality of memory circuits); and a bank-level filtering unit (BFU) configured to perform filtering operations on data fetched from one of the multiple sub-arrays to the memory bank (see [0028]: filtering circuit to filter data read from the plurality of memory circuits and transmitted to an external device).
TRAININ discloses the following limitations that are not taught by WON: each memory bank comprising: multiple sub-arrays (see [0074]: a DRAM can include multiple arrays) in which data is stored in horizontal layouts, with each byte present in a same row of the corresponding one of the multiple sub-arrays (see [0114]: table data stored in row and column format). TRAININ discloses a processing-in-memory structure (see [0103]) that allows for query operations to be executed on table data (see [0120]-[0121]). Accelerating data filtering for table data, which includes data stored in rows, avoids bottlenecks and inefficiencies associated with loading data directly from storage (see [0127]). WON already discloses a processing-in-memory structure for filtering data. TRAININ provides additional teachings to add functionality for processing queries on table data. WON already includes the necessary structure to perform this processing and the system of WON would be improved by incorporating the teachings of TRAININ to reduce bottlenecks in data transfer.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify WON to have data stored in rows, as disclosed by TRAININ. One of ordinary skill in the art would have been motivated to make such a modification to allow for query processing on table data to reduce bottlenecks between storage and a host, as taught by TRAININ. WON and TRAININ are analogous/in the same field of endeavor as both references are directed to processing-in-memory architectures to filter data.
2. The bank-level DRAM-PIM filtering architecture according to claim 1, wherein the BFU comprises a reconfigurable comparator block (RCB), which is receptive of the data of the one sub-array at the time (see WON [0030]: filtering logic receives data) and filtering predicates (see WON [0031]: register to store operand for filtering data), and which is configured to generate an output of elements of the data matching the filtering predicates (see WON [0032]: queue to store the filtered data to be output).
3. The bank-level DRAM-PIM filtering architecture according to claim 2, wherein the RCB is supportive of equality checking (see WON [0036]: output data entries that match the SITE, this is equality checking).
4. The bank-level DRAM-PIM filtering architecture according to claim 2, wherein the RCB is supportive of range checking (see WON [0038]-[0039]: greater than and less than).
5. The bank-level DRAM-PIP filtering architecture according to claim 2, wherein the BFU further comprises a scratchpad memory to store the output as a bitmap (see WON [0032]: filtered output data stored in a queue; [0033]-[0034]: count of filtered data stored in a register).
6. The bank-level DRAM-PIP filtering architecture according to The bank-level DRAM-PIP filtering architecture according to wherein the BFU further comprises a multiple filtering predicate loop (see TRAININ [0180]-[0182]: multiple filter values).
8. WON discloses A sub-array-level dynamic random access memory (DRAM) (see [0024]: DRAM) process- in-memory (DRAM-PIM) filtering architecture (see [0024]: memory device may be a processing-in-memory device) to accelerate database online analytical processing (OLAP) queries, comprising: a DRAM chip comprising multiple memory banks (see [0024]: memory circuits composed of memory banks), each memory bank comprising: multiple sub-array pairs, each sub-array having data stored thereon in a vertical layout, with each bit stored in a different row and in a same column of the sub-array (see TRAININ below); and a per-bank global data bus, by which data of one sub-array at a time flows relative to the memory bank (see [0028]: the GIO line allows access to the plurality of memory circuits), each of the multiple sub-array pairs comprising a sub-array-level filtering unit (SFU) comprising a bit-serial comparison circuit configured to perform filtering operations with respect to the associated one of the multiple sub-array pairs (see [0028]: filtering circuit to filter data read from the plurality of memory circuits and transmitted to an external device).
TRAININ discloses the following limitations that are not taught by WON: each memory bank comprising: multiple sub-array pairs (see [0074]: a DRAM can include multiple arrays), each sub-array having data stored thereon in a vertical layout, with each bit stored in a different row and in a same column of the sub-array (see [0114]: table data stored in row and column format). TRAININ discloses a processing-in-memory structure (see [0103]) that allows for query operations to be executed on table data (see [0120]-[0121]). Accelerating data filtering for table data, which includes data stored in rows, avoids bottlenecks and inefficiencies associated with loading data directly from storage (see [0127]). WON already discloses a processing-in-memory structure for filtering data. TRAININ provides additional teachings to add functionality for processing queries on table data. WON already includes the necessary structure to perform this processing and the system of WON would be improved by incorporating the teachings of TRAININ to reduce bottlenecks in data transfer.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify WON to have data stored in rows, as disclosed by TRAININ. One of ordinary skill in the art would have been motivated to make such a modification to allow for query processing on table data to reduce bottlenecks between storage and a host, as taught by TRAININ. WON and TRAININ are analogous/in the same field of endeavor as both references are directed to processing-in-memory architectures to filter data.
16. WON discloses A sub-array-level dynamic random access memory (DRAM) (see [0024]: DRAM) process- in-memory (DRAM-PIM) filtering architecture (see [0024]: memory device may be a processing-in-memory device) to accelerate database online analytical processing (OLAP) queries, comprising: a DRAM chip comprising multiple memory banks (see [0024]: memory circuits composed of memory banks), each memory bank comprising: multiple sub-arrays, each having data stored thereon in a horizontal layout, with each byte present in a same row of the corresponding one of the multiple sub-arrays (see TRAININ below); and a per-bank global data bus, by which data of one sub-array at a time flows at a time relative to the memory bank (see [0028]: the GIO line allows access to the plurality of memory circuits), each of the multiple sub-arrays comprising a sub-array-level filtering unit (SFU) comprising an element-serial bit-parallel comparison circuit configured to perform filtering operations with respect to the associated one of the multiple sub-arrays (see [0028]: filtering circuit to filter data read from the plurality of memory circuits and transmitted to an external device).
TRAININ discloses the following limitations that are not taught by WON: each memory bank comprising: multiple sub-arrays (see [0074]: a DRAM can include multiple arrays), each having data stored thereon in a horizontal layout, with each byte present in a same row of the corresponding one of the multiple sub-arrays (see [0114]: table data stored in row and column format). TRAININ discloses a processing-in-memory structure (see [0103]) that allows for query operations to be executed on table data (see [0120]-[0121]). Accelerating data filtering for table data, which includes data stored in rows, avoids bottlenecks and inefficiencies associated with loading data directly from storage (see [0127]). WON already discloses a processing-in-memory structure for filtering data. TRAININ provides additional teachings to add functionality for processing queries on table data. WON already includes the necessary structure to perform this processing and the system of WON would be improved by incorporating the teachings of TRAININ to reduce bottlenecks in data transfer.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify WON to have data stored in rows, as disclosed by TRAININ. One of ordinary skill in the art would have been motivated to make such a modification to allow for query processing on table data to reduce bottlenecks between storage and a host, as taught by TRAININ. WON and TRAININ are analogous/in the same field of endeavor as both references are directed to processing-in-memory architectures to filter data.
17. The sub-array-level DRAM-PIM filtering architecture according to claim 16, wherein the element-serial bit-parallel comparison circuit comprises a comparison unit (see WON [0036]: comparison of entries with filter condition for SITE).
18. The sub-array-level DRAM-PIM filtering architecture according to claim 17, wherein individual data elements stored in the multiple sub-arrays are accessed sequentially and fed into the comparison unit (see WON [0035]-[0036]: data of multiple entries is fed into the filtering logic, the filtering logic outputs the entries that match the filtering condition).
19. The sub-array-level DRAM-PIM filtering architecture according to claim 17, wherein the element-serial bit-parallel comparison circuit further comprises an instruction buffer configured to convey information as to which sub-array column is to be accessed for an operation and a type of comparison operation to be performed (see WON [0031]: register to store operand for filtering data; [0030]: data is read from the memory and fed into the filtering logic).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over WON (U.S. Patent Application Publication #2024/0257844) and TRAININ (U.S. Patent Application Publication #2023/0214389) as applied to claims 1-6, 8 and 16-19 above, and further in view of FAN (U.S. Patent Application Publication #2023/0297331).
9. The sub-array-level DRAM-PIM filtering architecture according to claim 8 (see WON above), wherein the bit-serial comparison circuit is configured to compare an attribute against a filtering predicate in a bit-serial manner, starting from a most significant bit (MSB) to a least significant bit (LSB) (see FAN below).
FAN discloses the following limitations that are not taught by WON: wherein the bit-serial comparison circuit is configured to compare an attribute against a filtering predicate in a bit-serial manner, starting from a most significant bit (MSB) to a least significant bit (LSB) (see [0057]-[0058]: bit-wise comparison starting with the MSB and ending with the LSB). This hardware structure supports bulk data storage and greatly minimizes the time associated with computing (see [0008]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify WON to perform a bit-serial comparison, as disclosed by FAN. One of ordinary skill in the art would have been motivated to make such a modification to greatly minimize the time and cost of computing, as taught by FAN. WON and FAN are analogous/in the same field of endeavor as both references are directed to processing-in-memory to filter data.
10. The sub-array-level DRAM-PIM filtering architecture according to claim 9, wherein the bit-serial comparison circuit is configured to perform a relational comparison between a block of table entries and a filtering predicate value (see TRAININ [0163]-[0164]: filter value used to filter a data table).
Allowable Subject Matter
Claims 7, 11-15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The state of the art fails to anticipate, or render obvious, “… a memory controller coupled to the DRAM chip and comprising a de-interleaving unit configured to swizzle bytes in each word such that an entirety of each word is stored on the DRAM chip.”
The state of the art fails to anticipate, or render obvious, “… wherein the bit-serial comparison circuit is configured to: reset set bit flip flops and register bit flip-flops to zero, once a mismatch is detected between first and second input bits, a set bit goes to high and latches itself and a current register bit is locked, and after all sequential row activations, final values of each set bit and each register bit determine a comparison output by reference to a truth table.”
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
MISHRA [2025/0307180] discloses a DRAM with a PIM architecture, filtering data stored in the DRAM, transmitting filter conditions to the DRAM and storing the filtering results in a register. [0040]-[0062]
INTERLANDI [2024/03116380] discloses performing query operations using a PIM device. [0093]
YUDANOV [2021/0294608] discloses a PIM device and sending filter conditions to the PIM device to filter data stored in the memory. [0022]-[0027]
“Enabling Relational Database Analytical Processing in bulk-bitwise processing-in-memory” discloses a processing-in-memory modules for performing database queries and returning results to a host computer, the queries result in filtering data as only the data that meets the query is returned, thereby reducing the amount of data that needs to be sent over a bus to the host.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain T Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132
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