DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/10/2025, 07/09/2025 and 03/08/2026 has been placed in record and considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 2 is objected to because of the following informalities:
The limitation “…….; or regulate the voltage of the second gate of the dual-gate transistor when the dual-gate transistor is conducted, to improve a driving capability of the dual-gate transistor, and regulate the voltage of the second gate of the dual-gate transistor when the dual-gate transistor is cut off, to suppress a leakage current of the dual-gate transistor.” is duplicated to the first part of the limitation, accordingly.
Appropriate corrections are required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. - An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 1-20 limitations “output control module, configured to.., a voltage regulation module, configured to..., first voltage regulation unit is configured, second voltage regulation unit is configured, first voltage regulation module, second voltage regulation module, first output control unit configured to, second output control unit configured to, third output control unit configured, and fourth output control unit configured to” has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder “configured to” coupled with functional language “to control, to regulate, and to transmit” reciting sufficient structure to achieve the function.
Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, claim(s) 1-20 has/have been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation: in paragraphs 0086-0098 and figures 7-14.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 11-13, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LU, Jian-jun (CN 115083329A hereinafter Lu).
Referring to claim 1, Lu discloses a gate drive circuit (Fig. 1-10; scanning drive circuit), comprising:
an output control module (Fig. 3; output control module comprises modules 110/120/130/140/150) (Lu-see attachment highlighted section; Specifically, in the first level signal output period, the input control module 110 directly controls the first output module 160 is turned on, and outputs the first level signal. At the same time, the input control module 110 also can directly control the first mutual control module 120 is conducted, the reverse control module 130 transmits the control signal, so that the reverse control module 130 controls the second output module 170 is turned off, so as to ensure the first output module 160 is turned on, the second output module 170 can be reliably cut off, cannot output the second level signal. Therefore, the scanning drive circuit can reliably output the first level signal.);
a first transistor (Fig. 3; M2);
a second transistor (Fig. 3; M1), wherein the output control module (Fig. 3; output control module comprises modules 110/120/130/140/150) is connected to a gate of the first transistor (Fig. 3; M2) and a gate of the second transistor (Fig. 3; M1) (Fig. 1; gates of M2 and M1 are connected to output control module comprises modules 110/120/130/140/150), a first electrode of the first transistor (Fig. 3; M2) is configured to receive a first output signal (Fig. 3; VGL) (Fig. 3; first electrode of first transistor M2 is configured to receive first output signal VGL), a second electrode of the first transistor (Fig. 3; M2) is connected to an output terminal (Fig. 3; Vout) of the gate drive circuit (Fig. 3; second electrode of first transistor M2 is connected to an output terminal Vout), a first electrode of the second transistor (Fig. 3; M1) is configured to receive a second output signal (Fig. 3; VGH) (Fig. 3; first electrode of second transistor M1 is configured to receive second output signal VGH), a second electrode of the second transistor (Fig. 3; M1) is connected to the output terminal (Fig. 3; Vout) of the gate drive circuit (Fig. 3; second electrode of first transistor M1 is connected to an output terminal Vout), the output control module (Fig. 3; output control module comprises modules 110/120/130/140/150) is configured to control the first transistor (Fig. 3; M2) and the second transistor (Fig. 3; M1) to be alternately turned on, to alternately transmit the first output signal and the second output signal to the output terminal of the gate drive circuit (Lu-see attachment highlighted section; Specifically, in the first level signal output period, the input control module 110 directly controls the first output module 160 is turned on, and outputs the first level signal. At the same time, the input control module 110 also can directly control the first mutual control module 120 is conducted, the reverse control module 130 transmits the control signal, so that the reverse control module 130 controls the second output module 170 is turned off, so as to ensure the first output module 160 is turned on, the second output module 170 can be reliably cut off, cannot output the second level signal. Therefore, the scanning drive circuit can reliably output the first level signal.
In the second level signal output period, the first mutual control module 120 is disconnected, the first stabilizing module 140 controls the reverse control module 130 generates a control signal, so that the reverse control module 130 controls the second output module 170 is turned on, and outputs the second level signal. Meanwhile, the second stabilizing module 150 outputs the control signal under the control of the first stabilizing module 140, so that the second stabilizing module 150 controls the first output module 160 is turned off, so as to ensure the first output module 160 is reliably cut off, cannot output the first level signal. Therefore, the scanning drive circuit can reliably output the second level signal.), at least one of the first transistor (Fig. 3; M2) and the second transistor (Fig. 3; M1) is a dual-gate transistor (Fig. 3-6; M1 and M2 are double-gated transistors), and a first gate of the dual-gate transistor is connected to the output control module (Fig. 3; output control module comprises modules 110/120/130/140/150 is connected to the gates of M2 and M1); and
a voltage regulation module (Fig. 3; a voltage regulation is presented but not shown via first and second threshold voltage adjusting signal B1 and B2) connected to a second gate of the dual-gate transistor and configured to regulate a voltage of the second gate of the dual-gate transistor (Lu-see attachment highlighted section; wherein the first output module 160 is further connected to the first threshold voltage adjusting signal B1, the first threshold voltage adjusting signal B1 is opposite to the level of the first level signal; and/or, the second output module 170 is further connected with the second threshold voltage adjusting signal B2, the second threshold voltage adjusting signal B2 and the second level signal level are opposite.).
Referring to claim 2, Lu discloses wherein the voltage regulation module is configured to: regulate the voltage of the second gate of the dual-gate transistor when the dual-gate transistor is conducted, to improve a driving capability of the dual-gate transistor, and regulate the voltage of the second gate of the dual-gate transistor when the dual-gate transistor is cut off, to suppress a leakage current of the dual-gate transistor (Lu-see attachment highlighted section; Aiming at the above problem, the first output module 160 of the solution is further connected to the first threshold voltage adjusting signal B1, can be input by the first output module 160 input first threshold voltage adjusting signal B1 to adjust the threshold voltage of the transistor in the first output module 160, so that the first output module 160 can be reliably conducted under the control of the input control module 110, the first stabilizing module 140 through the second stabilizing module 150 under the control of reliable disconnection. the second output module 170 is further connected to the second threshold voltage adjusting signal B2, and the second output module 170 may be input to the second threshold voltage adjusting signal B2 to adjust the threshold voltage of the transistor in the second output module 170, so that the second output module 170 can be reliably conducted under the control of the first stabilizing module 140 through the reverse control module 130, the input control module 110 through the first mutual control module 120 under the control of reliable disconnection…, In summary, the solution through the first output module 160 is further connected with the first threshold voltage adjusting signal B1, the second output module 170 is further connected with the second threshold voltage adjusting signal B2, which can overcome the problem that the transistor in the existing scanning drive circuit has threshold voltage drift, the transistor in the scanning drive circuit can be reliably conducted or cut off, the output of the driving circuit is more stable, so as to improve the display stability of the display panel.); or regulate the voltage of the second gate of the dual-gate transistor when the dual-gate transistor is conducted, to improve a driving capability of the dual-gate transistor, and regulate the voltage of the second gate of the dual-gate transistor when the dual-gate transistor is cut off, to suppress a leakage current of the dual-gate transistor (Lu-see attachment highlighted section; Aiming at the above problem, the first output module 160 of the solution is further connected to the first threshold voltage adjusting signal B1, can be input by the first output module 160 input first threshold voltage adjusting signal B1 to adjust the threshold voltage of the transistor in the first output module 160, so that the first output module 160 can be reliably conducted under the control of the input control module 110, the first stabilizing module 140 through the second stabilizing module 150 under the control of reliable disconnection. the second output module 170 is further connected to the second threshold voltage adjusting signal B2, and the second output module 170 may be input to the second threshold voltage adjusting signal B2 to adjust the threshold voltage of the transistor in the second output module 170, so that the second output module 170 can be reliably conducted under the control of the first stabilizing module 140 through the reverse control module 130, the input control module 110 through the first mutual control module 120 under the control of reliable disconnection…, In summary, the solution through the first output module 160 is further connected with the first threshold voltage adjusting signal B1, the second output module 170 is further connected with the second threshold voltage adjusting signal B2, which can overcome the problem that the transistor in the existing scanning drive circuit has threshold voltage drift, the transistor in the scanning drive circuit can be reliably conducted or cut off, the output of the driving circuit is more stable, so as to improve the display stability of the display panel.).
Referring to claim 11, Lu discloses wherein when the first transistor is the dual- gate transistor, the voltage regulation module comprises a first voltage regulation module, and the first voltage regulation module is connected to a second gate of the first transistor; and
when the second transistor is the dual-gate transistor, the voltage regulation module comprises a second voltage regulation module, and the second voltage regulation module is connected to a second gate of the second transistor (Lu-see attachment highlighted section; Aiming at the above problem, the first output module 160 of the solution is further connected to the first threshold voltage adjusting signal B1, can be input by the first output module 160 input first threshold voltage adjusting signal B1 to adjust the threshold voltage of the transistor in the first output module 160, so that the first output module 160 can be reliably conducted under the control of the input control module 110, the first stabilizing module 140 through the second stabilizing module 150 under the control of reliable disconnection. the second output module 170 is further connected to the second threshold voltage adjusting signal B2, and the second output module 170 may be input to the second threshold voltage adjusting signal B2 to adjust the threshold voltage of the transistor in the second output module 170, so that the second output module 170 can be reliably conducted under the control of the first stabilizing module 140 through the reverse control module 130, the input control module 110 through the first mutual control module 120 under the control of reliable disconnection. Thus, a first voltage regulation module and a second voltage regulation are present but not shown to allow the input of the adjusting signals B1 and B2 to the first module 160 and second module 170.).
Referring to claim 12, Lu discloses wherein the first transistor and the second transistor are both dual-gate transistors (Fig. 3; Transistors M1 and M2 are dual-gate transistors); and
the second gate of the first transistor is connected to the first voltage regulation module, and the second gate of the second transistor is connected to the second voltage regulation module (Fig. 3; second gate of transistors M1 and M2 are connected to the first and second threshold voltage adjusting signal B1 and B2).
Referring to claim 13, Lu discloses wherein the first transistor and the second transistor are both dual-gate transistors (Fig. 3; Transistors M1 and M2 are dual-gate transistors);
a second gate of one of the first transistor and the second transistor is connected to a first level signal line, and a second gate of the other of the first transistor and the second transistor is connected to the voltage regulation module (Fig. 3; second gates of Transistors M1 and M2 are connected to the voltage regulator module is presented but not shown via first and second threshold voltage adjusting signal B1 and B2); or
a first gate and a second gate of one of the first transistor and the second transistor are connected, and a second gate of the other of the first transistor and the second transistor is connected to the voltage regulation module.
Referring to claim 20, Lu discloses a display panel (Lu-see attachment highlighted section; The embodiment of the invention claims a scanning drive circuit and a display panel, so as to improve the reliability of the output of the scanning drive circuit and improve the display stability of the display panel.), comprising:
a plurality of gate drive circuits (Fig. 22; plurality of scan drive circuits 10), comprising:
an output control module (Fig. 3; output control module comprises modules
110/120/130/140/150) (Lu-see attachment highlighted section; Specifically, in the first
level signal output period, the input control module 110 directly controls the first output
module 160 is turned on, and outputs the first level signal. At the same time, the input
control module 110 also can directly control the first mutual control module 120 is
conducted, the reverse control module 130 transmits the control signal, so that the
reverse control module 130 controls the second output module 170 is turned off, so as to
ensure the first output module 160 is turned on, the second output module 170 can be
reliably cut off, cannot output the second level signal. Therefore, the scanning drive
circuit can reliably output the first level signal.);
a first transistor (Fig. 3; M2);
a second transistor (Fig. 3; M1), wherein the output control module (Fig. 3; output control module comprises modules 110/120/130/140/150) is connected to a gate of the first transistor (Fig. 3; M2) and a gate of the second transistor (Fig. 3; M1) (Fig. 1; gates of M2 and M1 are connected to output control module comprises modules 110/120/130/140/150), a first electrode of the first transistor (Fig. 3; M2) is configured to receive a first output signal (Fig. 3; VGL) (Fig. 3; first electrode of first transistor M2 is configured to receive first output signal VGL), a second electrode of the first transistor (Fig. 3; M2) is connected to an output terminal (Fig. 3; Vout) of the plurality of gate drive circuits (Fig. 3; second electrode of first transistor M2 is connected to an output terminal Vout), a first electrode of the second transistor (Fig. 3; M1) is configured to receive a second output signal (Fig. 3; VGH) (Fig. 3; first electrode of second transistor M1 is configured to receive second output signal VGH), a second electrode of the second transistor (Fig. 3; M1) is connected to the output terminal (Fig. 3; Vout) of the gate plurality of drive circuits (Fig. 3; second electrode of first transistor M1 is connected to an output terminal Vout), the output control module (Fig. 3; output control module comprises modules 110/120/130/140/150) is configured to control the first transistor (Fig. 3; M2) and the second transistor (Fig. 3; M1) to be alternately turned on, to alternately transmit the first output signal and the second output signal to the output terminal of the plurality of gate drive circuits (Lu-see attachment highlighted section; Specifically, in the first level signal output period, the input control module 110 directly controls the first output module 160 is turned on, and outputs the first level signal. At the same time, the input control module 110 also can directly control the first mutual control module 120 is conducted, the reverse control module 130 transmits the control signal, so that the reverse control module 130 controls the second output module 170 is turned off, so as to ensure the first output module 160 is turned on, the second output module 170 can be reliably cut off, cannot output the second level signal. Therefore, the scanning drive circuit can reliably output the first level signal.
In the second level signal output period, the first mutual control module 120 is
disconnected, the first stabilizing module 140 controls the reverse control module 130
generates a control signal, so that the reverse control module 130 controls the second
output module 170 is turned on, and outputs the second level signal. Meanwhile, the
second stabilizing module 150 outputs the control signal under the control of the first
stabilizing module 140, so that the second stabilizing module 150 controls the first
output module 160 is turned off, so as to ensure the first output module 160 is reliably
cut off, cannot output the first level signal. Therefore, the scanning drive circuit can
reliably output the second level signal.), at least one of the first transistor (Fig. 3; M2) and the second transistor (Fig. 3; M1) is a dual- gate transistor (Fig. 3-6; M1 and M2 are double-gated transistors), and a first gate of the dual-gate transistor is connected to the output control module (Fig. 3; output control module comprises modules 110/120/130/140/150 is connected to the gates of M2 and M1); and
a voltage regulation module (Fig. 3; a voltage regulation is presented but not shown via first and second threshold voltage adjusting signal B1 and B2) connected to a second gate of the dual-gate transistor and configured to regulate a voltage of the second gate of the dual-gate transistor (Lu-see attachment highlighted section; wherein the first output module 160 is further connected to the first threshold voltage adjusting signal B1, the first threshold voltage adjusting signal B1 is opposite to the level of the first level signal; and/or, the second output module 170 is further connected with the second threshold voltage adjusting signal B2, the second threshold voltage adjusting signal B2 and the second level signal level are opposite.), wherein the plurality of gate drive circuits are connected in a cascading manner (Lu-see attachment highlighted section; FIG. 22 is a schematic diagram of a cascade of a scan driving circuit provided by an embodiment of the present invention. Referring to FIG. 22, the display panel includes an N + 1 level scan drive circuit 10, and the signal output by the first output end Vout (1) of the first level scan drive circuit 10 is used as the input signal EIN of the second level scan drive circuit 10.... The signal output by the first output end Vout (N-1) of the Nth level scanning drive circuit 10 is used as the input signal EIN of the Nth level scanning drive circuit 10. so as to realize the shift output of the signal.).
Claim Objections
Claims 3-10 and 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 3, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein a control terminal of the voltage regulation module is configured to receive a first control signal, a first terminal of the voltage regulation module is configured to receive a first level signal, and a second terminal of the voltage regulation module is connected to the second gate of the dual-gate transistor; the voltage regulation module is configured to transmit the first level signal to the second gate of the dual-gate transistor in response to the first control signal when the dual-gate transistor is cut off, to suppress a leakage current of the dual-gate transistor; and
the voltage regulation module comprises a third transistor, wherein a gate of the third transistor is configured to receive the first control signal, a first electrode of the third transistor is configured to receive the first level signal, and a second electrode of the third transistor is connected to the second gate of the dual-gate transistor”.
Referring to claims 10 and 19 are objected upon dependent on the claim 3.
Referring to claim 4, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein a control terminal of the voltage regulation module is configured to receive a second control signal, a first terminal of the voltage regulation module is configured to receive a preset signal, and a second terminal of the voltage regulation module is connected to the second gate of the dual-gate transistor; the voltage regulation module is configured to regulate, through the preset signal, the voltage of the second gate of the dual-gate transistor in response to the second control signal when the dual-gate transistor is conducted, to improve a driving capability of the dual-gate transistor; and
the voltage regulation module comprises a fourth transistor, wherein a gate of the fourth transistor is configured to receive the second control signal, a first electrode of the fourth transistor is configured to receive the preset signal, and the fourth transistor is configured to transmit a signal related to the preset signal to the second gate of the dual- gate transistor in response to the second control signal”.
Referring to claims 5-6 are objected upon dependent on the claim 4.
Referring to claim 7, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the voltage regulation module comprises:
a first voltage regulation unit, wherein a control terminal of the first voltage regulation unit is configured to receive a first control signal, a first terminal of the first voltage regulation unit is configured to receive a first level signal, a second terminal of the first voltage regulation unit is connected to the second gate of the dual-gate transistor, and the first voltage regulation unit is configured to transmit the first level signal to the second gate of the dual-gate transistor in response to the first control signal when the dual-gate transistor is cut off; and
a second voltage regulation unit, wherein a control terminal of the second voltage regulation unit is configured to receive a second control signal, a first terminal of the second voltage regulation unit is configured to receive a preset signal, a second terminal of the second voltage regulation unit is connected to the second gate of the dual-gate transistor, and the second voltage regulation unit is configured to regulate, through the preset signal, the voltage of the second gate of the dual-gate transistor in response to the second control signal when the dual-gate transistor is conducted; and
a level of the first level signal comprises a first level, a level of the preset signal comprises a second level, one of the first level and the second level is a preset high level, and the other of the first level and the second level is a preset low level”.
Referring to claims 8-9 are objected upon dependent on the claim 7.
Referring to claim 14, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the output control module comprises: an input unit connected to a first node, a second node, and an input terminal of the gate drive circuit and configured to control a signal at the first node and a signal at the second node based on a first clock signal, a second level signal, and a signal at the input terminal of the gate drive circuit;
a first output control unit connected to the first node and the second node and configured to control the signal at the first node based on the signal at the second node and the first clock signal; and
a second output control unit connected to the first node and the second node and configured to control the signal at the second node based on the signal at the first node, a second clock signal, and a third level signal, wherein the first node is connected to the gate of the first transistor, and the signal at the second node is transmitted to the gate of the second transistor; and
the third level signal is reused as the first output signal, and the second clock signal is reused as the second output signal”.
Referring to claims 15-16 are objected upon dependent on the claim 14.
Referring to claim 17, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the output control module comprises: an input unit connected to a first node, a second node, and an input terminal of the gate drive circuit and configured to control a signal at the first node and a signal at the second node based on a first clock signal, a third level signal, and a signal at the input terminal of the gate drive circuit;
a first output control unit connected to a third node, the first node, and the second node and configured to control a signal at the third node based on a second clock signal, the signal at the first node, the signal at the second node, and the third level signal, wherein the third node is connected to the gate of the first transistor; and
a second output control unit connected to a fourth node and the third node and configured to control a signal at the fourth node based on the signal at the third node, the signal at the fourth node, the third level signal, and the second clock signal, wherein the fourth node is connected to the gate of the second transistor, and the signal at the second node is transmitted to the gate of the second transistor; and
the third level signal is reused as the first output signal, and a second level signal is reused as the second output signal”.
Referring to claim 18, the following is a statement of reasons for the indication of allowable subject matter: the prior art fail to suggest limitation “wherein the output control module comprises: an input unit connected to a first node, a second node, and an input terminal of the gate drive circuit and configured to control a signal at the first node and a signal at the second node based on a first clock signal, a second level signal, and a signal at the input terminal of the gate drive circuit;
a first output control unit connected to the first node and the second node and configured to control the signal at the first node based on the signal at the second node and the first clock signal;
a second output control unit connected to a third node and a fourth node and configured to control a signal at the fourth node based on a signal at the third node and a second clock signal, wherein the signal at the first node is transmitted to the third node, and the signal at the fourth node is transmitted to the gate of the first transistor;
a third output control unit connected to a fifth node and a sixth node and configured to control a signal at the sixth node based on a signal at the fifth node, the signal at the sixth node, a third level signal, and the second clock signal, wherein the signal at the first node is transmitted to the fifth node, the signal at the second node is transmitted to the sixth node, and the sixth node is connected to the gate of the second transistor; and
a fourth output control unit connected to a seventh node and the second node and configured to control a signal at the seventh node based on the signal at the second node and the third level signal, wherein the signal at the fourth node is transmitted to the seventh node, and the seventh node is connected to the gate of the first transistor; and
wherein the third level signal is reused as the first output signal, and the second level signal is reused as the second output signal”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shang et al. (US 2021/0398478) disclose a shift register unit and method for driving the same, gate driving circuit and display device.
Xue et al. (US 2021/0335265) disclose a GOA circuit and array substrate.
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