Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-25 are pending.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Information Disclosure Statement
The references cited in the information disclosure statement (IDS) submitted on November 04, 2025 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The title is meant to have an “informative value in indexing, classifying, searching”. See MPEP606.01.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-8, 10-12, 13, 14, 17-20, 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Bert et. al. U.S. Patent Pub No. 2022/0276789 (hereinafter Bert) in view of Sela et. al. US Patent No. Pub. 2024/0143509 (hereinafter Sela).
Regarding Claim 1, Bert teaches a memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: receive a plurality of write commands associated with respective logical block addresses that are in a sequential order, wherein the respective logical block addresses are associated with a zone of the memory system that comprises a plurality of sequential logical block addresses (Fig.1B, 2,4,5; Para13-15, 17-18 "When data having locality are written sequentially, the data are written to groups of memory cells that are also referred to as zones for simplicity, where each zone can store multiple physical blocks of data." Para21-22); write first data to a first physical block address of the memory system in response to receiving the plurality of write commands, wherein the first data is associated with a first logical block address of the respective logical block addresses (Fig.5-7; Para58-62 "the processing logic can allocate the one or more sequentially written data objects from the compound data object to the one or more groups of memory cells of the plurality of memory devices");
determine whether a second logical block address associated with second data is sequential relative to a write pointer associated with the zone, wherein the write pointer indicates a position within the plurality of sequential logical block addresses of the zone for writing data (Fig.2-5, 7, Para13-15, 41-42 "A write pointer (WP) to the zones of the memory device 130 can be stored in the cache 123."Para58-62, 70-75) and write the second data to a second physical block address of the memory system that is sequential to the first physical block address and on a value of a bitmap corresponding to the second logical block address (Fig.2-5, Para 41-42 "The zones in a ZNS can be groups of blocks that are sequentially numbered LBAs that are mapped to sequentially ordered physical addresses within the physical address Space" "the zone mapping data structure 158 can comprise a logical-to-physical (L2P) mapping data structure to map the logical block numbers ( or addresses) of LBA space to memory chunks that are allocated to zones or groups of memory" Para51-53, 58-62, 70-75).
However, Bert fails to teach but Sela teaches write the second data to a second physical block address of the memory system that is sequential to the first physical block address in response to determining that the second logical block address is non-sequential relative to the write pointer and on a value of a bitmap corresponding to the second logical block address(Fig.4, 5; Para37-39, 40-43 "When an out-of-order command arrives (e.g., a write command for LBAX+l , where LBAX was expected), the controller 102 in the data storage device 100 can write the data for LBA X+I in the temporary buffer").
Bert and Sela are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Bert, and incorporating the writing method, as taught by Sela.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by Sela (Para15-17).
Regarding claim 2, the combination of Bert and Sela teaches all the limitations of the base claims as outlined above.
Further, Bert teaches wherein the processing circuitry is further configured to cause the memory system to: increment a value of a counter in response to receiving the plurality of write commands; and determine whether the value of the counter satisfies a threshold value corresponding to the plurality of sequential logical block addresses of the zone, wherein writing the first data to the first physical block address of the memory system is in response to determining that the value of the counter satisfies the threshold value (Fig.2,5,6, Para13-15, 42-43 "The storage driver 133 can update the zone mapping data structure 158 to include which data set(s) are assigned to each zone, and to increment the data set counter." Para49,56-57).
Regarding claim 5, the combination of Bert and Sela teaches all the limitations of the base claims as outlined above.
Further, Bert teaches wherein the processing circuitry is further configured to cause the memory system to: determine the value of the bitmap corresponding to the second logical block address in response to determining that the second logical block address is non-sequential relative to the write pointer, wherein writing the second data to the second physical block address is in accordance with the value of the bitmap corresponding to the second logical block address comprising a first value (Fig.2-5, Para 41-42 "The zones in a ZNS can be groups of blocks that are sequentially numbered LBAs that are mapped to sequentially ordered physical addresses within the physical address Space" "the zone mapping data structure 158 can comprise a logical-to-physical (L2P) mapping data structure to map the logical block numbers ( or addresses) of LBA space to memory chunks that are allocated to zones or groups of memory" Para51-53, 58-62, 70-75).
Regarding claim 6, the combination of Bert and Sela teaches all the limitations of the base claims as outlined above.
Further, Bert teaches wherein the processing circuitry is further configured to cause the memory system to: reset the value of the bitmap corresponding to the second logical block address in response to writing the second data to the second physical block address (Fig.2-5, Para 41-42, 45, 63-65).
Regarding claim 7, the combination of Bert and Sela teaches all the limitations of the base claims as outlined above.
Further, Bert teaches wherein the processing circuitry is further configured to cause the memory system to: determine that a fourth logical block address associated with fourth data is non-sequential relative to the write pointer associated with the zone; determine that the value of the bitmap corresponding to the fourth logical block address comprises a second value; and refrain from writing the fourth data to a fourth physical block address of the memory system in accordance with the value of the bitmap corresponding to the fourth logical block address comprising the second value(Fig.2-5, Para 41-42, 45, 63-65).
Regarding claim 8, the combination of Bert and Sela teaches all the limitations of the base claims as outlined above.
Further, Bert teaches wherein the processing circuitry is further configured to cause the memory system to: receive a third plurality of write commands associated with respective logical block addresses in a sequential order, wherein the respective logical block addresses are associated with a second zone of the memory system that comprises a plurality of sequential logical block addresses; open the second zone of the memory system in response to receiving the third plurality of write commands; and allocate a second bitmap to the second zone in response to opening the second zone(Fig.2-5, Para 41-42,51-53, 58-62, 70-75).
Regarding claim 10, the combination of Bert and Sela teaches all the limitations of the base claims as outlined above.
Further, Bert teaches wherein the processing circuitry is further configured to cause the memory system to: set a value of the bitmap corresponding to the second logical block address to a first value in accordance with the second logical block address being non-sequential relative to the write pointer(Fig.2-5, Para 41-42, 45, 63-65).
Regarding claim 11, the combination of Bert and Sela teaches all the limitations of the base claims as outlined above.
Further, Bert teaches wherein the processing circuitry is further configured to cause the memory system to: increment the write pointer associated with the zone in response to writing the first data to the first physical block address of the memory system(Fig.2,5,6, Para13-15, 42-43 "The storage driver 133 can update the zone mapping data structure 158 to include which data set(s) are assigned to each zone, and to increment the data set counter." Para49,56-57).
Regarding claim 12, the combination of Bert and Sela teaches all the limitations of the base claims as outlined above.
Further, Sela teaches wherein the first logical block address and the second logical block address are non-sequential logical block addresses(Fig.4, 5; Para37-39, 40-43).
Regarding claims 13, 14, 17-20, 22-25, the combination of Bert and Sela teaches these claims according to the reasoning set forth in claim 1. 2, 5-8, 10-12.
Allowable Subject Matter
Claims 3-4, 9, 15-16, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, including the reference(s) cited below, neither anticipates, nor renders obvious the recited combination as a whole; including at least the limitations of : “wherein the processing circuitry is further configured to cause the memory system to: receive a second plurality of write commands associated with respective logical block addresses in a sequential order; increment the value of a counter in response to receiving the second plurality of write commands; and refrain from writing third data associated with a third logical block address to a third physical block address of the memory system in response to determining that the value of the counter fails to satisfy the threshold value.”
Conclusion
The prior art made of record , listed on form PTO-892, and not relied upon, if any, is considered pertinent to applicant's disclosure.
Jain US20190114255 teaches handling unaligned commands.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135
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