Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1, 11, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KE (US 20230215314 A1).
Regarding claim 1, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses a display substrate,
comprising K pixel rows, wherein: K is a positive integer greater than 1 (e.g., Figs. 3, 14, and 20; a plurality of pixel rows);
at least one pixel row of the K pixel rows comprises an initial signal line (e.g., Fig. 6; initial signal line Vref, Vini, or V0), a scan signal line (e.g., Fig. 6; scan signal line S1, S2, S3, S4, or SV), and a plurality of sub-pixels (e.g., Figs. 3, 14, and 20; a plurality of sub-pixels each comprising a pixel circuit 10 and a light-emitting element 20; [0037]) disposed sequentially along an extension direction of the initial signal line (initial signal line Vref, Vini, or V0) and the scan signal line (scan signal line S1, S2, S3, S4, or SV);
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Annotated version of KE’s Fig. 6
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Annotated version of KE’s Fig. 4
the initial signal line comprises a third initial signal line (initial signal line V0), the scan signal line comprises a second scan signal line (scan signal line SV), and at least one sub-pixel (e.g., Fig. 6; sub-pixel) of the plurality of sub-pixels comprises a pixel drive circuit (pixel driving circuit 10), and the pixel drive circuit (pixel driving circuit 10) comprises at least a storage capacitor (storage capacitor C1), a second transistor (transistor T6), a third transistor as a drive transistor (driving transistor T1) and an eighth transistor as an initialization transistor (initialization transistor T4); and
in a same sub-pixel, a first plate (electrode C11) of the storage capacitor (storage capacitor C1) is connected to a first electrode (electrode E1) of the second transistor (transistor T6) and a control electrode (gate electrode G) of the driving transistor (driving transistor T1), and a second electrode (electrode E2) of the second transistor (transistor T6) is connected to a first electrode (electrode D) of the driving transistor (driving transistor T1);
in the at least one pixel row, the eighth transistor (transistor T4) is connected with the third initial signal line (initial signal line V0), the second scan signal line (scan signal line SV), and a second electrode (electrode S) of the drive transistor (driving transistor T1), and is configured to supply an initial signal (initial voltage signal V0) of the third initial signal line (initial signal line V0) to the second electrode (electrode S) of the drive transistor (driving transistor T1) under control of the second scan signal line (scan signal line SV).
Regarding claim 11, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses the display substrate according to claim 1, wherein: the pixel driving circuit further includes a first power supply line (power supply line PVDD), a first transistor (transistor T2), and a fourth transistor (transistor T5); and in the same sub-pixel, a second electrode of the fourth transistor (transistor T5) and a second electrode of the eighth transistor (transistor T4) are connected to the second electrode (electrode S) of the driving transistor (driving transistor T1), a second electrode of the first transistor (transistor T2) is connected to the control electrode (gate electrode G) of the driving transistor (driving transistor T1), a first electrode (electrode E1) of the second transistor (transistor T6), and the first plate (electrode C11) of the storage capacitor (storage capacitor C1), and the first power line (power voltage line PVDD) is connected to a second plate (electrode C12) of the storage capacitor (storage capacitor C1).
Regarding claim 19, KE discloses a display device (Figs. 2-3 and Fig. 4 or Fig. 6; display device), comprising the display substrate according to claim 1.
Regarding claim 20, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses a working method of a display substrate, wherein:
the display substrate comprises K pixel rows and K is a positive integer greater than 1 (e.g., Figs. 3, 14, and 20; a plurality of pixel rows);
at least one pixel row comprises an initial signal line (e.g., Fig. 6; initial signal line Vref, Vini, or V0), a scan signal line (e.g., Fig. 6; scan signal line S1, S2, S3, S4, or SV), and a plurality of sub-pixels (e.g., Figs. 3, 14, and 20; a plurality of sub-pixels each comprising a pixel circuit 10 and a light-emitting element 20; [0037]) disposed sequentially along an extension direction of the initial signal line (initial signal line Vref, Vini, or V0) and the scan signal line (scan signal line S1, S2, S3, S4, or SV);
the initial signal line comprises a third initial signal line (initial signal line V0), the scan signal line comprises a second scan signal line (scan signal line SV), and at least one sub-pixel (e.g., Fig. 6; sub-pixel) comprises a pixel drive circuit (pixel driving circuit 10), the pixel drive circuit (pixel driving circuit 10) at least comprises a storage capacitor (storage capacitor C1), a second transistor (transistor T6), a third transistor as a drive transistor (driving transistor T1) and an eighth transistor as an initialization transistor (initialization transistor T4);
in a same sub-pixel, a first plate (electrode C11) of the storage capacitor (storage capacitor C1) is connected to a first electrode (electrode E1) of the second transistor (transistor T6) and a control electrode (gate electrode G) of the driving transistor (driving transistor T1), and a second electrode (electrode E2) of the second transistor (transistor T6) is connected to a first electrode (electrode D) of the driving transistor (driving transistor T1);
in at least a pixel row, the eighth transistor (transistor T4) is connected with the third initial signal line (initial signal line V0), the second scan signal line (scan signal line SV), and a second electrode (electrode S) of the drive transistor (driving transistor T1),
the working method comprising: providing, by the eighth transistor (transistor T4), an initial signal (initial voltage signal V0) of the third initial signal line (initial signal line V0) to a second electrode (electrode S) of the drive transistor (driving transistor T1) under control of the second scan signal line (scan signal line SV).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 2 is rejected under 35 U.S.C. 103 as unpatentable over KE (US 20230215314 A1) in view of BANG (US 20200133040 A1).
Regarding claim 2, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses the display substrate according to claim 1, wherein third initial signal lines in two adjacent pixel rows provide different initial signals (e.g., Figs. 3, 14, and 20), but does not disclose sub-pixels located in a same pixel row emit light of a same color, and sub-pixels located in two adjacent pixel rows emit light of different colors. However, BANG (e.g., Fig. 22) discloses a display device, wherein sub-pixels located in a same pixel row emit light of a same color (e.g., Figs. 21 and 23; green color), and sub-pixels located in two adjacent pixel rows emit light of different colors (e.g., Figs. 21 and 23; red and blue colors). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from BANG to the display device of KE. The combination/motivation would be to provide a full-color display device with a RGB sub-pixel arrangement.
6. Claims 3-9 are rejected under 35 U.S.C. 103 as unpatentable over KE (US 20230215314 A1) in view of LI (US 20210134917 A1).
Regarding claim 3, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses the display substrate according to claim 1, wherein: the display substrate further comprises a plurality of light emitting elements (light emitting elements 20) corresponding to a plurality of pixel drive circuits (pixel driving circuits 10), a first scan signal line (scan signal line S3), a third scan signal line (scan signal line S2), a fourth scan signal line (scan signal line S1), a first initial signal line (initial signal line Vref), a second initial signal line (initial signal line Vini), a first power line (power voltage line PVDD), a light emitting control line (light emitting control line EM), and a data signal line (data line Vdata); the pixel drive circuits (pixel driving circuits 10) are configured to drive the light emitting elements (light emitting elements 20) to emit light, and the pixel drive circuit (pixel driving circuit 10) comprises a first reset sub-circuit, a second reset sub-circuit, a third reset sub-circuit, a write-in sub-circuit, a compensation sub-circuit, a drive sub-circuit and a light emitting sub-circuit;
the first reset sub-circuit (transistor circuit T2) is respectively connected with the first initial signal line (initial signal line Vref), the second node (node N1) and the first scan signal line (scan signal line S3), and is configured to write an initial signal (initial signal Vref) of the first initial signal line into the second node (node N1) under control of the first scan signal line (scan signal line S3);
the second reset sub-circuit (transistor circuit T3) is respectively connected with the second initial signal line (initial signal line Vini), a scan signal line (scan signal line S4) and a first electrode (anode) of a light emitting element (light emitting elements 20), and is configured to write an initial signal (initial signal Vini) of the second initial signal line into the first electrode (anode) of the light emitting element (light emitting elements 20) under control of the scan signal line (scan signal line S4);
the third reset sub-circuit (transistor circuit T4) is respectively connected with the third initial signal line (initial signal line V0), the third node (node N2) and the second scan signal line (scan signal line SV), and is configured to write an initial signal (initial signal V0) of the third initial signal line into the third node (node N2) under control of the second scan signal line (scan signal line SV);
the write-in sub-circuit (transistor circuit T5) is respectively connected with the fourth scan signal line (scan signal line S1), the data signal line (data line Vdata) and the third node (node N2), and is configured to write a data signal (data signal Vdata) of the data signal line to the third node (node N2) under control of the fourth scan signal line (scan signal line S1);
the compensation sub-circuit (transistor circuit T6) is respectively connected with the first power line (power voltage line PVDD), the third scan signal line (scan signal line S2), the first node (node N3) and the second node (node N1), and is configured to provide a signal of the first node (node N3) to the second node (node N1) under control of the third scan signal line (scan signal line S2) until a signal of the second node (node N1) meets a threshold condition;
the drive sub-circuit (transistor circuit T1) is electrically connected with the first node (node N3), the second node (node N1) and the third node (node N2) respectively, and is configured to provide a drive current to the third node (node N2) under control of the first node (node N3) and the second node (node N1); and
the light emitting sub-circuit (transistor circuit T7/T8) is respectively connected with the first power line (power voltage line PVDD), the first node (node N3), the third node (node N2), the light emitting control line (light emitting control line EM) and the first electrode (anode) of the light emitting element (light emitting element 20), and is configured to write a signal of the first power line (power voltage line PVDD) into the first node (node N3) and a signal of the third node (node N2) into the first electrode (anode) of the light emitting element (light emitting element 20) under control of the light emitting control line (light emitting control line EM).
KE discloses the second reset sub-circuit (transistor circuit T3) is respectively connected with a scan signal line (scan signal line S4) and is configured to write an initial signal (initial signal Vini) of the second initial signal line into the first electrode (anode) of the light emitting element (light emitting elements 20) under control of the scan signal line (scan signal line S4), but does not disclose the scan signal line is same as the second scan signal line. However, LI (Figs. 19-20) discloses an eighth transistor (transistor M6) is connected with the third initial signal line (initial signal line DV), the second scan signal line (scan signal line S3), and a second electrode (electrode S) of the drive transistor (driving transistor Tm), and is configured to supply an initial signal (initial voltage signal DV) of the third initial signal line (initial signal line DV) to the second electrode (electrode S) of the drive transistor (driving transistor Tm) under control of the second scan signal line (scan signal line S3); and the second reset sub-circuit (transistor circuit M5) is respectively connected with the second initial signal line (initial signal line Vref), the second scan signal line (scan signal line S3) and a first electrode (anode) of a light emitting element (light emitting elements OL), and is configured to write an initial signal (initial signal Vref) of the second initial signal line into the first electrode (anode) of the light emitting element (light emitting elements OL) under control of the second scan signal line (scan signal line S3). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from LI to the display device of KE. The combination/motivation would be to provide an alternative signal control of a pixel driving circuit.
Regarding claim 4, KE in view of LI discloses the display substrate according to claim 1, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses wherein: the first reset sub-circuit comprises a first transistor (transistor circuit T2), the second reset sub-circuit comprises a seventh the eighth transistor (transistor circuit T3), and the third reset sub-circuit comprises the eighth transistor (transistor circuit T4); a control electrode of the first transistor is connected with the first scan signal line, a first electrode of the first transistor is connected with the first initial signal line, and a second electrode of the first transistor is connected with the second node (Fig. 6; transistor circuit T2); a control electrode of the eighth transistor is connected with the second scan signal line, a first electrode of the eighth transistor is connected with the third initial signal line, and a second electrode of the eighth transistor is connected with the third node (Fig. 6; transistor circuit T4); and a control electrode of the seventh transistor is connected with the second scan signal line, a first electrode of the seventh transistor is connected with the second initial signal line, and a second electrode of the seventh transistor is connected with the first electrode of the light emitting element (Fig. 6; transistor circuit T3).
Regarding claim 5, KE in view of LI discloses the display substrate according to claim 3, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses wherein: the write-in sub-circuit comprises a fourth transistor (transistor circuit T5); and a control electrode of the fourth transistor is connected with the fourth scan signal line (scan signal line S1), a first electrode of the fourth transistor is connected with the data signal line (data signal line Vdata), and a second electrode of the fourth transistor is connected with the third node (node N2).
Regarding claim 6, KE in view of LI discloses the display substrate according to claim 3, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses wherein: the compensation sub-circuit comprises the second transistor and the storage capacitor (transistor T6 and capacitor C1); a control electrode of the second transistor is connected with the third scan signal line (scan signal line S2), a first electrode of the second transistor is connected with the second node (node N1), and a second electrode of the second transistor is connected with the first node (node N3); and a first electrode plate of the storage capacitor is connected with the second node (node N1) and a second electrode plate of the storage capacitor is connected with the first power line (power line PVDD).
Regarding claim 7, KE in view of LI discloses the display substrate according to claim 3, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses wherein: the drive sub-circuit comprises the third transistor (transistor circuit T1); and a control electrode of the third transistor is connected with the second node (node N1), a first electrode of the third transistor is connected with the first node (node N1), and a second electrode of the third transistor is connected with the third node (node N2).
Regarding claim 8, KE in view of LI discloses the display substrate according to claim 3, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses wherein: the light emitting sub-circuit comprises a fifth transistor and a sixth transistor (transistors T7 and T8); a control electrode of the fifth transistor is connected with the light emitting control line (light emitting control line EM), a first electrode of the fifth transistor is connected with the first power line (power line PVDD), and a second electrode of the fifth transistor is connected with the first node (node N3); and a control electrode of the sixth transistor is connected with the light emitting control line (light emitting control line EM), a first electrode of the sixth transistor is connected with the third node (node N3), and a second electrode of the sixth transistor is connected with the first electrode (anode) of the light emitting element.
Regarding claim 9, KE in view of LI discloses the display substrate according to claim 3, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses wherein:
the first reset sub-circuit comprises a first transistor (transistor circuit T2), the second reset sub-circuit comprises the seventh transistor (transistor circuit T3), the third reset sub-circuit comprises the eighth transistor (transistor circuit T4), the write-in sub-circuit comprises a fourth transistor (transistor circuit T5), the compensation sub-circuit comprises the second transistor and the storage capacitor (transistor circuit T5 and capacitor C1), the drive sub-circuit comprises the third transistor (transistor circuit T1), and the light emitting sub-circuit comprises a fifth transistor and a sixth transistor (transistor circuit T7/T8); a control electrode of the first transistor is connected with the first scan signal line, a first electrode of the first transistor is connected with the first initial signal line, and a second electrode of the first transistor is connected with the second node (Fig. 6; transistor circuit T2 and connection); a control electrode of the second transistor is connected with a third scan signal line, a first electrode of the second transistor is connected with the second node, and a second electrode of the second transistor is connected with the first node (Fig. 6; transistor circuit T5 and connection); a control electrode of the third transistor is connected with the second node, a first electrode of the third transistor is connected with the first node, and a second electrode of the third transistor is connected with the third node (Fig. 6; transistor circuit T4 and connection); a control electrode of the fourth transistor is connected with the fourth scan signal line, a first electrode of the fourth transistor is connected with the data signal line, and a second electrode of the fourth transistor is connected with the third node (Fig. 6; transistor circuit T5 and connection); a control electrode of the fifth transistor is connected with the light emitting control tine, a first electrode of the fifth transistor is connected with the first power line, and a second electrode of the fifth transistor is connected with the first node (Fig. 6; transistor circuit T7 and connection); a control electrode of the sixth transistor is connected with the light emitting control line, a first electrode of the sixth transistor is connected with the third node, and a second electrode of the sixth transistor is connected with the first electrode of the light emitting element (Fig. 6; transistor circuit T8 and connection); a control electrode of the seventh transistor is connected with the second scan signal line, a first electrode of the seventh transistor is connected with the second initial signal line, and a second electrode of the seventh transistor is connected with the first electrode of the light emitting element (Fig. 6; transistor circuit T3 and connection); a control electrode of the eighth transistor is connected with the second scan signal line, a first electrode of the eighth transistor is connected with the third initial signal line, and a second electrode of the eighth transistor is connected with the third node (Fig. 6; transistor circuit T4 and connection); and a first electrode plate of the storage capacitor is connected with the second node and a second electrode plate of the storage capacitor is connected with the first power line (Fig. 6; storage capacitor C1 and connection).
7. Claim 10 is rejected under 35 U.S.C. 103 as unpatentable over KE (US 20230215314 A1) in view of LI (US 20210134917 A1) and further in view of XU (US 20230076760 A1).
Regarding claim 10, KE in view of LI discloses the display substrate according to claim 9, KE (Figs. 2-3 and Fig. 4 or Fig. 6) discloses wherein the first transistor and the second transistor (transistors T2 and T6) are N-type transistors and the third to eighth transistors (transistors T1, T3-T5, and T7-T8) are P-type transistors. It is well known in the field that N-type transistors are oxide transistors and P-type transistors are low temperature poly-crystalline silicon transistors. The examiner further cites XU as a reference. XU (e.g., Figs. 1-2 and 10) discloses a pixel driving circuit similar to that disclosed by KE and LI, wherein N-type transistor T2 is oxide transistor and P-type transistors (T0-T1 and T3-T6) are low temperature poly-crystalline silicon transistors. Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from XU to the display device of KE in view of LI. The combination/motivation would be to reduce current leakage and improve respond speed of a pixel driving circuit.
Allowable Subject Matter
8. Claims 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The present invention is directed to a pixel driving circuit of an OLED display. The closet prior arts, KE (US 20230215314 A1), LI (US 20210134917 A1), XU (US 20230076760 A1), CHA (US 20230090817 A1), CHO (US 20220190094 A1), and KANG (US 20210074783 A1), individually or in combination, discloses an OLED display device and a driving method similar to the claimed invention, the display device comprising K pixel rows; at least one pixel row of the K pixel rows comprises an initial signal line, a scan signal line, and a plurality of sub-pixels disposed sequentially along an extension direction of the initial signal line and the scan signal line; the initial signal line comprises a third initial signal line, the scan signal line comprises a second scan signal line, and at least one sub-pixel of the plurality of sub-pixels comprises a pixel drive circuit, and the pixel drive circuit comprises at least a storage capacitor, a second transistor, a third transistor as a drive transistor and an eighth transistor as an initialization transistor; and in a same sub-pixel, a first plate of the storage capacitor is connected to a first electrode of the second transistor and a control electrode of the driving transistor, and a second electrode of the second transistor is connected to a first electrode of the driving transistor; in the at least one pixel row, the eighth transistor is connected with the third initial signal line, the second scan signal line, and a second electrode of the drive transistor, and is configured to supply an initial signal of the third initial signal line to the second electrode of the drive transistor under control of the second scan signal line. However, the closet prior arts fail to teach wherein: in a direction perpendicular to the display substrate, the display substrate comprises a base substrate and a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer which are sequentially stacked on the base substrate; and the first semiconductor layer comprises active layers of the third transistor to the eighth transistor; the first conductive layer comprises control electrodes of the third transistor to the eighth transistor, the first electrode plate of the storage capacitor, and the first initial signal line; the second conductive layer comprises the second electrode plate of the storage capacitor; the second semiconductor layer comprises active layers of the first transistor and the second transistor; the third conductive layer comprises a first scan signal line, a third scan signal line, and a second initial signal line; the fourth conductive layer comprises first electrodes and second electrodes of the first transistor to the eighth transistor, and a connection electrode of the second electrode plate, and the third initial signal line; and the fifth conductive layer comprises a data signal line, a first power line and an anode connection electrode of the light emitting element.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623