Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harboe, US Patent Application Publication 2024/0330036 (hereinafter Harboe).
Regarding claim 1, Harboe teaches:
A hardware accelerator having a plurality of processing elements (see e.g. para. [0008], array of compute elements), the hardware accelerator comprising: an exception detector that detects an occurrence of an exception during an execution of a computation by the plurality of processing elements (see e.g. para. [0034], an exception/interrupt is detected), and an execution controller that, in response to the exception detector detecting the exception, causes the plurality of processing elements to sequentially re-execute the computation in which the occurrence of the exception has been detected (see e.g. para. [0034-5], [0052], execution is restarted in response to an exception), using re-execution information that has been used by at least a part of the plurality of processing elements for the execution of the computation and has been saved in a re-execution information storage before the detection of the exception (see e.g. para. [0034-5], [0052], execution is restarted using the previously saved and restored state from the shadow memory).
Regarding claim 3, Harboe teaches:
The hardware accelerator according to claim 1, wherein the computation is a matrix computation (see e.g. Harboe para. [0030]).
Claims 4, 6 are rejected for reasons corresponding to those given above for claims 1, 3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Harboe in view of Makkadayil et al., US Patent Application Publication 2024/0168841 (hereinafter Makkadayil).
Regarding claim 2, Harboe teaches:
The hardware accelerator according to claim 1, wherein the plurality of processing elements have a two-dimensional systolic array configuration (see e.g. para. [0026]),
Harboe fails to explicitly teach the hardware accelerator further comprises a first memory and a second memory each functioning as the re-execution information storage, the first memory storing information to be input to each of the plurality of processing elements configuring a first column of the plurality of processing elements, the second memory storing information to be input to each of the plurality of processing elements configuring a first row of the plurality of processing elements, and the execution controller causes the re-execution of the computation using the re-execution information read from the first memory and the second memory.
Makkadayil teaches separate SRAM and buffers used separately for columns or rows of systolic array processing elements (see e.g. fig. 9, para. [0062]).
While Harboe teaches storing backup information in shadow SRAM storage, Harboe fails to teach the SRAM split into two memories used specifically for a column or row of processing elements. Makkadayil teaches such separate SRAM stores used separately for columns or rows of systolic array elements. Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Harboe and Makkadayil such that the hardware accelerator further comprises a first memory and a second memory each functioning as the re-execution information storage, the first memory storing information to be input to each of the plurality of processing elements configuring a first column of the plurality of processing elements, the second memory storing information to be input to each of the plurality of processing elements configuring a first row of the plurality of processing elements, and the execution controller causes the re-execution of the computation using the re-execution information read from the first memory and the second memory. This would have provided an advantage of efficient storage and processing when it can be desirable to store and transmit weight data separately from other input data such as neural network processing, or where only some data needed to be reused (see e.g. Makkadayil para. [0019], [0036]).
Claim 5 is rejected for reasons corresponding to those given above for claim 2.
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
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