Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 5, 6, 8-10, 19, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 6, 7, 8, 19, and 20 of U.S. Patent No. 12,374,292 B2.
Instant claim 1 is a broader version of claim 1 of U.S. Patent No. 12,374,292 B2.
Claim 1 of U.S. Patent No. 12,374,292 B2 recites a shift register unit, comprising: “a first sensing control input circuit connected to a sensing control node, a sensing signal input terminal, a random signal input terminal, a clock control signal input terminal, and a first pull-up node” (e.g., column 47, lines 6-11) [encompassing instant claim 1’s first sensing control input circuit];
“at least one first output circuit, each of which is connected to the first pull-up node, a first clock signal input terminal, and a first signal output terminal; and configured to write a signal from the first clock signal input terminal to the first signal output terminal in response to control of a valid level signal at the first pull-up node” (e.g., column 47, lines 18-26);
“a first voltage control circuit, a first sensing input leakage prevention circuit and a first current limiting circuit; the first voltage control circuit is connected to a first power supply terminal, the first pull-up node and a first voltage control node, and is configured to write a valid level signal from the first power supply terminal to the first voltage control node in response to control of a valid level signal at the first pull-up node” (e.g., column 47, lines 27- 35);
“the first sensing control input circuit is connected to the first pull-up node through the first sensing input leakage prevention circuit, the first sensing control input circuit is connected to the first sensing input leakage prevention circuit at a first sensing input leakage prevention node connected to the first voltage control node, the first sensing input leakage prevention circuit is connected to the clock control signal input terminal and is configured to form a path between the first sensing input leakage prevention node and the first pull-up node in response to control of a valid level signal at the clock control signal input terminal” (e.g., column 47, lines 36- 47); and
“the first current limiting circuit is connected to the first voltage control node” (e.g., column 47, lines 50-52).
Each limitation of instant claim 1 is thereby met by, and fully encompassed within, claim 1 of the patent; the patented claim additionally recites, inter alia, the functional writes of the sensing control input circuit and the disconnection function, so that the patented claim 1 is a species falling wholly within the broader instant claim.
Instant claim 2 is identical in scope to the corresponding recitations of claim 1 of U.S. Patent No. 12,374,292 B2.
Claim 1 of U.S. Patent No. 12,374,292 B2 recites that the first sensing control input circuit is “configured to write a signal from the sensing signal input terminal to the sensing control node in response to control of a valid level signal from the random signal input terminal, and write a valid level signal to the first pull-up node in response to control of a valid level signal at the sensing control node and a valid level signal from the clock control signal input terminal” (e.g., column 47, lines 11-18).
Instant claim 5 is identical in scope to the corresponding recitations of claim 4 of U.S. Patent No. 12,374,292 B2.
Claim 4 of U.S. Patent No. 12,374,292 B2 recites “a first global reset circuit connected to a global reset signal input terminal, a second power supply terminal and the first pull-up node, and configured to write an invalid level signal from the second power supply terminal to the first pull-up node in response to control of a valid level signal from the global reset signal input terminal; and a first leakage prevention circuit; wherein the first global reset circuit is connected to the second power supply terminal through the first leakage prevention circuit; the first global reset circuit is connected to the first leakage prevention circuit at a first leakage prevention node connected to the first voltage control node; the first leakage prevention circuit is connected to the global reset signal input terminal and is configured to form a path between the first leakage prevention node and the second power supply terminal in response to control of a valid level signal from the global reset signal input terminal, and to disconnect the first leakage prevention node from the second power supply terminal in response to control of an invalid level signal from the global reset signal input terminal” (e.g., column 48, lines 13-37).
Instant claim 6 is identical in scope to the corresponding recitations of claim 4 of U.S. Patent No. 12,374,292 B2.
Claim 4 of U.S. Patent No. 12,374,292 B2 recites “a third load circuit between the first leakage prevention node and the first voltage control node, and configured to increase a load resistance between the first leakage prevention node and the first voltage control node; wherein the third load circuit comprises: an eighty-second transistor; and a control electrode of the eighty-second transistor is connected to the first voltage control node, a first electrode of the eighty-second transistor is connected to the first leakage prevention node, and a second electrode of the eighty-second transistor is connected to the first voltage control node” (e.g., column 48, lines 38-50); and “a fifth load circuit” comprising “an eighty-fourth transistor; and a control electrode of the eighty-fourth transistor is connected to the global reset signal input terminal, a first electrode of the eighty-fourth transistor is connected to the global reset signal input terminal, and a second electrode of the eighty-fourth transistor is connected to at least one of the first global reset circuit and the first leakage prevention circuit” (e.g., column 48, lines 51-67).
Instant claim 8 is identical in scope to claim 6 of U.S. Patent No. 12,374,292 B2.
Claim 6 of U.S. Patent No. 12,374,292 B2 recites the first pull-down noise reduction circuit comprising “a twenty-ninth transistor and a thirtieth transistor; a control electrode of the twenty-ninth transistor is connected to the clock control signal input terminal, a first electrode of the twenty-ninth transistor is connected to the first pull-down node, and a second electrode of the twenty-ninth transistor is connected to a first electrode of the thirtieth transistor; and a control electrode of the thirtieth transistor is connected to the sensing control node, and a second electrode of the thirtieth transistor is connected to the second power supply terminal” (e.g., column 49, line 61 - column 50, line 7); and
further comprising “an eighty-fifth transistor; the first electrode of the twenty-ninth transistor is connected to the first pull-down node through the eighty-fifth transistor; and a control electrode of the eighty-fifth transistor is connected to the sensing control node, a first electrode of the eighty-fifth transistor is connected to the first pull-down node, and a second electrode of the eighty-fifth transistor is connected to the first electrode of the twenty-ninth transistor” (e.g., column 50, lines 8-17).
Instant claim 9 is identical in scope to claim 7 of U.S. Patent No. 12,374,292 B2.
Claim 7 of U.S. Patent No. 12,374,292 B2 recites “a first display input circuit connected to a display signal input terminal, the first power supply terminal, and the first pull-up node, and configured to write a valid level signal from the first power supply terminal to the first pull-up node in response to control of a valid level signal from the display signal input terminal; and a first display reset circuit connected to a display reset signal input terminal, a second power supply terminal and the first pull-up node; and configured to write an invalid level signal from the second power supply terminal to the first pull-up node in response to control of a valid level signal from the display reset signal input terminal” (e.g., column 50, lines 19-32);
“at least one of a first display input leakage prevention circuit and a second leakage prevention circuit” (e.g., column 50, lines 33-35),
with both alternatives recited in full, including that “the first display reset circuit is connected to the second power supply terminal through the second leakage prevention circuit, the first display reset circuit is connected to the second leakage prevention circuit at a second leakage prevention node connected to the first voltage control node” and the second leakage prevention circuit’s path-forming and disconnection in response to the display reset signal (e.g., column 50, lines 51-64).
Instant claim 10 is identical in scope to the corresponding recitations of claim 8 of U.S. Patent No. 12,374,292 B2.
Claim 8 of U.S. Patent No. 12,374,292 B2 recites that the first sensing control input circuit comprises “a sensing control circuit and a first sensing input circuit” (e.g., column 50, lines 65-67); “the sensing control circuit is connected to the sensing control node, the sensing signal input terminal and the random signal input terminal, and is configured to write a signal from the sensing signal input terminal to the sensing control node in response to control of a valid level signal from the random signal input terminal” (e.g., column 51, lines 1-7); and
“the first sensing input circuit is connected to the sensing control node, the clock control signal input terminal, a sensing intermediate node and the first pull-up node, and configured to write a valid level signal to the sensing intermediate node in response to control of a valid level signal at the sensing control node and to form a path between the sensing intermediate node and the first pull-up node in response to control of a valid level signal from the clock control signal input terminal” (e.g., column 51, lines 8-17).
Instant claim 19 is a broader version of claim 19 of U.S. Patent No. 12,374,292 B2.
Claim 19 of U.S. Patent No. 12,374,292 B2 recites “A gate driving circuit, comprising: a plurality of cascaded shift register units, each of which is the shift register unit of claim 1” (e.g., column 56, lines 44-46). The patented gate driving circuit of narrower patented claim 1 falls wholly within the instant gate driving circuit of broader instant claim 1.
Instant claim 20 is a broader version of claim 20 of U.S. Patent No. 12,374,292 B2.
Claim 20 of U.S. Patent No. 12,374,292 B2 recites “A display substrate, comprising: a base substrate and a gate driving circuit on the base substrate, wherein the gate driving circuit is the gate driving circuit of claim 19” (e.g., column 56, lines 47-49).
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,374,292 B2 in view of Feng (US 2021/0201807 A1).
Instant claim 3 is almost identical in scope to claim 1 of U.S. Patent No. 12,374,292 B2.
Claim 1 of U.S. Patent No. 12,374,292 B2 recites the disconnection function added by instant claim 3: the first sensing input leakage prevention circuit is configured “to disconnect the first sensing input leakage prevention node from the first pull-up node in response to control of an invalid level signal at the clock control signal input terminal” (e.g., column 47, lines 47-50).
Claim 1 of U.S. Patent No. 12,374,292 B2 does not appear to recite the eighth transistor of instant claim 3, i.e., that the first sensing input leakage prevention circuit comprises an eighth transistor whose control electrode is connected to the clock control signal input terminal, whose first electrode is connected to the first sensing input leakage prevention node, and whose second electrode is connected to the first pull-up node.
However, Feng discloses the first sensing input leakage prevention circuit implemented as a single such transistor [second transmission transistor T2]: Paragraph 125: “the first electrode of the second transmission transistor T2 is connected to the leakage prevention node OF, and the second electrode of the second transmission transistor T2 is connected to the first node QI with T2’s gate electrode receiving the first clock signal CLKA per the same paragraph [Feng, Fig. 16: T2, CLKA, OF, Q1].
U.S. Patent No. 12,374,292 B2 and Feng are analogous art, because they are from the shared inventive field of shift register units for gate driving circuits of display devices employing leakage prevention at the pull-up node.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to implement the first sensing input leakage prevention circuit of the patented claim as Feng’s clock-gated transistor T2, so as to realize the claimed path-forming and disconnecting circuit with a minimal, known single-transistor implementation whose gate control by the clock control signal input terminal effects exactly the recited functions.
Moreover, it would have been obvious to one of ordinary skill in the art before the effective filing date because all the claimed elements were known in the prior art, and one skilled in the art could have combined Feng’s transistor implementation with the circuit of the patented claim by known methods with no change in their respective functions, and the combination would have yielded predictable results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claim construction (grounds pleaded in the alternative)
The claims recite, in several places, a junction node “connected to the first voltage control node” (claim 1: the first sensing input leakage prevention node; claim 5: the first leakage prevention node; claim 9: the second leakage prevention node).
Two reasonable constructions of “connected to” are addressed in the alternative.
Construction A (Ground I): “connected to” is satisfied by direct electrical connection, including the limiting case of a shared net; nothing in the claims requires intervening structure or nonzero impedance between the two recited nodes, and the instant application’s own admitted related art (FIG. 4) shows node SQ1 hard-wired to node OFFI - a zero-impedance “connection” between the two named nodes.
Construction B (Ground II): the recitation of two differently named nodes requires two distinct circuit nodes; the claims are then addressed under 35 U.S.C. 103. Construction A additionally cannot be narrower than the elected species itself, in which the sensing input leakage prevention node connects to the voltage control node through the first load circuit; “connected to” therefore at minimum embraces both direct and through-element connection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Ground I: Claims 1-3, 5, 10, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al (US 2021/0201807 A1).
Regarding claim 1, Feng discloses a shift register unit [Fig. 16; Figs. 5-6 (block level)], comprising:
a first sensing control input circuit [blanking input subunit 300’s selection control circuit 310 and third input circuit 320: Paragraph 104: “the blanking input sub-unit 300 includes a selection control circuit 310, a third input circuit 320, and a first transmission circuit 330”; Paragraph 105: “The selection control circuit 310 is configured to control the level of a third node H using a second input signal STU2 in response to the selection control signal OE”; Paragraph 107: “The third input circuit 320 is configured to transmit a first clock signal CLKA to a fourth node N under the control of the level of the third node H”; the blanking input serves line-by-line external-compensation sensing, Paragraphs 95-96; Fig. 16: 310 (B5, B6, C1, A4), 320 (B7), H, N]; and
at least one first output circuit, each of which is connected to a first pull-up node [Q1], a first clock signal input terminal [CLKB], and a first signal output terminal [CRT]; and
configured to write a signal from the first clock signal input terminal to the first signal output terminal in response to control of a valid level signal at the first pull-up node [Paragraph 173: “The gate electrode of the first output transistor D1 is connected to the first node Q1, the first electrode of the first output transistor D1 is configured to receive the second clock signal CLKB as the shift signal CR, the second electrode of the first output transistor D1 is connected to the shift signal output terminal CRT”; Fig. 16: 120, D1 (CLKB→CRT), D2 (CLKC→OP1), C2];
wherein the shift register unit further comprises: a first voltage control circuit [first leakage prevention transistor A1],
a first sensing input leakage prevention circuit [second transmission transistor T2], and
a first current limiting circuit [second leakage prevention transistor A2, diode-connected on node OF];
the first voltage control circuit is connected to a first power supply terminal [VDD], the first pull-up node [Q1] and a first voltage control node [leakage prevention node OF], and
is configured to write a valid level signal from the first power supply terminal to the first voltage control node in response to control of a valid level signal at the first pull-up node [Paragraph 81: “The gate electrode of the first leakage prevention transistorA1 is connected to the first
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node Q1, the first electrode of the first leakage prevention transistorA1 is configured to receive the second voltage VDD, and the second electrode of the first leakage prevention transistorA1 is connected to the leakage prevention node OF”; Fig. 16: A1, VDD, OF, Q1];
the first sensing control input circuit is connected to the first pull-up node through the first sensing input leakage prevention circuit [310/320’s output path reaches Q1 through T2: Paragraph 108: “The first transmission circuit 330 is electrically connected to the first node Q1, the fourth node N, and the leakage prevention node OF”],
the first sensing control input circuit is connected to the first sensing input leakage prevention circuit at a first sensing input leakage prevention node [OF] connected to the first voltage control node [OF; under Construction A the two recitations read on Feng’s single OF net - the first sensing input leakage prevention circuit is connected to a clock control signal input terminal [CLKA] and is configured to form a path between the first sensing input leakage prevention node and the first pull-up node in response to control of a valid level signal at the clock control signal input terminal [Paragraph 125: “the first electrode of the second transmission transistor T2 is connected to the leakage prevention node OF, and the second electrode of the second transmission transistor T2 is connected to the first node Q1”, T2’s gate receiving CLKA per the same paragraph; when 330 is on under CLKA the level of N is transmitted to Q1, Paragraph 108; the path is not formed at the invalid level of CLKA; Fig. 16: T1, T2, CLKA, OF, Q1]; and
the first current limiting circuit is connected to the first voltage control node [A2, a diode-connected transistor connected to OF: Paragraph 82: “the second leakage prevention transistor A2 adopts a diode connection”; Paragraph 6: “a gate electrode of the second leakage prevention transistor and a first electrode of the second leakage prevention transistor are configured to be connected to the leakage prevention node”, second electrode to VGL1; A2 sits in series in the Q1 discharge path and limits conduction through OF - Paragraph 84: “the first node Q1 is electrically connected to the first voltage terminal VGL1 through the first reset transistor R1 and the second leakage prevention transistor A2”; Paragraph 87: “the potential of the leakage prevention node OF is made to be higher than the first voltage”; Paragraph 88: “the second leakage prevention transistor A2 is multiplexed as a reset transistor”; same device species as the instant first current limiting circuit’s disclosed implementations - Fig. 16: A2; Fig. 3].
All of the foregoing is integrated in the single embodiment of Fig. 16; the mirrored second-channel (Q2) structure is additional to, and does not negate, the claimed combination (see Paragraphs 79-133, 169-229; Figs. 3, 5, 6, 13, 15, 16).
Regarding claim 2, Feng discloses that the first sensing control input circuit is connected to a sensing control node [H], a sensing signal input terminal [STU2], a random signal input terminal [OE], the clock control signal input terminal [CLKA], and the first pull-up node [Q1, through 330]; and
configured to write a signal from the sensing signal input terminal to the sensing control node in response to control of a valid level signal from the random signal input terminal [Paragraph 105, quoted at claim 1; STU2 is the shift/carry signal of another stage, Paragraph 106: “the shift register unit 10 of a certain stage may receive the shift signal CR output by the shift register unit 10 of the other stage as the second input signal STU2”; OE performs the row-selection function for external-compensation sensing, Paragraphs 95-96], and
write a valid level signal to the first pull-up node in response to control of a valid level signal at the sensing control node and a valid level signal from the clock control signal input terminal [B7 transmits the valid level of CLKA to N only under the control of valid H, Paragraph 107; T1 / T2 pass N’s level to Q1 only at valid CLKA, Paragraphs 108, 125; Fig. 16: B5, B6, B7, T1, T2, H, N, Q1].
Regarding claim 3, Feng discloses that the first sensing input leakage prevention circuit is configured to disconnect the first sensing input leakage prevention node from the first pull-up node in response to control of an invalid level signal at the clock control signal input terminal [T2 is gated by CLKA, Paragraph 125; the OF-Q1 path is formed when 330 “is turned on under the control of the first clock signal CLKA,” Paragraph 108, and is accordingly disconnected at the invalid level of CLKA (inherent gated operation)]; and
the first sensing input leakage prevention circuit comprises an eighth transistor [T2];
a control electrode of the eighth transistor is connected to the clock control signal input terminal [T2’s gate receives CLKA, Paragraph 125],
a first electrode of the eighth transistor is connected to the first sensing input leakage prevention node [OF], and
a second electrode of the eighth transistor is connected to the first pull-up node [Q1] [Paragraph 125, quoted at claim 1; Fig. 16: T2].
Regarding claim 5, Feng discloses a first global reset circuit [second reset transistor R2] connected to a global reset signal input terminal [TRST], a second power supply terminal [VGL1], and the first pull-up node [Q1], and
configured to write an invalid level signal from the second power supply terminal to the first pull-up node in response to control of a valid level signal from the global reset signal input terminal [Paragraph 212: “The gate electrode of the second reset transistor R2 is configured to receive the total reset signal TRST, the first electrode of the second reset transistor R2 is connected to the first node Q1, and
the second electrode of the second reset transistor R2 is connected to the leakage prevention node OF”]; and a first leakage prevention circuit [sixth reset transistor R6];
wherein the first global reset circuit is connected to the second power supply terminal through the first leakage prevention circuit [Q1-R2-OF-R6-VGL1];
the first global reset circuit is connected to the first leakage prevention circuit at a first leakage prevention node [OF] connected to the first voltage control node [OF; Construction A];
the first leakage prevention circuit is connected to the global reset signal input terminal and is configured to form a path between the first leakage prevention node and the second power supply terminal in response to control of a valid level signal from the global reset signal input terminal, and
to disconnect the first leakage prevention node from the second power supply terminal in response to control of an invalid level signal from the global reset signal input terminal [Paragraph 212: “The gate electrode of the sixth reset transistor R6 is configured to receive the total reset signal TRST, the first electrode of the sixth reset transistor R6 is connected to the leakage prevention node OF, and the second electrode of the sixth reset transistor R6 is connected to the first voltage terminal VGL1 to receive the first voltage”; Fig. 16: R2, R6, TRST, OF, VGL1].
Regarding claim 10, Feng discloses that the first sensing control input circuit comprises:
a sensing control circuit [selection control circuit 310] and
a first sensing input circuit [third input circuit 320 (B7) together with first transmission transistor T1]; the sensing control circuit is connected to the sensing control node [H], the sensing signal input terminal [STU2] and the random signal input terminal [OE], and
is configured to write a signal from the sensing signal input terminal to the sensing control node in response to control of a valid level signal from the random signal input terminal [Paragraph 105]; and
the first sensing input circuit is connected to the sensing control node [H], the clock control signal input terminal [CLKA], a sensing intermediate node [N] and the first pull-up node [Q1], and
configured to write a valid level signal to the sensing intermediate node in response to control of a valid level signal at the sensing control node [B7 transmits the valid level of CLKA to N under the control of H, Paragraph 107] and
to form a path between the sensing intermediate node and the first pull-up node in response to control of a valid level signal from the clock control signal input terminal [T1 (gate CLKA) conducts N to OF, Paragraph 125, with the N-Q1 path completed concurrently through T2 at the same valid CLKA, Paragraph 108; Fig. 16: B7, T1, T2, N, H].
Regarding claim 19, Feng discloses a gate driving circuit, comprising: a plurality of cascaded shift register units, each of which is the shift register unit of claim 1 [Paragraph 21: “a gate driving circuit, comprising a plurality of cascaded shift register units”; cascade via the shift signal CR of each stage supplied as the input signal of other stages, Paragraph 106; Figs. 22, 24] (see Paragraphs 21, 106, 230-259; Figs. 22-25).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Ground II: Claims 1-3, 5, 6, 9, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2021/0201807 A1) in view of Lee (US 2022/0366836 A1).
Lee (US 2022/0366836 A1) qualifies as prior art under 35 U.S.C. 102(a)(2). Although Lee was published 17 November 2022 and its U.S. application was filed 1 February 2022, Lee was effectively filed, under 35 U.S.C. 102(d)(2), as of 12 May 2021 — the filing date of its foreign priority application KR 10-2021-0061609, which provides written-description support for the subject matter relied upon herein. Lee names another inventor, and no exception under 35 U.S.C. 102(b)(2) applies.
This ground is presented in the alternative to Ground I under Construction B (distinct nodes), and additionally reaches claims 6 and 9, for which Ground I is not asserted.
Feng’s disclosure is applied as mapped in Ground I, incorporated herein. The combination and its rationale are stated once immediately below and are relied upon by each per-claim analysis that follows; the reasons for combining remain the same for each claim of this ground except where otherwise noted.
The combination and its rationale
Feng and Lee are analogous art: both are from the same field of endeavor of gate/ scan driving circuits for display devices, and more particularly line-selective sensing scan drivers for external compensation, addressing leakage at the driver’s internal control nodes.
Lee discloses a scan driver stage in which series transistor pairs having diode connection structures are deployed in the signal input and reset paths, with the pairs’ common midpoint constituting a distinct node tied into a leakage-control bias network:
Lee, Paragraph 109: “each of the (1-1)-th transistor T1-1 and the (1-2)-th transistor T1-2 may have a diode connection structure”;
Lee, Paragraph 109: “A gate electrode of the (1-1)th transistor T1-1 and a gate electrode of the (1-2)-th transistor T1-2 may be commonly connected to the first input terminal IN1” (i.e., T1-1 ‘s control electrode and first electrode both at the input terminal, its second electrode continuing into the circuit);
Lee, Paragraph 110 (the pair’s common node “may correspond to a sixth node N6”); Lee, Paragraph 112: “The eighth transistor may include a (8-1)-th transistor T8-1 and a (8-2)-th transistor T8-2 connected in series” (the same practice on the reset path);
Lee, Paragraph 159: “The leakage controller 180 may supply the control voltage VON supplied to the third input terminal IN3”;
Lee, Paragraph 160: “The leakage controller 180 may include a twentieth transistor T20 and a twenty-first transistor T21 connected between the third input terminal IN3 and the sixth node N6”.
Lee, Fig. 4: 110, 120, 141, 160, 180, T1-1, T1-2, T8-1, T8-2, T20, T21, N1, N6, IN1, IN2, IN3 (single integrated stage embodiment).
It would have been obvious before the effective filing date to modify Feng in view of Lee by
(i) constituting the junctions of Feng’s guarded paths (the sensing transmission path N-T1-T2-Q1 and the reset chains Q1-R1 / R2-R5 / R6-VGL1) as distinct midpoint nodes joined to Feng’s biased node OF through series transistors having diode connection structures, in the manner Lee deploys such structures around his biased midpoint N6, the gate-at-the-bias-node anchoring being Feng’s own established configuration for a diode-connected device on OF [Paragraphs 6, 82]; and
(ii) interposing Lee’s input-terminal series structure - control electrode and first electrode commonly at the signal input terminal, second electrode to the following circuit [Lee, Paragraph 109] - in Feng’s total reset signal (TRST) input line to the gates of R2/R6, as Lee deploys the same structure on his reset-side input
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path [Lee, Paragraph 112].
Both references direct the artisan to suppress leakage through the input and reset paths of the pull-up node by controlling those paths’ junction nodes –
Feng by biasing the shared junction from the supply [Paragraph 81] so that, Paragraph 213: “connecting the second reset transistor R2 to the leakage prevention node OF may prevent the first node Q1 from leaking through the second reset transistor R2”;
Lee by combining series diode-connection structures with an actively biased distinct midpoint node in the same paths [Lee, Paragraphs 109-112, 159-160].
The modification is the combination of prior-art elements according to known methods yielding no more than the predictable result of additionally impeding conduction (increased series load resistance) through the guarded paths and input lines, and the use of a known technique to improve a similar device in the same way. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
It employs Feng’s own device species and Lee’s own placements without changing either reference’s principle of operation.
Regarding claim 1, under Construction B, Feng does not disclose a first sensing input leakage prevention node connected to the first voltage control node as two distinct nodes,
Feng’s sensing-path junction and voltage control node being the single shared net OF.
However, Lee discloses a distinct series-pair midpoint node [N6] tied into the leakage-bias network through interposed series structures [Lee, Paragraphs 109-110, 159-160; Lee, Fig. 4: N6, 180].
It would have been obvious to constitute the junction of Feng’s sensing transmission path as such a distinct node joined to the biased node OF through Lee’s interposed series structure, because both references teach suppressing leakage through the pull-up node’s input paths by controlling the paths’ junction node, and providing the junction as a distinct node coupled to the bias node through the series structure predictably augments that suppression by adding series impedance in the guarded path - a combination of familiar elements according to known methods yielding predictable results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
In the combination, the junction of Feng’s sensing transmission path is a distinct first sensing input leakage prevention node connected to the first voltage control node [OF] through the interposed diode-connection structure. Feng discloses every remaining limitation of claim 1 as detailed in Ground I.
Regarding claim 2, Feng discloses all the limitations of this claim, as previously detailed in Ground I; the claim stands rejected as depending from claim 1 as addressed above.
Regarding claim 3, Feng discloses all the limitations added by this claim, as previously detailed in Ground I [T2: Paragraphs 108, 125], the recited first sensing input leakage prevention node being provided in the combination as set forth regarding claim 1.
Regarding claim 5, under Construction B, Feng does not disclose a first leakage prevention node connected to the first voltage control node as two distinct nodes (the R2/R6 junction and the voltage control node being the single net OF).
However, Lee discloses the distinct-midpoint architecture identified above, including on the reset path [Lee, Paragraphs 110, 112, 160].
In the combination, and for the same reasons stated regarding claim 1, the junction of Feng’s R2/R6 total-reset chain is a distinct first leakage prevention node connected to the first voltage control node through the interposed structure.
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Feng discloses every remaining limitation of claim 5 as detailed in Ground I [Paragraph 212].
Regarding claim 6, Feng does not disclose a third load circuit between the first leakage prevention node and the first voltage control node, and configured to increase a load resistance between the first leakage prevention node and the first voltage control node, comprising an eighty-second transistor whose control electrode is connected to the first voltage control node, first electrode is connected to the first leakage prevention node, and second electrode is connected to the first voltage control node; nor a fifth load circuit comprising an eighty-fourth transistor whose control electrode is connected to the global reset signal input terminal, first electrode is connected to the global reset signal input terminal, and second electrode is connected to at least one of the first global reset circuit and the first leakage prevention circuit (Feng’s R2/R6 gates connect directly to TRST).
However, Lee discloses series transistors having diode connection structures interposed at such junctions and input lines: the input-terminal anchoring with control electrode and first electrode commonly at the signal input terminal and second electrode to the following circuit [Lee, Paragraph 109], deployed also on the reset path [Lee, Paragraph 112], with the series midpoint constituting the distinct node tied to the bias network [Lee, Paragraphs 110, 159-160]; and
Feng supplies the gate-at-the-bias-node anchoring of a diode-connected device on OF [Paragraphs 6, 82].
In the combination set forth in the rationale above, and for the same reasons to combine, the interposed structure between the first leakage prevention node and the voltage control node is the third load circuit with the recited eighty-second-transistor anchoring, its diode-connected series conduction increasing the load resistance between the two nodes, and the structure interposed in the TRST input line is the fifth load circuit with the recited eighty-fourth-transistor anchoring.
Regarding claim 9, within Feng’s integrated Fig. 16 embodiment the first input circuit 110 adopts the two-transistor structure of Fig. 14C [Paragraph 182: “the first input circuit 110 includes a first input transistor B1 and a second input transistor B2, that is, the first input circuit 110 adopts the circuit structure illustrated in FIG. 14C”],
in which the pull-up node is charged from the display signal input terminal STU1 itself [Fig. 14c: STU1, B1, OF, B2, Q1];
that embodiment therefore does not disclose a first display input circuit configured to write a valid level signal from the first power supply terminal to the first pull-up node in response to the display signal input terminal.
However, Feng expressly teaches supply-charged implementations of the same first input circuit 110 as interchangeable circuit structures:
Paragraph 168: “the shift register unit 10 may be implemented as the circuit structure illustrated in FIG. 13”, in which Paragraph 169: “The gate electrode of the first input transistor B1 is configured to receive the first input signal STU1, the first electrode of the first input transistor B1 is configured to receive the first voltage VDD, the second electrode of the first input transistor B1 is connected to the first node Q1” (Feng’s internal “first voltage” / “second voltage” labeling of VDD is inconsistent; the identified signal VDD controls), and
the Fig. 14B implementation likewise charges from VDD [Fig. 14B: VDD, B1, B2, Q1; Fig. 13: B1].
This claim’s charging limitation presents a reason to combine distinct from the general rationale of this ground: it would have been obvious to implement the first input circuit 110 of Feng’s Fig. 16 unit with Feng’s own VDD-charged implementation - the simple substitution of one known, expressly interchangeable element for another from the reference’s own menu of “circuit structures” for the same circuit block [Paragraphs 168-172, 182], with predictable results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
The resulting first display input circuit is connected to the display signal input terminal [STU1], the first power supply terminal [VDD], and the first pull-up node [Q1], and writes a valid level from the supply in response to the display signal.
Feng further discloses a first display reset circuit [first reset transistor R1] connected to a display reset signal input terminal [STD], a second power supply terminal [VGL1] and the first pull-up node, writing the invalid level from the supply on valid STD [Paragraph 209: “The gate electrode of the first reset transistor R1 is configured to receive the display reset signal STD”, electrodes at Q1 and OF per the same paragraph]; and
the “at least one of” limitation is met by the second leakage prevention circuit [fifth reset transistor R5]: the display reset circuit connects to the second power supply terminal through it [Q1-R1-OF-R5-VGL1] at a second leakage prevention node [the R1/R5 junction], and
it is connected to the display reset signal input terminal, forming and disconnecting the path per the level of STD [Paragraph 209: “The gate electrode of the fifth reset transistor R5 is configured to receive the display reset signal STD, the first electrode of the fifth reset transistor R5 is connected to the leakage prevention node OF” and “the second electrode of the fifth reset transistor R5 is connected to the first voltage terminal VGL1 to receive the first voltage”; Fig. 16: R1, R5, STD].
Under Construction A the second leakage prevention node connected to the first voltage control node reads on the shared OF net; under Construction B, the node is provided as a distinct node in the combination with Lee, as set forth regarding claims 1 and 5. Claim 9 is accordingly unpatentable over Feng in view of Lee under either construction.
Regarding claim 10, Feng discloses all the limitations added by this claim, as previously detailed in Ground I.
Regarding claim 19, Feng discloses the cascaded gate driving circuit as previously detailed in Ground I [Paragraphs 21, 106; Figs. 22, 24]; the claim stands rejected as reciting the shift register unit of claim 1 as addressed above.
Ground III: Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2021/0201807 A1) in view of Ohara et al (US 2015/0179101 A1);
or, in the alternative, under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2021/0201807 A1) in view of Lee (US 2022/0366836 A1) as applied to claim 2 above, and further in view of Ohara et al (US 2015/0179101 A1).
As to the limitations of claims 1 and 2 from which claim 8 depends, Feng discloses them as set forth in Ground I (Construction A); under Construction B they are provided by the combination of Feng and Lee as set forth in Ground II, and the modification per Ohara set forth below applies equally to that combination.
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Regarding claim 8, Feng discloses the first pull-down noise reduction circuit comprising the twenty-ninth and thirtieth transistors: the first control transistor E1, gated by the clock control signal CLKA, between the first pulldown node QB_A and the common control node CC [Paragraph 197: “the first electrode of the first control transistor E1 is connected to the fifth node QB_A, and the second electrode of the first control transistor E1 is connected to the common control node CC”, E1’s gate receiving CLKA per Paragraphs 196-197],
with the chain completed from CC to the second power supply by the H-gated device [E3; Fig. 16: E1, E3, QB_A, CC, H], writing the invalid level to the pull
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down node in response to valid H and valid CLKA.
Feng does not disclose an eighty-fifth transistor having a control electrode connected to the sensing control node, a first electrode connected to the first pull-down node, and a second electrode connected to the first electrode of the twenty-ninth transistor.
Feng and Ohara are analogous art: both are from the same field of endeavor of thin-film-transistor driving circuitry for display devices - Feng’s sensing gate driver serving the external compensation of light-emitting display pixels of the very kind Ohara drives - and Ohara is additionally reasonably pertinent to the particular problem addressed by the eighty-fifth transistor, namely isolating a circuit node from conduction and coupling through a series-connected, differently-controlled device when a common control signal is deselected.
Ohara discloses that a switching element gated by a common control line and arranged in series with a differently-controlled device may equivalently be provided as one transistor on one side of that device or as two transistors, commonly gated by the same control line, on both sides of that device.
Ohara’s Fig. 7 embodiment provides two emission control transistors on one emission line flanking the differently-controlled driving transistor:
Ohara, Paragraph 89: “The transistor T4 has its gate terminal connected to the emission line EMi in the i-th row, and is between the source terminal of the transistor T1 and the anode terminal of the organic EL element OLED”;
Ohara, Paragraph 89: “The transistor T5 has its gate terminal connected to the emission line EMi in the i-th row, and is between the HIGH level power supply line ELVDD and the drain terminal of the transistor T1” [Ohara, Fig. 7: ELVDD, T5, T1 (gate VG), T4, EMi, OLED];
both turn off together, severing the path on both sides of T1 [Ohara, Paragraph 93: “the emission line EMi in the i-th row changes its state to LOW level, so the transistors T4, T5 turn OFF”, cutting the T1-to-OLED connection and the ELVDD-to-T1 connection].
Ohara’s Fig. 9 provides the single-transistor variation of the same circuit:
Ohara, Paragraph 99: “The pixel circuit 11 according to the present variation is the pixel circuit 11 in FIG. 7, without the transistor T5”, and
Ohara, Paragraph 99: “The pixel circuit 11 according to the present variation operates the same way as the circuit according to the second embodiment” [Ohara, Fig. 9: ELVDD, T1, T4, EMi].
Ohara thus expressly teaches the one-transistor and two-transistor commonly-gated configurations as interchangeable, with the two-transistor configuration providing isolation on both sides of the intermediate device when the common line is deselected, in service of preventing unwanted conduction [Ohara, Paragraph 36: “the emission control transistor stops the supply of drive current to the electrooptic element during a period in which the preliminary charging takes place”; Ohara: “This suppresses abnormal emission of the organic EL element OLED”].
It would have been obvious before the effective filing date to implement the H-controlled gating of Feng’s pull-down noise reduction chain in Ohara’s two-transistor, commonly-gated configuration - that is, to provide, in addition to the H-gated device on the supply side of the chain, a second H-gated transistor on the pull-down-node side of the CLKA-gated transistor E1, with its control electrode at the sensing control node [H], its first electrode at the first pulldown node [QB_A], and its second electrode at E1’s first electrode.
The rationale: Ohara teaches the one- and two-transistor commonly-gated configurations as art-recognized interchangeable implementations of the same series gating function (“operates the same way”), and teaches that the two-transistor form severs the path on both sides of the intermediate differently-controlled device when deselected; applying that known configuration to Feng’s chain - where the common signal H is already present and gates one end - is the use of a known technique to improve a similar device in the same way, and the simple substitution of one known configuration for another, with the predictable result that the pull-down node is isolated from the CLKA-gated device’s conduction and coupling when the stage is unselected. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
The resulting circuit is the claimed twenty-ninth, thirtieth, and eighty-fifth transistor arrangement.
As further evidence that providing one or two commonly-gated transistors in such a series path was a known and interchangeable design choice:
Lin (US 2022/0284860 A): “Each pixel can include one or two emission transistors.”;
Choi (US 2006/0255244 A1) illustrates, in one document, pixel test circuits having one emission-line-gated transistor [Choi, Fig. 3: M5, E1] and, alternatively, two transistors commonly gated by the same emission line flanking the differently-controlled driving transistor [Choi, Fig. 4: M5, M6, M1, E1]; and
the Park (KR 20060114470 A) publication teaches each such commonly-signaled blocking element as independently sufficient while providing both –
Park (MT): “the first light emission control element 114 may prevent the leakage current generated in the pixel driving circuit 112 during the data programming period”;
Park (MT): “the second light emission control element 116 can prevent the leakage current generated in the pixel driving circuit 112 during the data programming period”;
Park (MT): “the first light emission control signal and the second light emission control signal are the same waveform signals.”
Ground IV: Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2021/0201807 A1) in view of Yun et al (US 2022/0199034 A1);
or, in the alternative, under 35 U.S.C. 103 as being unpatentable over Feng et al (US 2021/0201807 A1) in view of Lee (US 2022/0366836 A1) as applied to claim 1 above, and further in view of Yun et al (US 2022/0199034 A1).
As to the limitations of claims 1 and 19 from which claim 20 depends, Feng discloses them as set forth in Ground I (Construction A); under Construction B they are provided by the combination of Feng and Lee as set forth in Ground II, and the modification per Yun set forth below applies equally to that combination.
Regarding claim 20, Feng discloses a display device comprising the gate driving circuit of claim 19 [Paragraph 22: “a display device, comprising the gate driving circuit according to any one of the embodiments of the present disclosure”; Fig. 26: display device 1, gate driving circuit 20 coupled by gate lines GL to the pixel region 50 (pixel units 510)] but does not expressly disclose a base substrate with the gate driving circuit on the base substrate.
However, Yun discloses a display panel whose gate driver circuit is provided on the panel’s substrate: Yun, Paragraph 4: “The switching transistor of the pixel circuit may be switched based on the gate signal output from a gate driver circuit disposed on a substrate of a display panel”; Yun, Paragraph 57: “each of a sub-pixel circuit and a gate driver circuit formed on a substrate of a display panel can be embodied as a transistor of an n-type MOSFET structure”.
Feng and Yun are analogous art, both being from the same field of endeavor of gate driving circuits for display devices, and more particularly shift-register gate drivers with line-selective sensing for external compensation.
It would have been obvious before the effective filing date to provide Feng’s gate driving circuit on the base substrate of the display panel it drives, as Yun teaches for gate driver circuits of the same kind, thereby yielding a display substrate comprising the base substrate and the gate driving circuit on the base substrate.
The rationale: forming the gate driver circuit on the display panel’s substrate together with the pixel circuits it drives is a known arrangement for such thin-film-transistor gate drivers [Yun, Paragraphs 4, 57], consistent with the coupling of Feng’s gate driving circuit 20 to the pixel region by the gate lines depicted in Fig. 26; applying that known arrangement to Feng’s circuit is the combination of prior-art elements according to known methods, and the use of a known technique to improve a similar device in the same way, with predictable results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Election/Restrictions
Applicant’s reply filed 14 July 2026 to the Election of Species requirement mailed 14 May 2026 is acknowledged.
In the written reply, applicant “provisionally elect[ed] to continue prosecution of Species 5” (drawn to the shift register unit of FIG. 6A), with traverse, and identified claims 1-20 as corresponding to the elected species.
That identification was not correct: by way of example, claim 4 requires the second load circuit comprising the eleventh capacitor C11, and claim 7 requires the fourth load circuit comprising the eighty-third transistor, neither of which is present in FIG. 6A (nor could the full claim set be examined within any single disclosed species).
During an interview between Zhuo Xu (Reg. No. 62,987) and the examiner on 22 July 2026, applicant changed the election to Species 17, drawn to the shift register unit of FIG. 12G, with the traversal maintained. The substitute election is acknowledged and entered; the election of record is Species 17 (FIG. 12G), with traverse.
Zhuo Xu identified claims 1-3, 5-6, 8-10 and 19-20 as encompassing elected Species 17.
Claims 1-3, 5, 6, 8-10, 19, and 20 read on elected Species 17 and are examined on the merits herein.
Claims 4, 7, and 11-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected species, there being no allowable generic or linking claim (the withdrawn claims are drawn to current-limiting implementations and to sensing-control-guard and second-channel arrangements of the nonelected species that are not present in FIG. 12G). Applicant timely traversed the requirement; the traversal is addressed below and the right to petition under 37 CFR 1.144 is preserved.
The traversal is on two grounds.
First, applicant submits that FIG. 6A illustrates the first load circuit 301 (eighty-first transistor M81) and FIG. 6B illustrates the second load circuit 302 (eleventh capacitor C11), and that, as disclosed in the original specification and as stated in original claim 4, the two load circuits “may be included in a same first current limiting circuit 300” - i.e., that the species are not mutually exclusive because the specification contemplates their combination.
Second, applicant submits that all other unit figures “further define the solutions shown in Figs. 6A and 6B” and “show how to particularly implement the various circuits shown in Fig. 6A” - i.e., that the remaining species are implementations of, rather than alternatives to, the FIG. 6A/6B disclosure.
On these grounds applicant requests that the requirement be withdrawn and all claims examined.
This is not found persuasive.
As to the first ground: the species of the requirement are the disclosed embodiments, and the disclosed embodiments are mutually exclusive.
FIG. 6A and FIG. 6B disclose alternative implementations of the first current limiting circuit - a diode-connected transistor providing series resistance in the path of the first voltage control node, versus a capacitor providing shunt capacitance from that node to the second power supply terminal - and the drawings never combine them: across all twenty-nine disclosed unit figures, the first load circuit 301 (M81) and the second load circuit 302 (C11) are not co-drawn in any figure.
The specification’s own framing preserves the alternatives as alternatives: “the first current limiting circuit 300 may selectively include at least one of the first load circuit 301 (the eighty-first transistor M81), the second load circuit 302 (the eleventh capacitor C11), the third load circuit 303 (the eighty-second transistor M82), and the fourth load circuit 304” (instant Paragraph 195).
That the specification textually contemplates, and original claim 4 recites, a combination of the two load circuits does not merge the disclosed single-implementation embodiments into one species; it at most describes a further, different embodiment - one that is illustrated in no figure and that applicant did not elect.
A species restriction divides the disclosed mutually exclusive embodiments; the possibility of claiming features of two species in combination does not make the species the same invention. The FIG. 6A unit (series device, no shunt capacitor) and the FIG. 6B unit (shunt capacitor, no series device) have mutually exclusive characteristics as disclosed, in structure and in operation, which is the distinctness the requirement found.
As to the second ground: the characterization of the remaining figures as implementations of FIG. 6A is contrary to the drawings.
The B-series figures (FIGS. 6B, 7B, 9B, 10B, 12B, 12D, 14B, 15B, 16B, 16D) omit the eighty-first transistor M81 entirely, substituting the eleventh capacitor C11 in its stead;
a unit lacking M81 is not a particular implementation of the FIG. 6A unit that is built upon M81 - it is a structurally exclusive alternative to it.
The same is true across the set: each figure presents a different, mutually exclusive combination of the disclosed circuits - for example, the fourth load circuit 304 (eighty-third transistor) appears only in FIGS. 12C, 12D, 16C, and 16D;
the fifth load circuit 305 (eighty-fourth transistor M84) appears only in FIGS. 12G and 16E; and the second-channel structures appear only in the later figure groups.
These are substitutions of, and mutually exclusive combinations among, the disclosed circuits - not progressive refinements of a single embodiment.
The specification presents each figure as its own embodiment and nowhere states that the figures are successive stages of one embodiment; and applicant’s own submission that the later figures “further define the solutions” of FIGS. 6A and 6B - two figures that are themselves mutually exclusive - concedes that the figures differ from one another in structure.
The reply identifies no pair of the twenty-nine species that shares all of its characteristics with another; the mutual-exclusivity and not-obvious-variants findings of the requirement therefore stand.
It is additionally noted that the traversal does not challenge the requirement’s finding of a serious search and/or examination burden (the species “require a different field of search”, e.g., different subclasses, resources, or search strategies), which accordingly stands; and that the reply identifies no claim as generic. As stated in the requirement, “Currently, no claims appear to be generic.”
The requirement is still deemed proper and is therefore made FINAL.
Claims 4, 7, and 11-18 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b). Upon the allowance of a generic claim, applicant will be entitled to consideration of claims to additional species which depend from or otherwise require all the limitations of an allowable generic claim, as provided by 37 CFR 1.141.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. The documents listed on the attached ‘Notice of References Cited’ are cited to further evidence the state of the art pertaining to shift registers.
Pertinent art made of record
Feng (CN 113781967 A) (shift register unit having pull-down node control transistors including a transistor gated by the sensing control node with a first electrode at the first pull-down node, in series with a clock-gated transistor);
Feng (CN 111179808 A) (sensing shift register with a two-transistor sensing noise reduction circuit at the pull-down node, gated by the first clock signal and the sensing control node);
Lee (US 2014/0198136 A1) (pixel switching units taught as implementable by a single transistor or by a plurality of transistors connected in series, commonly responsive to the same control signal).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached Monday - Friday (7:30AM - 4PM).
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
7 August 2026
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