DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 31 and 32 are objected to because of the following informalities:
The uses of the phrases “at least first memory cell”, “at least second memory cell” and “at least third memory cell” should each contain an article. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 5, 14 – 22 and 34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 14 and claim 34 recite the limitation "the number of access operations". There is insufficient antecedent basis for this limitation in the claim. Claims 2 – 5 and 15 – 22 inherit and do not correct this deficiency.
Claim 14 recites “the determining” in its final sentence. It is not clear which of the two “determining” steps this refers to. Claims 15 – 22 inherit and do not correct this deficiency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 3, 6 – 8, 12 – 16, 23 – 28, 31, 32 and 34 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Bronner et al. (US Patent Application Publication 2016/0071608), hereinafter Bronner.
Regarding claim 1, Bronner teaches a memory system comprising:
a memory apparatus including a plurality of memory cells (Fig. 1, the memory sub-system 107. According to paragraphs 0056 and 0065 it can be any number of memory implementations including memory cells); and
a controller that controls a curing operation (Fig. 1, the memory controller 105 which provides anneal control to the memory subsystem. Paragraph 0088, an annealing operation is a restorative healing operation, i.e. a curing operation) to be performed on a first memory cell among the plurality of memory cells (Any of the memory cells of the memory 107) when the number of access operations performed on the first memory cell exceeds a preset number of times (Paragraph 0077, an anneal operation within an IC may be based on a programmed usage threshold).
Regarding claim 2, Bronner teaches the memory system of claim 1, wherein the access operations include at least one read operation, or at least one write operation, or both (Paragraph 0003, program and erase operations produce defects in memory, limiting their usefulness in applications that required frequent write operations. That is, program erase cycles are write operations).
Regarding claim 3, Bronner teaches the memory system of claim 1, wherein the curing operation includes generating heat inside the first memory cell (Paragraph 0059, the anneal operation is performed by heating the memory element).
Regarding claim 6, Bronner teaches a memory system comprising:
a memory apparatus including a plurality of memory cells (Fig. 1, the memory sub-system 107. According to paragraphs 0056 and 0065 it can be any number of memory implementations including memory cells); and
a controller that controls a curing operation (Fig. 1, the memory controller 105 which provides anneal control to the memory subsystem. Paragraph 0088, an annealing operation is a restorative healing operation, i.e. a curing operation) to be performed on a first memory cell among the plurality of memory cells (Any of the memory cells of the memory 107) when an error rate of the first memory cell exceeds a preset value (Paragraph 0077, an anneal operation within an IC may be based on a programmed error rate threshold).
Regarding claim 7, Bronner teaches the memory system of claim 6, wherein the error rate includes an error rate for the number of access operations performed on the first memory cell (Paragraph 0077, the error rates can include bit error rates and programming error rates. Paragraph 0160, a bit error is indicated by error-correction-codes, which detects memory errors according to paragraph 0282, therefore a bit error is an error for access operations. Paragraph 0131, a programming operation is a write operation, therefore a programming error is an error rate for access operations).
Regarding claim 8, Bronner teaches the memory system of claim 6, wherein the curing operation includes generating heat inside the first memory cell (Paragraph 0059, the anneal operation is performed by heating the memory element).
Regarding claim 12, Bronner teaches the memory system of claim 6, wherein the memory apparatus further comprises a write circuit that performs the curing operation under control of the controller (Fig. 37 and paragraph 0278, one embodiment taught uses the word line driver of the memory’s read/write circuit to provide the annealing heat).
Regarding claim 13, Bronner teaches the memory system of claim 6, wherein the controller further comprises an error correction code (ECC) circuit that corrects and manages an error in data output from the plurality of memory cells (Paragraphs 0255 and 0287, error detecting circuitry for carrying out the anneal operation may include ECC).
Regarding claim 14, Bronner teaches an operation method of a memory system, comprising:
managing numbers of access operations for a plurality of memory cells (Paragraph 0077, an anneal operation within an IC may be based on a number of program erase cycles);
determining whether a first memory cell exists among the plurality of memory cells, the number of access operations performed on the first memory cell exceeding a set number of times (Paragraph 0077, an anneal operation within an IC may be based on exceeding a programmed usage threshold);
determining data stored in the first memory cell when the first memory cell exists (Paragraph 0077, a determination is made that the event to trigger the anneal exists); and
performing a curing operation on the first memory cell according to a result of the determining (The anneal operation is performed as stated in paragraph 0077).
Regarding claim 15, Bronner teaches the operation method of claim 14, wherein the curing operation includes generating heat inside the first memory cell (Paragraph 0059, the anneal operation is performed by heating the memory element).
Regarding claim 16, Bronner teaches the operation method of claim 15, wherein the generating of heat in the first memory cell comprises providing a curing pulse to the first memory cell (Paragraph 0215, the annealing is performed by providing current through the memory).
Regarding claim 23, Bronner teaches an operation method of a memory system, comprising:
correcting and managing an error in data output from a plurality of memory cells (Paragraphs 0160 and 0255, the system contains bit error correction codes);
determining states of the plurality of memory cells each according to an error rate calculated in the managing (Paragraphs 0077 and 0161, the error rates and counts); and
performing a curing operation based on the error rate (Paragraph 0161, the anneal can be triggered based on error rate).
Regarding claim 24, Bronner teaches the operation method of claim 23, wherein the determining of the states of the plurality of memory cells comprises:
determining a first memory cell having the error rate less than a first set value to be in a normal state (Fig. 4 and paragraph 0101, if the event count is below Thresh_P/the passive evacuation threshold, then the pages are evacuated passively, i.e. the memory is in normal operation); and
determining a second memory cell having the error rate equal to or greater than the first set value and less than a second set value to be in an intermittent failure state (Fig. 4/Paragraph 0101, if the event count is above Thresh_P/the passive evacuation threshold but below Thresh_A/the active evacuation threshold, the memory is in a state where anneal is needed but not urgent).
Regarding claim 25, Bronner teaches the operation method of a memory system of claim 24, further comprising determining a third memory cell having the error rate equal to or greater than the second set value to be in a hard fail state (Fig. 4/Paragraph 0101, if the event count is above Thresh_A, then the memory is in a state where anneal is needed and urgent).
Regarding claim 26, Bronner teaches the operation method of claim 25, further comprising performing a repair operation on the third memory cell determined to be in the hard fail state (Paragraph 0101, the anneal controller begins active, competitive evacuation; Paragraph 0097 and Fig. 3, anneal is then performed on the evacuated memory).
Regarding claim 27, Bronner teaches the operation method of claim 24, wherein the performing of the curing operation is performed on the second memory cell determined to be in the intermittent failure state (Paragraph 0101, the anneal controller begins active deferential evacuation; Paragraph 0097 and Fig. 3, anneal is then performed on the evacuated memory).
Regarding claim 28, Bronner teaches the operation method of claim 27, wherein the performing of the curing operation comprises generating heat in the second memory cell determined to be in the intermittent failure state (Paragraph 0059, the anneal operation is performed by heating the memory element).
Regarding claim 31, Bronner teaches a memory apparatus comprising:
a cell array including a plurality of memory cells (Fig. 1, the memory sub-system 107. According to paragraphs 0056 and 0065 it can be any number of memory implementations including memory cells);
a write circuit that stores data in at least first memory cell of the plurality of memory cells on the basis of a write command (Fig. 37/paragraph 0278, there is an operation select signal applied to the word line to perform a write);
a read circuit that outputs data from at least second memory cell of the plurality of memory cells on the basis of a read command (Fig. 37/paragraph 0278, likewise, there is an operation select signal applied to perform a read),
wherein the write circuit cures at least third memory cell of the plurality of memory cells on the basis of a curing command (Fig. 37/paragraph 0278, likewise, there is an operation select signal applied to perform an anneal, which uses the same circuit as the write command).
Regarding claim 32, Bronner teaches the memory apparatus of claim 31, wherein the write circuit provides a write pulse to the at least first memory cell on the basis of the write command (Paragraph 0278, the write command is carried out with the assertion of write voltage V WL_WR), and provides a curing pulse to the at least third memory cell on the basis of the curing command (Paragraph 0215, the annealing is performed by providing current through the memory).
Regarding claim 34, Bronner teaches the memory apparatus of claim 32, wherein the curing command is received from a controller that controls the memory apparatus (Paragraph 0066) when the number of access operations performed on the at least third memory cell exceeds a set number of times, or when the at least third memory cell has an error rate that exceeds a set value (Paragraph 0077, the anneal can be triggered based on an error rate or usage rate exceeding a threshold).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 9, 10, 17 – 19, 29, 30 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Bronner in view of Khwa et al. (US Patent Application Publication 2015/0371704), hereinafter Khwa.
Regarding claim 4, Bronner teaches the memory system of claim 3.
Bronner does not teach that the curing operation further includes providing the first memory cell with a curing pulse with a width longer than a width of a write pulse (Bronner teaches that heat is applied by applying a current, but does not describe details of the pulse).
Khwa teaches a curing operation which further includes providing a memory cell with a curing pulse with a width longer than a width of a write pulse (Fig. 7/paragraph 0084, the HEAL pulse 703 is longer in total than the RESET pulse 702; Paragraph 0085, the total pulse duration is longer).
It would have been obvious to one of ordinary skill in the art to use a curing pulse such as that taught by Khwa when applying the techniques of Bronner to phase-change memory. Bronner explicitly teaches that its techniques can be applied to phase-change memory (Paragraph 0065), but does not teach details related to the unique characteristics of operating phase-change memory. One of ordinary skill in the art would be motivated to use a pulse similar to that of Khwa’s because applying a long, low-current pulse allows one to apply more thermal energy, and thus more healing, to a phase-change memory, without providing excessive current which damages the cell (Khwa paragraph 0085).
Claim 9 recites similar language to claim 4, and is similarly rejected.
Regarding claim 10, Bronner in view of Khwa teaches the memory system of claim 9, wherein an amplitude of the curing pulse is equal to or smaller than an amplitude of the write pulse (Khwa Fig. 7/paragraph 0084, the current of the HEAL waveform is lower than that of the SET and RESET pulses).
Regarding claim 17, Bronner teaches the operation method of claim 16.
Bronner does not teach the operation method of claim 16, wherein a current flows through the first memory cell in a first direction during a set write operation, and
wherein the providing of the curing pulse to the first memory cell comprises causing a current to flow through the first memory cell in the first direction when the data stored in the first memory cell has been determined to be set data (Bronner teaches that heat is applied by applying a current, but does not describe details of the pulse).
Khwa teaches an operation method wherein a current flows through the first memory cell in a first direction during a set write operation (Khwa paragraph 0075, a current is applied through the top to the bottom electrode of the memory to write to it to change between the SET and RESET states), and
wherein the providing of the curing pulse to the first memory cell comprises causing a current to flow through the first memory cell in the first direction (Paragraph 0083, the healing mode uses the same current flow as the read and write modes) when the data stored in the first memory cell has been determined to be set data (Paragraph 0087, a testing pulse is sent to detect the resistance of the cell, i.e. the state of the cell).
It would have been obvious to one of ordinary skill in the art to apply a curing current such as that taught by Khwa when applying the techniques of Bronner to phase-change memory. Bronner explicitly teaches that its techniques can be applied to phase-change memory (Paragraph 0065), but does not teach details related to the unique characteristics of operating phase-change memory. One of ordinary skill in the art would be motivated to apply a current such as Khwa’s because it produces heat which beneficially repairs the cell (Khwa paragraph 0084), and because it allows the writing and healing signals to use the same circuitry (Khwa paragraphs 0082 – 0084), which one of ordinary skill in the art would recognize reduces the need for a dedicated heating element.
Regarding claim 18, Bronner teaches the operation method of claim 16.
Bronner does not teach the operation method of claim 16, wherein a current flows through the first memory cell in a second direction during a reset write operation, nor that the providing of the curing pulse to the first memory cell comprises causing a current to flow through the first memory cell in the second direction when the data stored in the first memory cell has been determined to be reset data (Bronner teaches that heat is applied by applying a current, but does not describe details of the pulse).
Khwa teaches an operation method wherein a current flows through the first memory cell in a second direction during a reset write operation (Khwa paragraph 0075, a current is applied through the top to the bottom electrode of the memory to write to it to change between the SET and RESET states), and
wherein the providing of the curing pulse to the first memory cell comprises causing a current to flow through the first memory cell in the second direction (Paragraph 0083, the healing mode uses the same current flow as the read and write modes) when the data stored in the first memory cell has been determined to be reset data (Paragraph 0087, a testing pulse is sent to detect the resistance of the cell, i.e. the state of the cell).
It would have been obvious to one of ordinary skill in the art to apply a curing current such as that taught by Khwa when applying the techniques of Bronner to phase-change memory. Bronner explicitly teaches that its techniques can be applied to phase-change memory (Paragraph 0065), but does not teach details related to the unique characteristics of operating phase-change memory. One of ordinary skill in the art would be motivated to apply a current such as Khwa’s because it produces heat which beneficially repairs the cell (Khwa paragraph 0084), and because it allows the writing and healing signals to use the same circuitry (Khwa paragraphs 0082 – 0084), which one of ordinary skill in the art would recognize reduces the need for a dedicated heating element.
Regarding claim 19, Bronner teaches the operation method of claim 16.
Bronner does not teach that the curing pulse has a pulse width longer than a width of a write pulse and an amplitude equal to or smaller than an amplitude of the write pulse (Bronner teaches that heat is applied by applying a current, but does not describe details of the pulse.).
Khwa teaches an operation method where the curing pulse has a width longer than a width of a write pulse (Fig. 7/paragraph 0084, the HEAL pulse 703 is longer in total than the RESET pulse 702; Paragraph 0085, the total pulse duration is longer) and an amplitude equal to or smaller than an amplitude of the write pulse (Fig. 7/paragraph 0084, the current of the HEAL waveform is lower than that of the SET and RESET pulses).
It would have been obvious to one of ordinary skill in the art to use a curing pulse such as that taught by Khwa when applying the techniques of Bronner to phase-change memory. Bronner explicitly teaches that its techniques can be applied to phase-change memory (Paragraph 0065), but does not teach details related to the unique characteristics of operating phase-change memory. One of ordinary skill in the art would be motivated to use a pulse similar to that of Khwa’s because applying a long, low-current pulse allows one to apply more thermal energy, and thus more healing, to a phase-change memory, without providing excessive current which damages the cell (Khwa paragraph 0085).
Claim 29 recites similar language to claim 19, and is similarly rejected.
Regarding claim 30, Bronner teaches the operation method of claim 28.
Bronner does not teach that the curing operation comprises providing the second memory cell with a plurality of curing pulses each having an amplitude equal to or smaller than an amplitude of a write pulse, a total sum of the widths of the plurality of curing pulses being longer than a width of the write pulse (Bronner teaches that heat is applied by applying a current, but does not describe details of the pulse.).
Khwa teaches a curing operation for phase-change memory which includes providing a memory cell with a plurality of curing pulses each having an amplitude equal to or smaller than an amplitude of a write pulse (Fig. 7/paragraph 0084, the current of the HEAL waveform is lower than that of the SET and RESET pulses), a total sum of the widths of the plurality of curing pulses being longer than a width of the write pulse (Fig. 7/paragraph 0084, the HEAL pulse 703 is longer in total than the RESET pulse 702; Paragraph 0085, the total pulse duration is longer).
It would have been obvious to one of ordinary skill in the art to use a curing pulse such as that taught by Khwa when applying the techniques of Bronner to phase-change memory. Bronner explicitly teaches that its techniques can be applied to phase-change memory (Paragraph 0065), but does not teach details related to the unique characteristics of operating phase-change memory. One of ordinary skill in the art would be motivated to use a pulse similar to that of Khwa’s because applying a long, low-current pulse allows one to apply more thermal energy, and thus more healing, to a phase-change memory, without providing excessive current which damages the cell (Khwa paragraph 0085).
Claim 33 recites similar language to claim 19, and is similarly rejected.
Claims 5, 11 and 20 – 22 are rejected under 35 U.S.C. 103 as being unpatentable over Bronner and Khwa, further in view of Fantini et al. (US Patent Application Publication 2023/0260576).
Regarding claim 5, Bronner in view of Khwa teaches the method of claim 4, wherein a current flows through the first memory cell in a first direction when the curing pulse is provided to the first memory cell (Khwa paragraph 0075, a current is applied through the top to the bottom electrode of the memory to write to it; Paragraph 0083, the healing mode uses the same current flow as the read and write modes).
Neither Bronner nor Khwa explicitly teach that the curing operation further includes causing a current to flow through the first memory cell in a second direction opposite to the first direction, before providing the curing pulse to the first memory cell (Khwa teaches a testing pulse before performing the operation in paragraph 0087, but simply states that the pulse is a current and does not elaborate on the direction).
Fantini teaches causing a current to flow through the first memory cell in a second direction opposite to the first direction, before providing a write pulse to the first memory cell (Fig. 5, each shown write operation is preceded with a first pulse between t0 and t1. Paragraph 0060 states that this first pulse may be a pre-read pulse which determines the current logic state of the cell).
It would have been obvious to one of ordinary skill in the art that the testing pulse taught by Bronner and Khwa may be in the opposite direction as the curing pulse, in a manner similar to that taught by Fantini. Fantini teaches that the pre-read pulse may also function as a drift cancellation pulse (Paragraph 0069), advantageously making it easier for the memory cell to operate by lowering its threshold voltage by applying an opposite voltage (Paragraph 0061). One of ordinary skill in the art would be motivated to make the testing pulse before the curing pulse of Khwa be in the opposite direction as the curing pulse in order to gain the benefit of easier operation.
Claim 11 recites similar language to claim 5, and is similarly rejected.
Regarding claim 20, Bronner in view of Khwa teaches the operation method of claim 16.
Neither Bronner nor Khwa explicitly teach that providing of the curing pulse to the first memory cell further comprises performing a drift cancellation operation to reduce a threshold voltage of the first memory cell before providing the curing pulse (Khwa teaches a testing pulse before performing the operation in paragraph 0087, but does not explicitly state that the operation reduces a threshold voltage of the memory cell; Bronner teaches that annealing can correct for issues with the threshold voltage in paragraph 0215, but does not explain details specific to phase change memory such as whether the threshold voltage decreases).
Fantini teaches performing a drift cancellation operation to reduce a threshold voltage of the first memory cell before providing the curing pulse (Fig. 5, each shown write operation is preceded with a first pulse between t0 and t1. Paragraph 0060/0061 states that this first pulse may be a drift cancellation pulse which lowers the threshold voltage of the memory cell).
It would have been obvious to one of ordinary skill in the art that the testing pulse taught by Bronner and Khwa may be used as a drift cancellation pulse, in a manner similar to that taught by Fantini. Fantini teaches that the drift cancellation pulse advantageously makes it easier for the memory cell to operate by lowering its threshold voltage (Paragraph 0061). One of ordinary skill in the art would be motivated to make the testing pulse before the curing pulse of Khwa be in the opposite direction as the curing pulse in order to gain the benefit of easier operation.
Regarding claim 21, Bronner in view of Khwa and Fantini teaches the operation method of claim 20, wherein a current flows through the first memory cell in a first direction during a set write operation (Fantini Fig. 5/paragraph 0047, the pulses in the interval t1 – t2 each apply a voltage polarity, it follows that these would induce a current. See Fantini paragraph 0044; Fantini paragraph 0052, the memory cell draws current when it changes state ), and
wherein the performing of the drift cancellation operation comprises causing a current to flow through the first memory cell in a second direction opposite to the first direction when the data is stored in the first memory cell has been determined to be set data (Fantini paragraph 0061, when the memory is in the SET state and programmed using a positive voltage, a negative voltage is applied to mitigate the drift; Fig. 5, the pulses in the intervals t0 – t1 have an opposite polarity to the pulses they precede in intervals t1 – t2).
Regarding claim 22, Bronner in view of Khwa and Fantini teaches the operation method of claim 20, wherein a current flows through the first memory cell in a second direction during a reset write operation (Fantini Fig. 5/paragraph 0047, the pulses in the interval t1 – t2 each apply a voltage polarity, it follows that these would induce a current. See Fantini paragraph 0044; Fantini paragraph 0052, the memory cell draws current when it changes state ), and
wherein the performing of the drift cancellation operation comprises causing a current to flow through the first memory cell in a first direction opposite to the second direction when the data is stored in the first memory cell has been determined to be reset data (Fantini paragraph 0061, an opposite corresponding voltage is applied to apply drift cancellation; Fig. 5, the pulses in the intervals t0 – t1 have an opposite polarity to the pulses they precede in intervals t1 – t2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Khwa is relied upon in this Office action regarding implementation details for phase change memory. Regarding claims 23 – 28, Khwa teaches an “open failure condition” where repairing the memory becomes more difficult in paragraphs 0077 and 0078. Khwa also teaches that a healing operation may be performed at predetermined numbers of usage cycles in paragraph 0092. Khwa is not relied upon with respect to these claims because it does not explicitly teach three thresholds, but is noted for its close similarity to the claims. Although Khwa teaches many aspects of the independent claims, it is relied upon as a secondary reference rather than a primary reference as it is not focused on the high-level decision making regarding managing the curing operations.
Bedeschi et al. (US Patent Application Publication 2023/0395135) and Tu et al. (US Patent Application Publication 2025/0069657) teach details for the operation of phase-change memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN PAI SONG HUANG whose telephone number is (571)272-0510. The examiner can normally be reached Monday - Friday 11:30 AM - 8:30 PM.
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/B.P.H./ Examiner, Art Unit 2114
/JOSEPH R KUDIRKA/ Primary Patent Examiner, Art Unit 2114
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