The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: MEMORY CONTROLLER WITH HOST ACCESSIBLE BAD BLOCK REPORTING AND BACKGROUND OPERATION MANAGMENT.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of US Patent # 11455249 and claims 1-4 of US Patent # 12353328. Although the claims at issue are not identical, they substantially overlap in scope such that the minor differences between the claims correspond to obvious design choice differences which would have been obvious to one of ordinary skill in the art at the time of the invention because they are substantially the same elements recited at least in the independent claims with slight modifications of wording as can be seen in the table below:
Instant application 19234749
US Patent # 11455249
US Patent # 12353328
1. A memory controller for controlling a memory device including a plurality of memory blocks, the memory controller comprising:
a host interface configured to receive a target device initial operation request from a host device; and
a target device dump operation controller configured to provide information on one or more bad blocks of the memory device to the host device
in response to the target device initial operation request.
1. A first memory controller for controlling a first memory device including a plurality of memory blocks, the first memory controller comprising:
a host interface configured to receive bad block information of a second memory device controlled by a second memory controller from a host device,
wherein the bad block information of the second memory device includes physical addresses of bad blocks of the second memory device; and a bad block processor configured to control the first memory device to designate source bad blocks of the first memory device based on the physical addresses of the bad blocks of the second memory device, and to store data stored in the source bad blocks of the first memory device in other memory blocks included in the first memory device, wherein physical addresses of the source bad blocks in the first memory device are the same as the physical addresses of the bad blocks in the second memory device.
4. The memory controller according to claim 2, wherein: the host interface is further configured to receive a source device preparation request from the host device; and the first memory controller further comprises a full-garbage collection operation controller configured to store valid data of the writing-completed memory blocks included in the first memory device in the free blocks in response to the source device preparation request.
1. A first memory controller for controlling a first memory device, comprising:
a host interface configured to receive a source device dump execution request from a host device; and
a dump data chunk generator configured to generate, in response to the source device dump execution request from the host device, a dump data chunk including a data chunk stored in the first memory device and a first physical address indicating a location in a second memory device where the data chunk is to be stored, and to provide the dump data chunk from the first memory device to the host device, wherein the second memory device is controlled by a second memory controller different from the first memory controller, wherein the second memory controller is controlled by the host device, and the second memory controller provides the first physical address to the second memory device without performing a logical-to-physical address translation operation, and wherein the dump data chunk is further provided from the host device to the second memory device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US PGPUB # 20070011395) in view of Morio et al. (US PGPUB # 20160267003 ).
With respect to independent claims 1, 11 Kim discloses: A memory controller for controlling a memory device including a plurality of memory blocks [memory controller for controlling a memory device – Kim 0008-0010, fig 1], the memory controller comprising:
a host interface [controller 210 controls the memory unit 220 and interfaces with the host device 100 - Kim 0026-0027, fig 1] configured to receive a target device initial operation request from a host device [host device requests card capacity (i.e., memory capacity) information from the memory card apparatus such as when the memory card apparatus is connected thereto or when necessary & in response to the request, the memory card apparatus transmits the memory capacity information to the host device - Kim 0007, 0013, 0016, 0033, fig 1]; and
a target device dump operation controller [controller updates available memory capacity information according to occurrence of bad memory in the non-volatile memory and transmits the updated memory capacity information to a host device - Kim abstract; Kim does not explicitly disclose a dump operation, nevertheless in the same field of endeavor Morio teaches a dump operation and control means for executing said dump operation wherein the dump operation may include bad block information – Morio 0018, 00470055, 0059, 0072] configured to provide information on one or more bad blocks of the memory device to the host device [controller updates available memory capacity information according to occurrence of bad memory in the non-volatile memory and transmits the updated memory capacity information to a host device - Kim abstract, 0013] in response to the target device initial operation request [host device requests card capacity (i.e., memory capacity) information from the memory card apparatus such as when the memory card apparatus is connected thereto or when necessary & in response to the request, the memory card apparatus transmits the memory capacity information to the host device - Kim 0007, 0013, 0016, 0033, fig 1; a controller transmitting capacity information of the NAND type flash memory to a host device in response to a request of the host device, wherein the controller updates bad memory capacity information according to occurrence of bad memory block(s) in the NAND type flash memory and reflects the updated bad memory capacity information in the capacity information of the NAND type flash memory - Kim 0013].
Kim does not explicitly teach a dump operation, nevertheless in the same field of endeavor Morio teaches a dump operation and control means for executing said dump operation wherein the dump operation may include bad block information – Morio 0018, 00470055, 0059, 0072.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement a dump operation and control means for executing said dump operation in the invention of Kim as taught by Morio because it would be advantageous for determining and reporting error/fault/bad/malfunction conditions (Morio 0059).
With respect to dependent claim 2, 12 Kim/Morio discloses wherein the information includes one or more physical addresses, each of the physical addresses indicating a location of each of the bad blocks [Morio 0029].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim/Morio in view of Jeong et al. (US PGPUB # 20160132237).
With respect to dependent claim 3 Kim/Morio does not explicitly disclose the limitation(s) of the instant claim. Nevertheless in the same field of endeavor Jeong teaches a completion response upon successfully executing each one of the commands, and stores the resulting completion responses in a buffer, wherein the NVMe controller extracts at least two of the completion responses stored in the buffer to generate a completion packet and transmits the completion packet to the host during a single transaction – Jeong abstract, so that the combination of Kim/Morio/Jeong discloses wherein the target device dump operation controller provides a target device initial operation completion response to the host device [command completion notification for the host - Morio 0040 in view of Jeong abstract]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to provide an operation completion response to the host device in the invention of Kim/Morio as taught by Jeong because it would be advantageous for improving data access performance of the data storage device – Jeong 0005-0006].
Claims 4-5, 10, 15-16, are rejected under 35 U.S.C. 103 as being unpatentable over Kim/Morio in view of Cheon et al. (US PGPUB # 20120246392).
With respect to dependent claim 4, 10, 15 Kim/Morio does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Jeong teaches a buffer memory is configured to temporarily store write data to be written in the flash memory so the combination of Kim/Morio/Cheon discloses a buffer memory device; and a buffer memory controller configured to assign the buffer memory device as an exclusive device for a write operation of storing data to be stored in the memory device [buffer memory is configured to temporarily store write data to be written in the flash memory - CHEON abstract, in other words, the buffer memory is dedicated to (exclusive access) the write path and for write operations & is exclusively used for buffering write data]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use an exclusive write buffer in the invention of Kim/Morio as taught by Cheon because it would be advantageous for optimizing memory/storage performance with benefits of volatile memory (faster access speed) and non-volatile memory (power loss resilience) when writing to memory – Cheon 0004-0005, 0030-0031.
With respect to dependent claim 5, 16, Kim/Morio/Cheon discloses wherein the buffer memory device is a volatile memory device [buffer memory including volatile RAM – Cheon abstract].
Claims 6-7, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim/Morio in view of Horspool et al. (US PGPUB # 20170046256).
With respect to dependent claim 6, 13 Kim/Morio does not explicitly disclose the limitations of the instant claims. Nevertheless in the same field of endeavor Horspool teaches means for stopping background garbage collection. Therefore the combination of Kim/Morio/Horspool teaches a background operation controller configured to deactivate a background operation on the memory device regardless of a request provided from the host device [stop or pause the background garbage collection - Horspool 0030]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to provide means for stopping background garbage collection in the invention of Kim/Morio as taught by Horspool because it would be advantageous for improving system performance and workload potential – Horspool 0006
With respect to dependent claim 7, 14 Kim/Morio/Horspool discloses wherein the background operation comprises one or more of a map update operation, a read reclaim operation, a wear-leveling operation, and a garbage collection operation [Horspool 20170046256 0030 ].
Claim 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Okubo (US PGPUB # 20190095136) in view of Jayaraman (US PGPUB # 20200174940).
With respect to independent claim 8 Okubo/Jayaraman discloses a host interface [host interface 270 may receive a transfer command, wherein a transfer command reads on a dump execution request – Okubo 0068] configured to receive a target device dump execution request and a dump data chunk from a host device [Okubo does not explicitly teach a dump request/indication although Jayaraman teaches a dump request/operation/indications generated by dumping modules in conjunction with controllers/applications acting functionally as a host – Jayaraman 0032, fig 1], the dump data chunk including data chunk [data transfer processing uses physical address to select which data (chunk) to transfer – Okubo 0112 in view of Jayaraman 0032, 0044 & fig 1-3 teaching that data is copied in generated dump chunks from originating cluster to destination cluster, wherein a log identifies where the data is stored (implicitly teaching addressing of dump data – Jayaraman 0004, 0033), also, Okubo teaches initiating a data transfer in response to receiving a request from a host at a storage device - Okubo 0068];
a write data generator configured to generate write data to be stored in the memory device and a physical address based on the dump data chunk [physical addresses correspond to locations where target data is stored – Okubo 0127, 0133, 0135 in view of Jayaraman 0032, 0044 & fig 1-3; host may transfer data to first or second memory devices – Okubo paragraph 0046, fig 4; transferred data may be a ‘dump chuck’ – Jayaraman 0044;], the physical address indicating a location at which the data chunk is to be stored in the memory device [physical addresses correspond to locations where target data is stored – Okubo 0127, 0133, 0135 ]; and
a write operation controller configured to store the write data in an area corresponding to the physical address by controlling the memory device [the transfer unit may select data to be transferred from the first memory to the second memory on a basis of an address related to the writing command – Okubo 0014, 0072].
Okubo does not explicitly disclose a “dump chunk” and requests or generators associated therewith, although the term ‘dump chunk’ is understood within the context of a broadest reasonable interpretation to be a unit or quantity of data such that a dump chunk request is understood to be a data unit transfer/movement/copy/read request and similarly a dump chunk generator is understood to be any functional component capable of generating/producing a unit of data to be involved in a copy/transfer operation.
Nevertheless, in the same field of endeavor Jayaraman teaches “a dump chunk” which may be a variable size amount of data involved in a data transfer/copy operation – Jayaraman 0044.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement a dump chunk in the invention of Okubo as taught by Jayaraman because it would be advantageous for optimizing data transfer based on bandwidth, available storage and other factors associated with data copy/transfer operations (Jayaraman 0044).
With respect to dependent claim 9 Okubo/Jayaraman discloses wherein the host interface provides a target device dump completion response to the host device after the dump data chunk has been stored [store/write completion response – Okubo 0056, 0075, 0130].
With respect to dependent claim 10 Okubo/Jayaraman discloses a buffer memory device; and a buffer memory controller configured to assign the buffer memory device as an exclusive device for a write operation of storing data to be stored in the memory device [each memory cell array 311 and 312 have exclusive data buffers 341 and 342 assigned for facilitating read operations, these are connected to controller interface via memory bus - Okubo fig 6 in view of 0070].
Claim 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim/Morio/Okubo /Jayaraman.
With respect to dependent claim 17 since the instant claims are substantially similar in scope relative to claim 11 & 8, it is rejected according to substantially the same rationale as applied to claims 11 and 8, with minor differences considered.
With respect to dependent claim 18 Okubo/Jayaraman discloses providing target device dump completion response to the host device after the dump data chunk has been stored [store/write completion response – Okubo 0056, 0075, 0130].
With respect to dependent claim 19 Okubo/Jayaraman discloses assigning a buffer memory device as an exclusive device for a write operation of storing data to be stored in the memory device. [each memory cell array 311 and 312 have exclusive data buffers 341 and 342 assigned for facilitating read operations, these are connected to controller interface via memory bus - Okubo fig 6 in view of 0070].
With respect to dependent claim 20 Okubo/Jayaraman discloses wherein the buffer memory device is a volatile memory device [Okubo 0070 in view of Jayaraman 0078, 0081].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee US PGPUB # 20180307625 teaches receiving, at a storage device, a request. The request includes a request message authentication code and write protect information. The write protect information includes at least one of start address information and length information. The start address information indicates a logical block address at which a memory area in a non-volatile memory of the storage device starts, and the length information indicates a length of the memory area. The method also includes generating, at the storage device, a message authentication code based on (1) at least one of the start address information and the length information, and (2) a key stored at the storage device; authenticating, at the storage device, the request based on the generated message authentication code and the request message authentication code; and processing, at the storage device, the request based on a result of the authenticating.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARWAN AYASH whose telephone number is (571)270-1179. The examiner can normally be reached 9a-530p M-R.
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/Marwan Ayash/Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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