Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. Patent US12160496 in view of Yanagishima.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of Patent US12160496 and in view of Yanagishima. Regarding claim 1, see table below.
Instant application 19/235,068
Patent US12160496
Claim 1. A signal transmitter, comprising: a transmission circuit; a reception circuit; and a plurality of insulating elements configured to transmit a plurality of signals, respectively, from the transmission circuit to the reception circuit while insulating between the transmission circuit and the reception circuit, wherein the transmission circuit includes: an oscillator circuit configured to generate a plurality of clock signals having different phases; and a plurality of driving circuits configured to drive the plurality of insulating elements in synchronization with the plurality of clock signals, respectively.
1. A signal transmission device comprising: a first pulse transmitting circuit configured to generate a first transmission pulse signal in synchronization with one of a rising edge and a falling edge of a first reference clock signal; a first pulse receiving circuit configured to receive a first reception pulse signal and generate a second reference clock signal; a first insulation communication circuit configured to transmit the first transmission pulse signal as the first reception pulse signal while insulating between the first pulse transmitting circuit and the first pulse receiving circuit; and a drive clock signal generating circuit configured to generate a drive clock signal having a predetermined oscillation frequency and a predetermined duty or a predetermined pulse width in synchronization with the second reference clock signal.
Regarding claim 1, Patent US12160496 fails to disclose wherein a plurality of driving circuits configured to drive the plurality of insulating elements in synchronization with the plurality of clock signals, respectively.
However, Yanagishima in the same field of endeavor discloses a plurality of driving circuits [222 and 224] configured to drive the plurality of insulating elements [226 and 228] in synchronization with the plurality of clock signals, respectively [fig. 4c-4d showing differing phases of Sa1 and Sa2 with synchronization of 25us].
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. US12160496. Although the claims at issue are not identical, they are not patentably distinct from each other because for claim 1 of the current application, they merely omit features that is recited in the claim 1 of Patent No. US12160496 such as a first pulse receiving circuit configured to receive a first reception pulse signal and generate a second reference clock signal.
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of Patent US12160496 and in view of Yanagishima. Regarding claim 11, see table below.
Instant application 19/235,068
Patent US12160496
11. A signal transmitter, comprising: a transmission circuit; a reception circuit; and a plurality of insulating elements configured to transmit a plurality of signals, respectively, from the transmission circuit to the reception circuit while insulating between the transmission circuit and the reception circuit, wherein the transmission circuit includes: an oscillator circuit configured to generate a clock signal; and a plurality of driving circuits configured to receive electric power from different power supply lines for each of a plurality of groups to which the plurality of driving circuits respectively belong, and to drive the plurality of insulating elements in synchronization with the clock signal.
1. A signal transmission device comprising: a first pulse transmitting circuit configured to generate a first transmission pulse signal in synchronization with one of a rising edge and a falling edge of a first reference clock signal; a first pulse receiving circuit configured to receive a first reception pulse signal and generate a second reference clock signal; a first insulation communication circuit configured to transmit the first transmission pulse signal as the first reception pulse signal while insulating between the first pulse transmitting circuit and the first pulse receiving circuit; and a drive clock signal generating circuit configured to generate a drive clock signal having a predetermined oscillation frequency and a predetermined duty or a predetermined pulse width in synchronization with the second reference clock signal.
Regarding claim 11, Patent US12160496 fails to disclose wherein a plurality of driving circuits configured to receive electric power from different power supply lines for each of a plurality of groups to which the plurality of driving circuits respectively belong, and to drive the plurality of insulating elements in synchronization with the clock signal.
However, Yanagishima in the same field of endeavor discloses a plurality of driving circuits [222 and 224] configured to drive the plurality of insulating elements [226 and 228] in synchronization with the plurality of clock signals, respectively [fig. 4c-4d showing differing phases of Sa1 and Sa2 with synchronization of 25us].
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 19/235,068. Although the claims at issue are not identical, they are not patentably distinct from each other because for claim 1 of the current application, they merely omit features that is recited in the claim 1 of patent/application such as a drive clock signal generating circuit configured to generate a drive clock signal having a predetermined oscillation frequency and a predetermined duty or a predetermined pulse width in synchronization with the second reference clock signal
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 8 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Nishinouchi et al. (US 20240007100 A1 and Nishinouchi hereinafter.) in view of Yanagishima et al. (US 11115020 and Yanagishima hereinafter.).
Regarding claim 1, Nishinouchi disclosing a signal transmitter [fig. 1, para. 10], comprising: a transmission circuit [211]; a reception circuit [223]; and a plurality of insulating elements [transformers 231 and 232 isolating 211 from 223, para. 48] configured to transmit a plurality of signals [S11 and S21, para. 48], respectively, from the transmission circuit to the reception circuit while insulating between the transmission circuit and the reception circuit [para. 41-50],
Nishinouchi does not explicitly disclose the transmission circuit includes: an oscillator circuit configured to generate a plurality of clock signals having different phases; and a plurality of driving circuits configured to drive the plurality of insulating elements in synchronization with the plurality of clock signals, respectively.
However, Yanagishima discloses [fig. 2] the transmission circuit [220a] includes: an oscillator circuit configured to generate a plurality of clock signals [222 and 224 outputting Sa1 and Sa2, col 19 lines 18-22 regarding 222 and 224 constituting a ring oscillator] having different phases [fig. 4c-4d showing differing phases of Sa1 and Sa2]; and a plurality of driving circuits [222 and 224] configured to drive the plurality of insulating elements [226 and 228] in synchronization with the plurality of clock signals, respectively [fig. 4c-4d showing differing phases of Sa1 and Sa2 with synchronization of 25us].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nishinouchi to include the oscillator circuit with differing phase signals to drive the plurality of insulating elements as taught by Yanagishima to improve power consumption in a transmission circuit.
Regarding claim 4, Nishinouchi in view of Yanagishima discloses further wherein the plurality of driving circuits [Yanagishima, 222 and 224] are configured to drive the plurality of insulating elements [Yanagishima, 226 and 228] in synchronization with both a rising edge and a falling edge of each of the plurality of clock signals [Yanagishima, fig. 4c-4d showing pulse signals having rising and falling edges of Sa1 and Sa2 and showing Sa1 and Sa2 with synchronization of 25us].
Regarding claim 5, Nishinouchi in view of Yanagishima discloses further wherein the plurality of driving circuits [Yanagishima, 222 and 224] are supplied with electric power from different power supply lines [Nishinouchi, para. 38, VCC1-GND1 system providing power to 200p and VCC2-GND2 system providing power to 200s] for each of a plurality of groups to which the plurality of driving circuits respectively belong [Yanagishima, fig. 2, 222 driving 226 and 224 driving 228].
Regarding claim 8, Nishinouchi in view of Yanagishima discloses further wherein the oscillator circuit includes a trimming circuit configured to adjust an oscillation frequency of each of the plurality of clock signals [Yanagishima, fig. 4c and 4d showing later pulses R3 and R1 with differing timing than those of A2 and B2, col 21 lines 18-30].
Regarding claim 10, Nishinouchi in view of Yanagishima discloses further wherein each of the plurality of insulating elements is a transformer or a capacitor [Nishinouchi, transformers 231 and 232 isolating 211 from 223, para. 48].
Regarding claim 11, Nishinouchi disclosing a signal transmitter [fig. 1, para. 10], comprising: a transmission circuit [211]; a reception circuit [223]; and a plurality of insulating elements [transformers 231 and 232 isolating 211 from 223, para. 48] configured to transmit a plurality of signals [S11 and S21, para. 48], respectively, from the transmission circuit to the reception circuit while insulating between the transmission circuit and the reception circuit [para. 41-50].
Nishinouchi does not explicitly disclose wherein the transmission circuit includes: an oscillator circuit configured to generate a clock signal;
However, Nishinouchi discloses [fig. 1] signal transmitter 211 accepting an input pulse signal IN to drive 211 [para. 40]. The use of oscillators to provide pulse signals is well known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to use an oscillator to provide input pulse signal IN to improve usability of the signal transmitter.
Nishinouchi discloses further a plurality of driving circuits configured to receive electric power from different power supply lines for each of a plurality of groups to which the plurality of driving circuits respectively belong [para. 38, VCC1-GND1 system providing power to 200p and VCC2-GND2 system providing power to 200s providing power to 212 and 232, driving transformer 231 and 232].
Nishinouchi does not explicitly disclose the driving circuits configured drive the plurality of insulating elements in synchronization with the clock signal.
However, Yanagishima discloses [fig. 2] the driving circuits [222 and 224] configured drive the plurality of insulating elements [226 and 228] in synchronization with the clock signal [fig. 4c-4d showing differing phases of Sa1 and Sa2].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nishinouchi to include the oscillator circuit with differing phase signals to drive the plurality of insulating elements as taught by Yanagishim to improve power consumption in a transmission circuit.
Regarding claim 12, Nishinouchi in view of Yanagishima discloses further a an electronic device, comprising :the signal transmitter of Claim 1 [Nishinouchi, para. 36 and fig. 27].
Regarding claim 13, Nishinouchi in view of Yanagishima discloses further a vehicle, comprising: the electronic device of Claim 12 [Nishinouchi, para. 36 and fig. 27].
Regarding claim 14, Nishinouchi in view of Yanagishima discloses further an insulated gate driver integrated circuit [fig. 7, functional device 60, para. 131 and 134], which is formed by integrating the signal transmitter of Claim 1 [fig. 1, para. 10].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nishinouchi in view of Yanagishima further in view of Takayama et al. (US 7239189 and Takayama hereianfter.).
Regarding claim 2, Nishinouchi in view of Yanagishima discloses all the features regarding claim 1 as indicated above. Nishinouchi in view of Yanagishima does not explicitly disclose wherein the oscillator circuit includes: an oscillator configured to generate a reference clock signal; and a plurality of delay circuits connected in series, wherein the reference clock signal is input to a delay circuit located most upstream among the plurality of delay circuits, and the plurality of clock signals are output from the plurality of delay circuits, respectively.
However, Takayama discloses [fig. 1] wherein the oscillator circuit includes: an oscillator [INPUT CLOCK] configured to generate a reference clock signal [IN1]; and a plurality of delay circuits connected in series [10a1 – 10a4 and 10b1 – 10b4], wherein the reference clock signal is input to a delay circuit located most upstream among the plurality of delay circuits [as shown in fig. 1].
Takayama does not explicitly disclose the plurality of clock signals are output from the plurality of delay circuits, respectively.
However, the use of tapped delay lines is well known in the art.
Therefore, it would have been obvious to one of ordinary skill in the art to provide the individual clock signals by tapping individual outputs of the delay elements in order to improve usability of an oscillator to drive a transmission circuit.
Claims 3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Nishinouchi in view of Yanagishima further in view of Nakashima et al. (US 5703541 and Nakashima hereinafter.).
Regarding claim 3, Nishinouchi in view of Yanagishima discloses all the features regarding claim 1 as indicated above. Nishinouchi in view of Yanagishima does not explicitly disclose wherein the oscillator circuit is a ring oscillator including a plurality of inverters connected in a ring shape, and wherein the plurality of clock signals are output from the plurality of inverters, respectively.
However, Nakashima discloses wherein the oscillator circuit [fig. 1] is a ring oscillator [col 3 lines 34-35] including a plurality of inverters connected in a ring shape [inverters 4 and 5, 11 and 12, 17 and 18 with feedback from output of 17 and 18 back into input of 4 and 5] and wherein the plurality of clock signals are output from the plurality of inverters [fig. 2a – 2e, showing phase offsets of V1, V3 through V2n-1], respectively.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the invention of Nishinouchi in view of Yanagishima to include the ring oscillator as taught by Nakashima to improve usability of a transmission circuit.
Regarding claim 6, Nishinouchi in view of Yanagishima further in view of Nakashima discloses further wherein the plurality of driving circuits [Yanagishima, 222 and 224] are supplied with electric power from different power supply lines [Nishinouchi, para. 38, VCC1-GND1 system providing power to 200p and VCC2-GND2 system providing power to 200s] for each of a plurality of groups to which the plurality of driving circuits respectively belong [Yanagishima, fig. 2, 222 driving 226 and 224 driving 228], and wherein the clock signals output from adjacent inverters among the plurality of inverters [Nakashima, fig. 1, inverters 4 and 5, 11 and 12, 17 and 18 priving clocking signals V1, V3 through V2n-1] are output to driving circuits [Yanagishima, fig. 2 222 and 224] belonging to different groups among the plurality of driving circuits [Yanagishima, fig. 2, 222 driving 226 and 224 driving 228].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Nishinouchi in view of Yanagishima further in view of Pernia et al. (TW 200908561 A and Pernia hereinafter.).
Regarding claim 9, Nishinouchi in view of Yanagishima discloses all the features regarding claim 1 as indicated above. Nishinouchi in view of Yanagishima does not explicitly disclose wherein the oscillator circuit is configured such that an oscillation frequency of each of the plurality of clock signals has a negative temperature characteristic.
However, Pernia discloses [fig. 4, pg. 9 regarding “frequency calibration”] wherein the oscillator circuit is configured such that an oscillation frequency of each of the plurality of clock signals has a negative temperature characteristic [via temperature response compensation module 420].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to include the temperature response compensation module within the ring oscillator circuitry of Yanagishima to improve operating performance of a transmission circuit.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, Fagerhoj et al. (TW 200306086 A and Fagerhoj hereinafter.) discloses [pg. 4, fig. 4] a transmitter 200 comprising a multiplexor 258 accepting a clocking signal from a clock generator 250 and a divided version of the clocking signal via frequency divider 256 and outputting the clocking signal or the divided version of the clocking signal via a selection signal on 207.
However, Fagerhoj does not teach the plurality of multiplexors and dividers nor does it teach driving a plurality of driving circuits configured to drive the plurality of insulating elements.
Furthermore, it would not be obvious to one of ordinary skill in the art to modify the teachings of Nishinouchi in view of Yanagishima to incorporate these missing features.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure, Teramoto (US 20110148477 A1) is cited to teach a transmission and receiving circuit.
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/JAMES G YEAMAN/ Examiner, Art Unit 2836
/TAELOR KIM/ Supervisory Patent Examiner, Art Unit 2836
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